Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsEvaluation board

1181

Filter input

Filter output

Counter

Filter input

Filter output

Counter

preload value

N2HET Functional Description

www.ti.com

23.2.6 Suppression Filters

Each N2HET pin is equipped with a suppression filter. If the pin is configured as an input it enables to filter

out pulses shorter than a programmable duration. Each filter consists of a 10-bit down counter, which

starts counting at a programmable preloaded value and is decremented using the VCLK2 clock.

• The counter starts counting when the filter input signal has the opposite state of the filter output signal.

The output signal is preset to the same input signal state after reset, in order to ensure proper

operation after device reset.

• Once the counter reaches zero without detecting an opposite pin state on the filter input signal, the

output signal is set to the opposite state.

• When the counter detects an opposite pin action on the filter input signal before reaching zero, the

counter is loaded with it's preload value and the opposite pin action on the filter output signal does not

take place. The counter resumes at the preload value until it detects an opposite pin action on the

input signal again.

• Therefore the filter output signal is delayed compared to the filter input signal. The amount of delay

depends on the counter clock frequency (VCLK2) and the programmed preload value.

• The accuracy of the output signal is +/- the counter clock frequency.

Figure 23-26. Suppression Filter Counter Operation

Table 23-11 gives examples for a 100 MHz VCLK2 frequency.

Table 23-11. Pulse Length Examples for Suppression Filter

Possible values for the suppressed pulse length / frequency resulting from the

Divider CCDIV VCLK2 programmable 10 bit preload value (0,1,..,1023)

1 100.0 MHz 10 ns, 20 ns, …, 10.22 µs, 10.23 µs 50 MHz, 25 MHz, …, 48.924 kHz, 48.876 kHz

2 50.0 MHz 20 ns, 40 ns, …, 20.44 µs, 20.48 µs 25 MHz, 12.5 MHz, …, 24.462 kHz, 24.414 kHz

3 33.3 MHz 30 ns, 60 ns, …, 30.66 µs, 30.69 µs 16.7 MHz, 8.3 MHz, …, 16.308 kHz, 16.292 kHz

23.2.7 Interrupts and Exceptions

N2HET interrupts can be generated by any instruction that has an interrupt enable bit in its instruction

format. When the interrupt condition in an instruction is true and the interrupt enable bit of that instruction

is set an interrupt flag is then set in the N2HET Interrupt Flag Register (HETFLG). The address code for

this flag is determined by the five LSBs of the current timer program address. The flag in the N2HET

Interrupt Flag Register (HETFLG) is set even if the corresponding bit in the N2HET Interrupt Enable Set

Enable Set Register (HETINTENAS) must be one. In the N2HET interrupt service routine, the main CPU

must first determine which source inside the N2HET created the interrupt request. This operation is

accelerated by the N2HET Offset Index Priority Level 1 Register (HETOFF1) or N2HET Offset Index

Priority Level 2 Register (HETOFF2) which automatically provide the number of the highest priority source

within each priority level. Reading the offset register will automatically clear the corresponding N2HET

interrupt flag which created the request. However, if the offset registers are not used by the N2HET

interrupt service routine, the flag should be cleared explicitly by the CPU once the interrupt has been

serviced.

960

High-End Timer (N2HET) Module SPNU562–May 2014

Submit Documentation Feedback