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1181

N2HET pin

to other N2HET pin structures

N2HET pin enable

nDIS pin*

*nDIS pin realized by GIOA[5] (N2HET1) and GIOB[2] (N2HET2)

HETPINDIS

HETDIR

HETDIN

HETDOUT

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N2HET Functional Description

23.2.5.16 N2HET Pin Disable Feature

This feature is provided for the safe operation of systems such as power converters and motor drives. It

can be used to inform the monitoring software of motor drive abnormalities such as over-voltage, over-

current, and excessive temperature rise.

Figure 23-25. N2HET Pin Disable Feature Diagram

Table 23-10 shows the conditions for the output buffer to be enabled/disabled.

Table 23-10. N2HET Pin Disable Feature

HETPINDIS.x nDIS Pin (Input) HET PIN ENA (HETGCR.24) HETDIR.x Output Buffer

0 X X 0 Disabled

0 X X 1 Enabled

1 0 X 0 Disabled

1 0 X 1 Disabled

1 1 X 0 Disabled

1 1 0 1 Disabled

1 1 1 1 Enabled

An interrupt capable device I/O pin can share the same pin as the N2HET nDIS signal. Normally GIOA[5]

serves as nDIS for N2HET1 and GIOB[2] as nDIS for N2HET2. Check the device datasheet for the actual

implementation. Sharing a pin with a GIO pin that is Interrupt capable allows the N2HET nDIS input to

also generate an interrupt to the CPU. An active low level on nDIS is intended to signal an abnormal

situation as described above. All N2HET pins, which are selected with the N2HET Pin Disable Register

(HETPINDIS), will be put in the high-impedance state by hardware immediately after the nDIS signal is

pulled low. At this time a CPU interrupt is issued, if it is enabled in the GIO pin logic.

The bit HET PIN ENA is automatically cleared in the failure condition and this state remains as long as the

software explicitly sets the bit again. The steps to do this are:

• Software detects, by reading the HETDIN register of the GIO pin, that the level on nDIS is inactive

(high).

• Software sets bit HET PIN ENA to deactivate the high impedance state of the pins.

959

SPNU562–May 2014 High-End Timer (N2HET) Module

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