Datasheet

Output enable
Data out
Data in
Pull control disable
Pull select
N2HET pin
Pull control
logic
Input enable
HR clock
Loop res
clock
HR counter
HR capt.
reg
WCAP DF
Input pin HET[0]
0 1
2 3 0 1 2 3 0
X
2
X 4
Instruction
CNT WCAP CNT WCAP CNT WCAP CNT WCAP CNT WCAP CNT WCAP
0
A register
1 2 3 4 5 6
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
WCAP
Previous bit
0x0240 captured to WCAP DF [31:0]
LRP
HRP
sync’d to VCLK2
Input pin HET[0]
sampled by LRP
www.ti.com N2HET Functional Description
Figure 23-23. WCAP Instruction Timing
HETPFR_register = 0x0200 --> lr = 4, hr = 1, ts = 4
N2HET Program:
L00 CNT {reg=A, max=01ffffffh}
L01 WCAP {next=L00, cond_addr=L00, hr_lr=high, reg=A, event= FALL, pin=0,
data=0}
In the example, the WCAP is configured to capture the counter when a falling edge occurs. The WCAP
data field (WCAP_DF) is updated in the loop succeeding the loop in which the edge occurred. The WCAP
instruction evaluates an edge by comparing its Previous bit with the sync’d input signal. In Figure 23-23,
the current value of the counter (4) is captured to WCAP_DF[31:7] and the value of the HR capture
register (2) is transferred to the valid bits (according the lr prescaler) of WCAP_DF[6:0]. Therefore, in the
example 0x0240 is captured in WCAP_DF[31:0].
23.2.5.14 I/O Pull Control Feature
Figure 23-24. I/O Block Diagram Including Pull Control Logic
957
SPNU562–May 2014 High-End Timer (N2HET) Module
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