Datasheet

HR clock
Loop res
clock
PCNT CF
HR counter
HR capt.
reg
PCNT DF
Input pin
Input pin
sync’d
X
0 1 2
0 1 2 3 0 1 2 3 0
0
X
3
X 1
1
2
3
HR clock
Loop res
clock
PCNT CF
HR counter
HR capt.
reg
PCNT DF
Input pin
Input pin
sync’d
X
0 1 2
0 1 2 3 0 1 2 3 0
0
X
1
X 2
1 2 3
N2HET Functional Description www.ti.com
Figure 23-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow)
Figure 23-22 shows what happens when the capture edge arrives before the HR counter overflows. This
causes the non-incremented value to be captured by the PCNT instruction.
Figure 23-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow)
23.2.5.13 WCAP Execution Example (in HR Mode)
The HR capability is enabled for WCAP, if its hr_lr bit is zero. In this case the HR counter is always
enabled and is synchronized with the resolution loop. When the specified edge is detected, the current
value of the HR counter is captured in the HR capture register and written into the RAM after the next
WCAP execution. The WCAP instruction effectively time stamps the free running timer saved in a register
(for example, register A shown in Figure 23-23).
956
High-End Timer (N2HET) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated