Datasheet

118
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 6-39. Interrupt Request Assignments (continued)
MODULES VIM INTERRUPT SOURCES
DEFAULT VIM
INTERRUPT CHANNEL
ePWM5INTn ePWM5 Interrupt 98
ePWM5TZINTn ePWM5 Trip Zone Interrupt 99
ePWM6INTn ePWM6 Interrupt 100
ePWM6TZINTn ePWM6 Trip Zone Interrupt 101
ePWM7INTn ePWM7 Interrupt 102
ePWM7TZINTn ePWM7 Trip Zone Interrupt 103
eCAP1INTn eCAP1 Interrupt 104
eCAP2INTn eCAP2 Interrupt 105
eCAP3INTn eCAP3 Interrupt 106
eCAP4INTn eCAP4 Interrupt 107
eCAP5INTn eCAP5 Interrupt 108
eCAP6INTn eCAP6 Interrupt 109
eQEP1INTn eQEP1 Interrupt 110
eQEP2INTn eQEP2 Interrupt 111
Reserved Reserved 112
DCAN4 DCAN4 Level 0 interrupt 113
I2C2 I2C2 interrupt 114
LIN2 LIN2 level 0 interrupt 115
SCI4 SCI4 level 0 interrupt 116
DCAN4 DCAN4 Level 1 interrupt 117
LIN2 LIN2 level 1 interrupt 118
SCI4 SCI4 level 1 interrupt 119
DCAN4 DCAN4 IF3 Interrupt 120
CRC2 CRC2 Interrupt 121
Reserved Reserved 122
Reserved Reserved 123
EPC EPC FIFO FULL or CAM FULL interrupt 124
Reserved Reserved 125-127
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR
entry; therefore only request channels 0..126 can be used and are offset by one address in
the VIM RAM.
NOTE
The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise"
interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt
condition is indicated as soon as the device is powered up. This can be ignored if the
EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used
in the application, then the external slave memory must always drive the EMIF_nWAIT signal
such that an interrupt is not caused due to the default pull-up on this signal.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt
channels.