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1171

HET[0]

HR0

HR1

Asymmetrical

counter

(CNT)

Symmetrical

counter

(not in HET)

N2HET Functional Description

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The following N2HET program gives an example for one channel of the symmetrical PWM. The generated

timing is given in Figure 23-14.

MAXC .equ 22

A_ .equ 0 ; HR structure HR0

B_ .equ 1 ; HR structure HR1

CN CNT { next=EA, reg=A, max=MAXC }

EA ECMP { next=EB, cond_addr=MA, hr_lr=HIGH, en_pin_action=ON, pin=A_,

action=PULSELO, reg=A, data=17, hr_data=115 }

MA MOV32 { next=EB, remote=EA, type=IMTOREG&REM, reg=NONE, data=17, hr_data=19 }

EB ECMP { next=CN, cond_addr=MB, hr_lr=HIGH, en_pin_action=ON, pin=B_,

action=PULSELO, reg=A, data=5, hr_data=13 }

MB MOV32 { next=CN, remote=EB, type=IMTOREG&REM, reg=NONE, data=5, hr_data=13 }

N2HET Settings and output signal calculation for this example program:

• Pin HET[0] and HET[1] are XOR-shared.

• HETPFR[31:0] register = 0x700: lr=128, hr=1, time slots ts = 128

• PWM period (determined by CNT_max field) = (22+1) · LRP = 2944 HRP

• Length of high pulse of (HET[0] XOR HET[1]) =

LH = (17·LRP+115·HRP) - (5·LRP+13·HRP)

With lr=128 there is LRP = 128 · HRP, so

LH = (2291 - 653) · HRP = 1638 HRP

• Duty cycle = DC = LH / PWM_period = 1638 HRP / (2944·HRP) = 55.6 %

Figure 23-14 graphically shows the implementation of the XOR-shared feature. The first 2 waveforms

(symmetrical counter and CNT) show a symmetric counter and asymmetric counter. The symmetric

counter is shown only to highlight the axis of symmetry and is not implemented in the N2HET. The

asymmetric counter, which is implemented with a CNT instruction, needs to be set to the period of the

symmetric counter. The next two waveforms (HR [0] and HR [1]) show the output of the HR structures,

which are the inputs for the XOR gate to create the PWM output on pin HET[0]. Notice that the pulses of

signal HET[0] are centered about the axis of symmetry.

Figure 23-14. Symmetrical PWM with XOR-sharing Output

950

High-End Timer (N2HET) Module SPNU562–May 2014

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