Datasheet

HET[0]

HET[1]

HETXOR0

N2HET HR 0

N2HET HR 1

HET[0]

HET[1]

N2HET

HR 0

N2HET

HR 1

HR share 1/0

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N2HET Functional Description

23.2.5.5 HR Structures Sharing (Input)

The HR Share Control Register (HETHRSH) allows two HR structures to share the same pin for input

capture only. If these bits are set, the HR structures N and N+1 are connected to pin N. In this structure,

pin N+1 remains available for general purpose input/output. See Figure 23-12.

Figure 23-12. Example of HR Structure Sharing for N2HET Pins 0/1

The following program gives an example how the HR share feature (HET[0] HR structure and HET[1] HR

structure shared) can be used for the PCNT instruction:

L00 PCNT { next=L01, type=rise2fall, pin=0 }

L01 PCNT { next=L00, type=fall2rise, pin=1 }

The HET[1] HR structure is also connected to the HET[0] pin. The L00_PCNT data field is able to capture

a high pulse and the L01_PCNT captures a low pulse on the same pin (N2HET [0] pin).

23.2.5.6 AND / XOR-shared HR Structure (Output)

Usually the N2HET design allows only one HR structure to generate HR edges on a pin configured as

output pin. The HETXOR register allows a logical XOR of the output signals of two consecutive HR

structures N (even) and N+1 (odd). See Figure 23-13. In this way, it is possible to generate pulses smaller

than the loop resolution clock since both edges can be generated by two independent HR structures. This

is especially required for symmetrical PWM. See Figure 23-14.

The hardware provides a XOR gate that is connected to the outputs of the HR structure of two

consecutive pins. In this structure, pin N+1 remains available for general purpose input/output.

Figure 23-13. XOR-shared HR I/O

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SPNU562–May 2014 High-End Timer (N2HET) Module

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