Datasheet

4
0 1 2 3 4 0 1
0 1 0
VCLK2
HR Clock
LR Clock
Instruction
Counter
Pin HET[0]
Z-Flag
LRP
HRP
25-bit ECMP
match
Pin action in next
loop resolution cycle
CNT resets
Sets Z-Flag
Opposite Pin action in
next loop resolution
cycle
1 1 1 1 1
10 0 0 0 0
Timer data in
HET[x]
Loop
Resolution
Clock
Timer data out
HETDIR
HETDIN
HETDOUT
HETDSET
HETDCLR
www.ti.com N2HET Functional Description
Figure 23-9. N2HET Loop Resolution Structure for Each Bit
The example in Figure 23-10 shows a simple PWM generation with loop resolution accuracy. The
corresponding program is:
HETPFR[31:0] register = 0x201 --> lr=4 and hr=2 --> ts = 8
N2HET Program:
L00 CNT { next= L01, reg=A, irq=OFF, max = 4 }
L01 ECMP { next= L00, cond_addr= L00, hr_lr=LOW, en_pin_action=ON, pin=0,
action=PULSEHI, reg=A, irq=OFF, data= 1, hr_data = 0x0 }
; 25 bit compare value is 1 and the 7-bit HR compare value is 0
The CNT and ECMP instructions are executed once each loop resolution cycle. When the CNT instruction
is executed, the specified register (A) and the CNT instruction data field are both incremented by one.
Next the ECMP is executed and the data field of the ECMP is compared with the specified register (A). If
both values match, then the pin action (PULSEHI in this case) will be performed in the next loop resolution
cycle. The CNT continues incrementing each loop resolution cycle. When the data field overflows (max +
1), then the Z-flag is set by the CNT instruction. In the next loop resolution cycle, the Z-flag is evaluated
and the opposite pin action is performed if it is set. The Z-flag will only be active for one loop resolution
cycle.
Figure 23-10. Loop Resolution Instruction Execution Example
947
SPNU562–May 2014 High-End Timer (N2HET) Module
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