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1161

N2HET Functional Description

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There are lr high resolution clock periods (HRP) within the N2HET loop resolution clock period (LRP). If lr

= 128 then the HR delay can range from 0 to127 HRP clocks within LRP and all 7 bits of the HR data field

are needed. Instead of being limited to measuring and triggering events based on the loop resolution clock

period (LRP) the HR extension allows measurements and events to be described in terms fractions of an

LRP (down to 1/128 of an LRP). The only limitation is that a maximum of one HR delay can be specified

per pin during each loop resolution period.

Table 23-6 shows which bits of the HR data field are not used by the high resolution IO structures if lr is

less than 128. In this case the non-relevant bits (LSBs) of the HR data fields will be one of the following:

• Written as 0 for HR capture (for PCNT, WCAP)

• Or interpreted as 0 for HR compare (for ECMP, MCMP. PWCNT)

Table 23-6. Interpretation of the 7-Bit HR Data Field

Bits of the HR data field

(1)

Loop Resolution

Prescale divide rate (lr) D[6] D[5] D[4] D[3] D[2] D[1] D[0] HRP Cycles delay range

1 X X X X X X X 0

2 1/2 X X X X X X 0 to 1

4 1/2 1/4 X X X X X 0 to 3

8 1/2 1/4 1/8 X X X X 0 to 7

16 1/2 1/4 1/8 1/16 X X X 0 to 15

32 1/2 1/4 1/8 1/16 1/32 X X 0 to 31

64 1/2 1/4 1/8 1/16 1/32 1/64 X 0 to 63

128 1/2 1/4 1/8 1/16 1/32 1/64 1/128 0 to 127

(1)

X = Non-relevant bit (treated as '0')

23.2.3.2.1 Example:

Prescale Factor Register (HETPFR) = 0x0300

—> lr = 8 —> LRP = 8 · HRP

Assumption: HR data field = 0x50 = 1010000b

lr = 8 —> Bits D[3:0] are ignored —> HR delay = 101b = 5 HRPs

or by using the calculation with weight factors:

HR Delay

= lr · (D[6] · 1/2 + D[5] · 1/4 + D[4] · 1/8 + D[3] · 1/16 + D[2] · 1/32 + D[1] · 1/64 + D[0] · 1/128)

= 8 · (1 · 1/2 + 0 · 1/4 + 1 · 1/8 + 0 · 1/16 + 0 · 1/32 + 0 · 1/64 + 0 · 1/128)

= 5 HRPs

23.2.4 Host Interface

The host interface controls all communications between timer-RAM and masters accessing the N2HET

RAM. It includes following components:

23.2.4.1 Host Accesses to N2HET RAM

The host interface supports the following types of accesses to N2HET RAM:

• Read accesses of 8, 16, or 32 bits

• Read accesses of 64-bits that follow the shadow register sequence described in Section 23.2.4.2.

• Write accesses of 32 bits

Writes of 8 or 16 bits to N2HET RAM by an external host are not supported.

944

High-End Timer (N2HET) Module SPNU562–May 2014

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