Datasheet
hr = 2 HRP
hr
VCLK2
--------------------
2
32MHz
------------------= = =
lr =128
lr x HRP = 128 x 62.5ns = 8 sμ
ts = hr x lr = 2 x 128 = 256
hr = 2, lr = 128
HETPFR[31:0] = 0x00000701
62.5ns
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N2HET Functional Description
5. LRP = loop resolution clock period LRP = lr · HRP (ns)
The loop resolution period (LRP) must be selected to be larger than the number of Time slots (VCLK2
cycles) required to complete the worst-case execution path through the N2HET program. Otherwise a
program overflow condition may occur (see Section 23.2.1.4). Because of the relationship of time slots to
the hr and lr prescalers as described in item 3 above, increasing either hr or lr increases the number of
time slots available for program execution. However, lr would typically be increased first, since increasing
hr results in a decrease in timer resolution since it reduces the clock to the High Resolution IO structures.
The divide rates hr and lr can be defined in the HETPFR register. Table 23-5 lists the bit field encodings
for the prescale options.
Table 23-5. Prescale Factor Register Encoding
LRPFC - Loop Resolution HRPFC - High Resolution
HETPFR[10:8] Prescale Factor lr HETPFR[5:0] Prescale Factor hr
000 /1 000000 /1
001 /2 000001 /2
010 /4 000010 /3
011 /8 000011 /4
100 /16 : :
101 /32 111101 /62
110 /64 111110 /63
111 /128 111111 /64
23.2.3.1 Determining Loop Resolution
As an example, consider an application that requires high resolution of HRP = 62.5 ns, and loop resolution
of LRP = 8 μs, and needs at least 250 time slots for the N2HET application program.
Assuming VCLK2 = 32 MHz, the following shows which divide-by rates and which value in the Prescale
Factor Register (HETPFR) is required for the above requirements:
(31)
In the example above, if the loop resolution period needs to decrease from 8 μs to 4 μs, then only 128
time slots will be available for program execution. The program may need to be restructured as suggested
in Section 23.2.1.6.
23.2.3.2 The 7-Bit HR Data Field
The instruction execution examples of ECMP (Section 23.2.5.9), MCMP (Section 23.2.5.10), PCNT
(Section 23.2.5.12), PWCNT (Section 23.2.5.11), and WCAP (Section 23.2.5.13) show that the 7-bit HR
data field can generate or measure high resolution delays (HR delay) relative to the start of an LRP within
one N2HET loop LRP. The last section showed that:
LRP = lr × HRP
943
SPNU562–May 2014 High-End Timer (N2HET) Module
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