Datasheet

HR
prescaler
Loop resolution
prescaler
(3 bits)
(6 bits)
VCLK2
Loop resolution
clock
HR
clock
N2HET Functional Description www.ti.com
Table 23-4. N2HET Parity Bit Mapping (continued)
Bits
Address Address
N2HET1 N2HET2 [31:1] [0]
0xFF46_200C 0xFF44_200C Reads 0, Writes have no effect Read 0
0xFF46_2010 0xFF44_2010 Reads 0, Writes have no effect Instruction 1 Program Field Parity Bit
.... .... ... ...
Each 32-bit N2HET field has its own parity bit in the N2HET Parity RAM as shown in Table 23-4. There
are no parity bits for the reserved fields, since there is no physical N2HET RAM for these fields.
23.2.2.5 Initialization of Parity RAM
After device power up, the N2HET RAM contents including the parity bits cannot be guaranteed. In order
to avoid false parity failures due to the random state in which RAM powers up, the RAM has to be
initialized.
Before initializing the N2HET RAM, enable the N2HET parity logic by writing to HETPCR. Then the
N2HET Instruction RAM should be initialized. With parity enabled, the N2HET parity RAM will be initialized
automatically by N2HET at the same time that the N2HET instruction RAM is initialized by the CPU. Note
that loading the N2HET program with parity enabled is also effective.
Another possibility to initialize the N2HET memory and its parity bits is, to use the system module to start
the automatic initialization of all RAMs on the microcontroller. The RAMs will be initialized to ‘0’.
Depending on the even/odd parity selection, the parity bit will be calculated accordingly.
23.2.3 Time Base
All N2HET timings are derived from VCLK2 (see Figure 23-7). Internally N2HET instructions execute at
the VCLK2 rate; but the timer loop clock and the high-resolution hardware timer clock can be scaled down
from VCLK2. Two prescalers are available to adjust the timer loop resolution clock for the program loop,
and the high resolution (HR) clock for the HR I/O counters.
• Time Slots: The number of cycles available for instruction execution per loop. Time Slots is the
number of VCLK2 cycles in a Loop Resolution Clock.
• High Resolution Clock: The high resolution clock is the smallest time increment with which a pin can
change it’s state or can be measured in the case of input signals. A 6-bit prescaler dividing VCLK2 by
a user-defined HR prescale divide rate (hr) stored in the 6-bit HR prescale factor code (HETPFR). See
Table 23-5.
• Loop Resolution Clock: The loop resolution clock defines the timebase for executing all instructions
in a N2HET program. Since instructions can be conditionally executed, the longest path through the
N2HET program must fit into one loop resolution clock period (LRP).A 3-bit prescaler dividing the HR
clock by a user-defined loop-resolution prescale divide rate (lr) stored in the 3-bit loop-resolution
prescale factor code (HETPFR). See Table 23-5.
Figure 23-7. Prescaler Configuration
The following abbreviations and relations are used in this document:
1. hr: high resolution prescale factor (1, 2, 3, 4,..., 63, 64)
2. lr: loop resolution prescale factor (1, 2, 4, 8, 16, 32, 64,128)
3. ts: Time slots (cycles) available for instruction execution per loop. ts = hr x lr
4. HRP = high resolution clock period HRP = hr · T
VCLK2
(ns)
942
High-End Timer (N2HET) Module SPNU562–May 2014
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