Datasheet

www.ti.com N2HET Functional Description
Even or odd parity selection for N2HET parity detection can be configured in the system module. Parity
calculation and checking can be enabled/disabled by a 4-bit key in HETPCR.
During a read access to the N2HET RAM, the parity is calculated based on the data read from the RAM
and compared with the good parity value stored in the parity bits. The parity check is performed when the
N2HET execution unit makes a read access to N2HET RAM, but also when a different master (for
example, CPU, HTU, DMA) performs the read access. If any 32-bit-word fails the parity check then an
error is signaled to the ESM module. The N2HET address, which generated the error is detected and is
captured in HETPAR for host system debugging. The address is frozen from being updated until it is read
by the bus master.
The N2HET execution unit reads the instructions, which are 96-bit wide. They contain the program-,
control- and data-field whereby each is 32-bit wide. So when fetching N2HET instructions parity checking
is performed on three words in parallel.
If a parity error is detected in two or more words in the same cycle then only one address (word at the
lower address) is captured. The captured N2HET address is always aligned to a 32-bit word boundary.
During debug, parity checking is still performed on accesses originating from the on-chip host CPU and
DMA. However, parity errors that are detected during an access initiated by the debugger itself are
ignored.
23.2.2.3 Parity Error Detection Actions
Detection of a N2HET parity error causes the following actions:
1. An error is signaled to the ESM module.
2. The Parity Address Register (HETPAR) is loaded with the address of the faulty N2HET field.
3. N2HET execution immediately stops. (The instruction that triggered the parity error is not executed.)
4. The Turn-On/Off-Bit in the N2HET Global Configuration Register (HETGCR) is automatically cleared.
5. All N2HET internal flags are cleared.
6. All N2HET pins selected by N2HET Parity Pin Register (HETPPR) enter a predefined safe state.
7. Register HETDOUT is also updated to reflect changes in pin state due to HETPPR.
The safe state for N2HET pins selected through the HETPPR register depends on how the pin is
configured in the HETDIR, HETPDR, and HETPSL registers. Table 23-3 explains how the safe state is
determined.
Table 23-3. Pin Safe State Upon Parity Error Detection
Safe State HETDIR HETPDR HETPSL
Drive Low 1 0 0
Drive High 1 0 1
High Impedance 1 1 x
23.2.2.4 Testing Parity Detection Logic
To test the parity detection logic, the parity RAM has to be made accessible to the CPU in order to allow a
diagnostic program to insert parity errors. The control register bit HETPCR.TEST must be set in order to
make the parity RAM accessible. Once HETPCR.TEST is set, the parity bits are accessible as described
in Table 23-4.
Table 23-4. N2HET Parity Bit Mapping
Bits
Address Address
N2HET1 N2HET2 [31:1] [0]
0xFF46_2000 0xFF44_2000 Reads 0, Writes have no effect Instruction 0 Program Field Parity Bit
0xFF46_2004 0xFF44_2004 Reads 0, Writes have no effect Instruction 0 Control Field Parity Bit
0xFF46_2008 0xFF44_2008 Reads 0, Writes have no effect Instruction 0 Data Field Parity Bit
941
SPNU562–May 2014 High-End Timer (N2HET) Module
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