Datasheet

VIM1
VIM2
Interrupt
Requests
PCR
R5F-0
R5F-1
nIRQ/nFIQ/IRQVECADDR
2 cyc
delay
CCM-R5F
ESM
2 cyc
delay
Cortex-R5 Processor Group
2 cyc
delay
2 cyc
delay
115
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
6.15 Vectored Interrupt Manager
There are two on-chip Vector Interrupt Manager (VIM) modules. The VIM module provides hardware
assistance for prioritizing and controlling the many interrupt sources present on a device. Interrupts are
caused by events outside of the normal flow of program execution. Normally, these events require a timely
response from the CPU; therefore, when an interrupt occurs, the CPU switches execution from the normal
program flow to an interrupt service routine (ISR).
6.15.1 VIM Features
The VIM module has the following features:
• Supports 128 interrupt channels
• Provides programmable priority for the request lines
• Manages interrupt channels through masking
• Prioritizes interrupt channels to the CPU
• Provides the CPU with the address of the interrupt service routine (ISR) for each interrupt
The two VIM modules are in lockstep. These two VIM modules are memory mapped to the same address
space. From a programmer’s model point of view it is only one VIM module. Writes to VIM1 registers and
memory will be broadcasted to both VIM1 and VIM2. Reads from VIM1 will only read the VIM1 registers
and memory. All interrupt requests which go to the VIM1 module will also go to the VIM2 module.
Because the VIM1 and VIM2 have the identical setup, both will result in the same output behavior
responding to the same interrupt requests. The second VIM module acts as a diagnostic checker module
against the first VIM module. The output signals of the two VIM modules are routed to CCM-R5F module
and are compared constantly. Mis-compare detected will be signaled as an error to the ESM module. The
lockstep VIM pair takes care of the interrupt generation to the lockstep R5F pair.
6.15.2 Interrupt Generation
To avoid common mode failures the input and output signals of the two VIMs are delayed in a different
way as shown in Figure 6-17.
Figure 6-17. Interrupt Generation