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22.3.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR)
ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) is shown in Figure 22-95 and described
in Table 22-70.
Figure 22-95. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) [offset = 178h]
31 9 8 0
Reserved G1_RAM_ADDR
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-70. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reads return zeros, writes have no effect.
8-0 G1_RAM_ADDR Group1 results memory write pointer. This field shows the address of the location where the next
Group1 conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Group1 conversion results
available until that time.
22.3.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR)
ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) is shown in Figure 22-96 and described
in Table 22-71.
Figure 22-96. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) [offset = 17Ch]
31 9 8 0
Reserved G2_RAM_ADDR
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-71. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reads return zeros, writes have no effect.
8-0 G2_RAM_ADDR Group2 results memory write pointer. This field shows the address of the location where the next
Group2 conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Group2 conversion results
available until that time.
921
SPNU562–May 2014 Analog To Digital Converter (ADC) Module
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