Datasheet

ADC Registers

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22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)

ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) is shown in Figure 22-81 and

described in Table 22-58.

Figure 22-81. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)

[offset = 120h]

31 16

Reserved

R-0

15 8 7 1 0

G1_SAMP_DIS_CYC Reserved G1_SAMP_

DIS_EN

R/W-0 R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-58. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)

Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Reads return zeros, writes have no effect.

15-8 G1_SAMP_DIS_CYC Group1 sample cap discharge cycles. These bits specify the duration in terms of ADCLK cycles

for which the ADC internal sampling capacitor is allowed to discharge before sampling the input

channel voltage.

7-1 Reserved 0 Reads return zeros, writes have no effect.

0 G1_SAMP_DIS_EN Group1 sample cap discharge enable.

Any operation mode read/write:

0 Group1 sample cap discharge mode is disabled.

1 Group1 sample cap discharge mode is enabled. The ADC internal sampling capacitor is

connected to the V

REFLO

reference voltage for a duration specified by the G1_SAMP_DIS_CYC

field. After this discharge time has expired the selected ADC input channel is sampled and

converted normally based on the Group1 settings.

912

Analog To Digital Converter (ADC) Module SPNU562–May 2014

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