Datasheet

EMIF_CLK
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
1
2 2
4
6
8
8
12
10
16
3
5
7
7
11
13
15
9
BASIC SDRAM
WRITE OPERATION
EMIF_CS[0]
EMIF_DQM[1:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
113
RM57L843
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
6.14.2.5 Write Timing (Synchronous RAM)
Figure 6-16. Basic SDRAM Write Operation
EMIF Synchronous Memory Timing
Table 6-37. EMIF Synchronous Memory Timing Requirements
NO. MIN MAX UNIT
19 t
su(EMIFDV-EM_CLKH)
Input setup time, read data valid on
EMIF_DATA[15:0] before EMIF_CLK rising
1 ns
20 t
h(CLKH-DIV)
Input hold time, read data valid on
EMIF_DATA[15:0] after EMIF_CLK rising
2.2 ns
Table 6-38. EMIF Synchronous Memory Switching Characteristics
NO. PARAMETER MIN MAX UNIT
1 t
c(CLK)
Cycle time, EMIF clock EMIF_CLK 10 ns
2 t
w(CLK)
Pulse width, EMIF clock EMIF_CLK high or low 3 ns
3 t
d(CLKH-CSV)
Delay time, EMIF_CLK rising to EMIF_nCS[0] valid 7 ns
4 t
oh(CLKH-CSIV)
Output hold time, EMIF_CLK rising to EMIF_nCS[0] invalid 1 ns
5 t
d(CLKH-DQMV)
Delay time, EMIF_CLK rising to EMIF_nDQM[1:0] valid 7 ns
6 t
oh(CLKH-DQMIV)
Output hold time, EMIF_CLK rising to EMIF_nDQM[1:0] invalid 1 ns
7 t
d(CLKH-AV)
Delay time, EMIF_CLK rising to EMIF_ADDR[21:0] and EMIF_BA[1:0]
valid
7 ns
8 t
oh(CLKH-AIV)
Output hold time, EMIF_CLK rising to EMIF_ADDR[21:0] and
EMIF_BA[1:0] invalid
1 ns
9 t
d(CLKH-DV)
Delay time, EMIF_CLK rising to EMIF_DATA[15:0] valid 7 ns