Datasheet

ADC Registers
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22.3.29 ADC Group1 Status Register (ADG1SR)
ADC Group1 Status Register (ADG1SR) is shown in Figure 22-51 and described in Table 22-35.
Figure 22-51. ADC Group1 Status Register (ADG1SR) [offset = 70h]
31 8
Reserved
R-0
7 4 3 2 1 0
Reserved G1_MEM_ G1_BUSY G1_STOP G1_END
EMPTY
R-0 R-1 R-0 R-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-35. ADC Group1 Status Register (ADG1SR) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return zeros, writes have no effect.
3 G1_MEM_EMPTY Group1 Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Group1 results memory in the "read from FIFO" mode.
Any operation mode read:
0 The Group1 results memory has valid conversion results.
1 The Group1 results memory is empty, or does not contain any unread conversion results.
2 G1_BUSY Group1 Conversion Busy.
Any operation mode read:
0 Group1 conversions are neither in progress nor frozen.
1 Group1 conversions are either in progress, or are frozen for servicing some other group. This
bit will always be set when the Group1 is configured to be in the continuous conversion mode.
1 G1_STOP Group1 Conversion Stopped.
Any operation mode read:
0 Group1 conversions are not currently frozen.
1 Group1 conversions are currently frozen.
0 G1_END Group1 Conversions Ended.
Any operation mode read:
0 Group1 conversions have either not been started or have not yet completed since the last time
this status bit was cleared.
1 The conversion for all the channels selected in the Group1 has completed. This bit can be
cleared under the following conditions:
By reading a conversion result from the Group1 results memory in the "read from FIFO"
mode.
By writing a new value to the Group1 channel select register (ADG1SEL).
By writing a 1 to this bit.
By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).
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Analog To Digital Converter (ADC) Module SPNU562May 2014
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