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ADC Registers

22.3.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)

ADC Event Group Sampling Time Configuration Register (ADEVSAMP) is shown in Figure 22-47 and

described in Table 22-31.

Figure 22-47. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) [offset = 60h]

31 12 11 0

Reserved EV_ACQ

R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-31. ADC Event Group Sampling Time Configuration Register (ADEVSAMP)

Field Descriptions

Bit Field Value Description

31-12 Reserved 0 Reads return zeros, writes have no effect.

11-0 EV_ACQ Event Group Acquisition Time. These bits define the sampling window (SW) for the Event Group

conversions.

SW = EV_ACQ + 2 in terms of ADCLK cycles.

There are two factors that determine the minimum sampling window value required:

First, the ADC module design requires that SW >= 3 ADCLK cycles.

Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to be

guaranteed by configuring the EV_ACQ value properly considering the frequency of the ADCLK

signal. Refer to the device datasheet to determine the minimum sampling time for this device.

22.3.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP)

ADC Group1 Sampling Time Configuration Register (ADG1SAMP) is shown in Figure 22-48 and

described in Table 22-32.

Figure 22-48. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) [offset = 64h]

31 12 11 0

Reserved G1_ACQ

R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-32. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) Field Descriptions

Bit Field Value Description

31-12 Reserved 0 Reads return zeros, writes have no effect.

11-0 G1_ACQ Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions.

SW = G1_ACQ + 2 in terms of ADCLK cycles.

There are two factors that determine the minimum sampling window value required:

First, the ADC module design requires that SW >= 3 ADCLK cycles.

Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to be

guaranteed by configuring the G1_ACQ value properly considering the frequency of the ADCLK

signal. Refer to the device datasheet to determine the minimum sampling time for this device.

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SPNU562–May 2014 Analog To Digital Converter (ADC) Module

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