Datasheet

ADC Registers

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Table 22-27. ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions (continued)

Bit Field Value Description

0 G1_DMA_EN Group1 DMA Transfer Enable.

Any operation mode read:

0 ADC module does not generate a DMA request when it writes the conversion result to the

Group1 memory.

1 ADC module generates a DMA transfer when the ADC has written to the Group1 memory. The

G1_BLK_XFER bit must be cleared to 0 for this DMA request to be generated.

886

Analog To Digital Converter (ADC) Module SPNU562–May 2014

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