Datasheet

111
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Table 6-36. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
(continued)
NO. PARAMETER MIN TYP MAX UNIT
4 t
su(EMCEL-EMOEL)
Output setup time, EMIF_nCS[4:2] low to
EMIF_nOE low (SS = 0)
(RS)*E-3 (RS)*E (RS)*E+3 ns
Output setup time, EMIFnCS[4:2] low to
EMIF_nOE low (SS = 1)
–3 0 3 ns
5 t
h(EMOEH-EMCEH)
Output hold time, EMIF_nOE high to
EMIF_nCS[4:2] high (SS = 0)
(RH)*E -4 (RH)*E (RH)*E + 3 ns
Output hold time, EMIF_nOE high to
EMIF_nCS[4:2] high (SS = 1)
–4 0 3 ns
6 t
su(EMBAV-EMOEL)
Output setup time, EMIF_BA[1:0] valid to
EMIF_nOE low
(RS)*E-3 (RS)*E (RS)*E+3 ns
7 t
h(EMOEH-EMBAIV)
Output hold time, EMIF_nOE high to
EMIF_BA[1:0] invalid
(RH)*E-4 (RH)*E (RH)*E+3 ns
8 t
su(EMBAV-EMOEL)
Output setup time, EMIF_ADDR[21:0] valid to
EMIF_nOE low
(RS)*E-3 (RS)*E (RS)*E+3 ns
9 t
h(EMOEH-EMAIV)
Output hold time, EMIF_nOE high to
EMIF_ADDR[21:0] invalid
(RH)*E-4 (RH)*E (RH)*E+3 ns
10 t
w(EMOEL)
EMIF_nOE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns
EMIF_nOE active low width (EW = 1) (RST+EWC) *E-3 (RST+EWC)*E (RST+EWC) *E+3 ns
11 t
d(EMWAITH-EMOEH)
Delay time from EMIF_nWAIT deasserted to
EMIF_nOE high
3E-3 4E 4E+5 ns
29 t
su(EMDQMV-EMOEL)
Output setup time, EMIF_nDQM[1:0] valid to
EMIF_nOE low
(RS)*E-5 (RS)*E (RS)*E+3 ns
30 t
h(EMOEH-EMDQMIV)
Output hold time, EMIF_nOE high to
EMIF_nDQM[1:0] invalid
(RH)*E-4 (RH)*E (RH)*E+5 ns
Writes
15 t
c(EMWCYCLE)
EMIF write cycle time (EW = 0) (WS+WST+WH)* E-3 (WS+WST+WH)*E (WS+WST+WH)* E+3 ns
EMIF write cycle time (EW = 1)
(WS+WST+WH+
EWC)*E -3
(WS+WST+WH+
EWC)*E
(WS+WST+WH+
EWC)*E + 3
ns
16 t
su(EMCEL-EMWEL)
Output setup time, EMIF_nCS[4:2] low to
EMIF_nWE low (SS = 0)
(WS)*E -3 (WS)*E (WS)*E + 3 ns
Output setup time, EMIF_nCS[4:2] low to
EMIF_nWE low (SS = 1)
–3 0 3 ns
17 t
h(EMWEH-EMCEH)
Output hold time, EMIF_nWE high to
EMIF_nCS[4:2] high (SS = 0)
(WH)*E-3 (WH)*E (WH)*E+3 ns
Output hold time, EMIF_nWE high to
EMIF_CS[4:2] high (SS = 1)
–3 0 3 ns
18 t
su(EMDQMV-EMWEL)
Output setup time, EMIF_nDQM[1:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
19 t
h(EMWEH-EMDQMIV)
Output hold time, EMIF_nWE high to
EMIF_nDQM[1:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns
20 t
su(EMBAV-EMWEL)
Output setup time, EMIF_BA[1:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
21 t
h(EMWEH-EMBAIV)
Output hold time, EMIF_nWE high to
EMIF_BA[1:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns
22 t
su(EMAV-EMWEL)
Output setup time, EMIF_ADDR[21:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
23 t
h(EMWEH-EMAIV)
Output hold time, EMIF_nWE high to
EMIF_ADDR[21:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns
24 t
w(EMWEL)
EMIF_nWE active low width (EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns
EMIF_nWE active low width (EW = 1) (WST+EWC) *E-3 (WST+EWC)*E (WST+EWC) *E+3 ns
25 t
d(EMWAITH-EMWEH)
Delay time from EMIF_nWAIT deasserted to
EMIF_nWE high
3E+3 4E 4E+14 ns
26 t
su(EMDV-EMWEL)
Output setup time, EMIF_DATA[15:0] valid to
EMIF_nWE low
(WS)*E-3 (WS)*E (WS)*E+3 ns
27 t
h(EMWEH-EMDIV)
Output hold time, EMIF_nWE high to
EMIF_DATA[15:0] invalid
(WH)*E-3 (WH)*E (WH)*E+3 ns