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ADC Registers

22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)

ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in Figure 22-33 and

described in Table 22-17.

Figure 22-33. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) [offset = 28h]

31 8

Reserved

R-0

7 4 3 2 1 0

Reserved EV_END_ Reserved EV_OVR_ EV_THR_

INT_EN INT_EN INT_EN

R-0 R/W-0 R-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-17. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions

Bit Field Value Description

31-4 Reserved 0 Reads return zeros, writes have no effect.

3 EV_END_INT_EN Event Group Conversion End Interrupt Enable. Refer to Section 22.2.3.1 for more details on the

conversion end interrupts.

Any operation mode read/write:

0 No interrupt is generated when conversion of all the channels selected for conversion in the

Event Group is done.

1 An Event Group conversion end interrupt is generated when conversion of all the channels

selected for conversion in the Event Group is done.

2 Reserved 0 Reads return zeros, writes have no effect.

1 EV_OVR_INT_EN Event Group Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries

to write a new conversion result to the Event Group results memory which is already full. For

more details on the overrun interrupts, refer to Section 22.2.3.3.

Any operation mode read/write:

0 No interrupt is generated if an Event Group memory overrun occurs.

1 An Event Group memory overrun interrupt is generated if an Event Group memory overrun

condition occurs.

0 EV_THR_INT_EN Event Group Threshold Interrupt Enable. An Event Group threshold interrupt occurs when the

programmed Event Group threshold counter counts down to zero. Refer to Section 22.2.3.2 for

more details.

Any operation mode read/write:

0 No interrupt is generated if the Event Group threshold counter reaches zero.

1 An Event Group threshold interrupt is generated if the Event Group threshold counter reaches

zero.

875

SPNU562–May 2014 Analog To Digital Converter (ADC) Module

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