Datasheet

EMIF_nCS[3:2]
25
Asserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nWE
EMIF_WAIT
SETUP
Extended Due to EMIF_WAIT
28
Deasserted
STROBE STROBE HOLD
110
RM57L843
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(1) E = EMIF_CLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure 6-12 and Figure 6-14 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Figure 6-14. EMIFnWAIT Write Timing Requirements
6.14.2.3 EMIF Asynchronous Memory Timing
Table 6-35. EMIF Asynchronous Memory Timing Requirements
(1)
NO. MIN NOM MAX UNIT
Reads and Writes
2 t
w(EM_WAIT)
Pulse duration, EMIFnWAIT assertion and deassertion 2E ns
Reads
12 t
su(EMDV-EMOEH)
Setup time, EMIFDATA[15:0] valid before EMIFnOE high 11 ns
13 t
h(EMOEH-EMDIV)
Hold time, EMIFDATA[15:0] valid after EMIFnOE high 0.5 ns
14 t
su(EMOEL-EMWAIT)
Setup Time, EMIFnWAIT asserted before end of Strobe Phase
(2)
4E+14 ns
Writes
28 t
su(EMWEL-EMWAIT)
Setup Time, EMIFnWAIT asserted before end of Strobe Phase
(2)
4E+14 ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the EMIF chapter of the TRM SPNU562 for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the EMIF chapter of the TRM SPNU562 for more information.
Table 6-36. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
NO. PARAMETER MIN TYP MAX UNIT
Reads and Writes
1 t
d(TURNAROUND)
Turn around time (TA)*E -3 (TA)*E (TA)*E + 3 ns
Reads
3 t
c(EMRCYCLE)
EMIF read cycle time (EW = 0) (RS+RST+RH)*E-3 (RS+RST+RH)*E (RS+RST+RH)*E + 3 ns
EMIF read cycle time (EW = 1)
(RS+RST+RH+
EWC)*E -3
(RS+RST+RH+
EWC)*E
(RS+RST+RH+
EWC)*E + 3
ns