Datasheet

EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_nWE
EMIF_DATA[15:0]
EMIF_nOE
15
1
16
18
20
22
24
17
19
21
23
26
27
EMIF_nDQM[1:0]
EMIF_nCS[3:2]
11
Asserted Deasserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nOE
EMIF_WAIT
SETUP
Extended Due to EMIF_WAIT
STROBE HOLD
14
STROBE
109
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
Submit Documentation Feedback
Product Folder Links: RM57L843
System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Figure 6-12. EMIFnWAIT Read Timing Requirements
6.14.2.2 Write Timing (Asynchronous RAM)
Figure 6-13. Asynchronous Memory Write Timing