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22.3.5 ADC Event Group Operating Mode Control Register (ADEVMODECR)
ADC Event Group Operating Mode Control Register (ADEVMODECR) is shown in Figure 22-24 and
Figure 22-25, and described in Table 22-11. As shown, the format of the ADEVMODECR is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 22-24. 12-bit ADC Event Group Operating Mode Control Register (ADEVMODECR)
[offset = 10h]
31 24
Reserved
R-0
23 17 16
No Reset on
Reserved
ChnSel
R-0 R/W-0
15 10 9 8
Reserved EV_DATA_FMT
R-0 R/W-0
7 6 5 4 3 2 1 0
Reserved EV_CHID OVR_EV_ Reserved EV_MODE FRZ_EV
RAM_IGN
R-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 22-25. 10-bit ADC Event Group Operating Mode Control Register (ADEVMODECR)
[offset = 10h]
31 24
Reserved
R-0
23 17 16
No Reset on
Reserved
ChnSel
R-0 R/W-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved EV_CHID OVR_EV_ Reserved EV_8BIT EV_MODE FRZ_EV
RAM_IGN
R-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
863
SPNU562–May 2014 Analog To Digital Converter (ADC) Module
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