Datasheet

ADIN0
ADIN31
Self-test and
calibration
AD
REFLO
AD
REFHI
V
in
R1
R2
S4
S1
S2
S3
S5
ADC Core
ADDRx.16,9:0
ADCALR.9:0
CALR
MUX
R1 ~ 5K
R2 ~ 7K
www.ti.com Basic Operation
Figure 22-15. Self-Test and Calibration Logic
In self-test mode, a test voltage defined by the HILO bit (ADCALCR.8) is provided to the ADC core input
through a resistor (see Table 22-3). To change the test source, this bit can be toggled before any single
conversion mode request. Changing this bit while a conversion is in progress can corrupt the results if the
source switches during the acquisition period.
Note that the switch S5 shown in Figure 22-15 is only for the purpose of explaining the self-test sequence.
There is no physical switch.
Table 22-3. Self-Test Reference Voltages
(1)
SELF_TEST HILO S1 S2 S3 S4 S5 Reference Voltage
1 0 0 1 1 0 1 AD
REFLO
via R1 || R2 connected to V
in
1 1 1 0 0 1 1 AD
REFHI
via R1 || R2 connected to V
in
0 X 0 0 0 0 1 V
in
(1)
Switches refer to Figure 22-15.
Conversions in self-test mode are started just as they are in the normal operating mode (see
Section 22.2.1.6). The conversion starts according to the configuration set in the three mode control
registers (ADEVMODECR, ADG1MODECR, ADG2MODECR) and the sampling time control registers
(ADEVSAMP, ADG1SAMP, ADG2SAMP). The acquisition time for each conversion in self-test mode is
extended to twice the normal configured acquisition time. The selected reference voltage and the input
voltage from the ADINx input channel are both connected to the ADC internal sampling capacitor
throughout this extended acquisition period. Figure 22-16 shows the self-test mode timing when the
ADREFLO is chosen as the reference voltage for the self-test mode conversion. It also assumes an
external capacitor connected to the ADC input channel.
851
SPNU562–May 2014 Analog To Digital Converter (ADC) Module
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