Datasheet

ADIN31
ADIN0
On-chipInput “Multiplexer”
External 8:1 Analog Multiplexers
to ADCSample/HoldCircuit
012293031
ADGxSEL
1 00 0 0 1
0
1
29
30
31
Index
External,5-bit
Internal,5-bit
ChannelIdentifiers
7 30
5 1
0 29
4 2
1 1
8:1
8:1
8:1
8:1
LUT index, 0to31
5-bitSelect forext.channelmux
InternalChannel
Select,32bits
Current
MaxCount
Count
4 2
1 1
3
2
EnableStrobe
Generator
1-bit EnableornEnable
forext.channelmux
StartOf
Conversion
Incrementon
EndofConversion
Resetwhen
CurrentCount=MaxCount
www.ti.com Basic Operation
22.2.2.2.2.2 Example ADC Conversion Sequence Using Enhanced Channel Selection Mode
Consider the example conversion Group1 configuration shown in Figure 22-12. Only bits 0 and 31 of
ADG1SEL are set. Assume that all other bits in this register are zeros.
In case of the default sequential channel selection mode, the write to the ADG1SEL register would cause
the Group1 conversions to start with channel 0 followed by channel 31. The conversions would then stop
or repeat in this order depending on whether Group1 is in single or continuous conversion mode.
Figure 22-12. Group1 Enhanced Channel Selection Mode Example
839
SPNU562–May 2014 Analog To Digital Converter (ADC) Module
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