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22.2.2 Advanced Conversion Group Configuration Options
Figure 22-10 shows the operating mode control registers and the status registers for each of the three
conversion groups. The register addresses shown are offsets from the base address. The ADC1 register
frame base address is FFF7 C000h and the ADC2 register frame base address is FFF7 C200h.
Figure 22-10. ADC Groups’ Operating Mode Control and Status Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Offset Address
Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No
Reset
Reserved
On
ChnSel
0x010
ADEVMODECR
OVR_
EV_ EV_ EV_ EV_ FRZ_
Reserved EV_DATA_FMT Reserved Rsvd
CHID RAM_ 8BIT MODE EV
IGN
No
Reset
Reserved
On
ChnSel
0x014
ADG1MODECR
OVR_
G1_ G1_ G1_ G1_ FRZ_
Reserved G1_DATA_FMT Reserved Rsvd
CHID RAM_ 8BIT MODE G1
IGN
No
Reset
Reserved
On
ChnSel
0x018
ADG2MODECR
OVR_
G2_ G2_ G2_ G2_ FRZ_
Reserved G2_DATA_FMT Reserved Rsvd
CHID RAM_ 8BIT MODE G2
IGN
Reserved
0x06C
EV_
EV_ EV_ EV_
ADEVSR
Reserved MEM_
BUSY STOP END
EMPTY
Reserved
0x070
G1_
G1_ G1_ G1_
ADG1SR
Reserved MEM_
BUSY STOP END
EMPTY
Reserved
0x074
G2_
G2_ G2_ G2_
ADG2SR
Reserved MEM_
BUSY STOP END
EMPTY
Reserved
0x19C
ADEVCURRCOUNT
Reserved EV_CURRENT_COUNT
Reserved
0x1A0
ADEVMAXCOUNT
Reserved EV_MAX_COUNT
0x1A4
Reserved
ADG1CURRCOUNT
Reserved G1_CURRENT_COUNT
Reserved
0x1A8
ADG1MAXCOUNT
Reserved G1_MAX_COUNT
Reserved
0x1AC
ADG2CURRCOUNT
Reserved G2_CURRENT_COUNT
Reserved
0x1B0
ADG2MAXCOUNT
Reserved G2_MAX_COUNT
836
Analog To Digital Converter (ADC) Module SPNU562–May 2014
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