Datasheet

106
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) If parity protection is enabled for the peripheral SRAM modules, then the parity bits will also be initialized along with the SRAM modules.
(2) If ECC protection is enabled for the CPU data RAM or peripheral SRAM modules, then the auto-initialization process also initializes the
corresponding ECC space.
(3) The L2 SRAM from range 128KB to 512KB is divided into 8 memory regions. Each region has an associated control bit to enable auto-
initialization.
(4) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the multibuffered mode is enabled. This is
independent of whether the application has already initialized these RAMs using the auto-initialization method or not. The MibSPIx
modules must be released from reset by writing a 1 to the SPIGCR0 registers before starting auto-initialization on the respective RAMs.
6.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware
Initialization mechanism in the system module. This hardware mechanism allows an application to
program the memory arrays with error detection capability to a known state based on their error detection
scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers, see the device-specific Technical Reference Manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is provided in
Table 6-34.
Table 6-34. Memory Initialization
(1)(2)
CONNECTING MODULE
ADDRESS RANGE
SYS.MSINENA Register
Bit #
L2RAMW.MEMINT_ENA
Register Bit #
(3)
BASE ADDRESS ENDING ADDRESS
L2 SRAM 0x08000000 0x0800FFFF 0 0
L2 SRAM 0x08010000 0x0801FFFF 0 1
L2 SRAM 0x08020000 0x0802FFFF 0 2
L2 SRAM 0x08030000 0x0803FFFF 0 3
L2 SRAM 0x08040000 0x0804FFFF 0 4
L2 SRAM 0x08050000 0x0805FFFF 0 5
L2 SRAM 0x08060000 0x0806FFFF 0 6
L2 SRAM 0x08070000 0x0807FFFF 0 7
MIBSPI5 RAM
(4)
0xFF0A0000 0xFF0BFFFF 12 n/a
MIBSPI4 RAM
(4)
0xFF060000 0xFF07FFFF 19 n/a
MIBSPI3 RAM
(4)
0xFF0C0000 0xFF0DFFFF 11 n/a
MIBSPI2 RAM
(4)
0xFF080000 0xFF09FFFF 18 n/a
MIBSPI1 RAM
(4)
0xFF0E0000 0xFF0FFFFF 7 n/a
DCAN4 RAM 0xFF180000 0xFF19FFFF 20 n/a
DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 n/a
DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 n/a
DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 n/a
MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 n/a
MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8 n/a
NHET2 RAM 0xFF440000 0xFF45FFFF 15 n/a
NHET1 RAM 0xFF460000 0xFF47FFFF 3 n/a
HET TU2 RAM 0xFF4C0000 0xFF4DFFFF 16 n/a
HET TU1 RAM 0xFF4E0000 0xFF4FFFFF 4 n/a
DMA RAM 0xFFF80000 0xFFF80FFF 1 n/a
VIM RAM 0xFFF82000 0xFFF82FFF 2 n/a