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1051

ADC1

12 Bit

EXT_SEL[4:0]

EXT_ENA

AD1EVT

AD1IN[7:0]

AD1IN[15:8]/AD2IN[15:8]

AD1IN[23:16]/AD2IN[7:0]

AD1IN[31:24]

ADC2

12 Bit

CCAD

SSAD

REFHI

REFLO

AD2EVT

AD2IN[24:16]

CPU Interface

Overview

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22.1 Overview

This microcontrollers implements up to two instances of the ADC module. The main features of the ADC

module are:

• Selectable 10-bit or 12-bit resolution

• Successive-approximation-register architecture

• Three conversion groups – Group1, Group2, and Event Group

• All three conversion groups can be configured to be hardware-triggered; group1 and group2 can also

be triggered by software

• Conversion results are stored in a 64-word memory (SRAM)

– These 64 words are divided between the three conversion groups and are configurable by software

– Accesses to the conversion result RAM are protected by parity

• Flexible options for generating DMA requests for transferring conversion results

• Selectable channel conversion order

– Sequential conversions in ascending order of channel number, OR

– User-defined channel conversion order with the Enhanced Channel Selection Mode

• The Enhanced Channel Selection Mode is only available to ADC1.

• Single or continuous conversion modes

• Embedded self-test logic for input channel failure detection (open / short to power / short to ground)

• Embedded calibration logic for offset error correction

• Enhanced Power-down mode

• External event pin (ADEVT) to trigger conversions

– ADEVT is also programmable as general-purpose I/O

• Eight hardware events to trigger conversions

The two instances of the 12-bit ADC modules on the microcontroller share 16 analog input channels. The

connections are shown in Figure 22-1.

• ADC1 supports 32 channels.

• ADC2 supports 25 channels, of which 16 channels are shared with ADC1.

• When using both ADC1 and ADC2 on a shared channel, the sample windows must be identical such

that the sample windows completely match each other or non-overlapping with a minimum of 2 ADC

cycles buffer between the end of one ADC’s sample window and the start of the other ADC’s sample

window.

• The reference voltages, as well as operating supply and ground, are shared between the two ADC

cores.

Figure 22-1. Channel Assignments of Two ADC Cores

826

Analog To Digital Converter (ADC) Module SPNU562–May 2014

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