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Example Configuration
21.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDSRETR) Settings for the EMIF to K4S641632H-
TC(L)70 Interface
The SDRAM self refresh exit timing register (SDSRETR) should be programmed second to satisfy the t
XSR
timing requirement from the K4S641632H-TC(L)70 datasheet. Table 21-39 shows the calculation of the
proper value to program into the T_XS field of this register. Based on this calculation, a value of 6h should
be written to SDSRETR. Figure 21-29 shows how SDSRETR should be programmed.
Table 21-39. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface
Value from K4S641632H-TC(L)70 Value Calculated for
Field Name Formula Datasheet Field
T_XS T_XS >= (t
XSR
× f
EMIF_CLK
) - 1 t
RC
= 68 ns (min)
(1)
6
(1)
The Samsung datasheet does not specify a t
XSR
value. Instead, Samsung specifies t
RC
as the minimum required time after CKE
going high to complete self refresh exit.
Figure 21-29. SDRAM Self Refresh Exit Timing Register (SDSRETR)
31 16
0000 0000 0000 0000
Reserved
15 5 4 0
000 0000 0000 0 0110
Reserved T_XS
21.4.2.1.4 SDRAM Refresh Control Register (SDRCR) Settings for the EMIF to K4S641632H-TC(L)70
Interface
The SDRAM refresh control register (SDRCR) should next be programmed to satisfy the required refresh
rate of the K4S641632H-TC(L)70. Table 21-40 shows the calculation of the proper value to program into
the RR field of this register. Based on this calculation, a value of 61Ah should be written to SDRCR.
Figure 21-30 shows how SDRCR should be programmed.
Table 21-40. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface
Field Name Formula Values Value Calculated for Field
RR RR ≤ f
EMIF_CLK
× t
Refresh Period
From SDRAM datasheet: t
Refresh Period
RR = 1562 cycles = 61Ah cycles
/ n
cycles
= 64 ms; n
cycles
= 4096 EMIF clock
rate: f
EMIF_CLK
= 100 MHz
Figure 21-30. SDRAM Refresh Control Register (SDRCR)
31 19 18 16
0 0000 0000 0000 000
Reserved Reserved
15 13 12 0
000 0 0110 0001 1010 (61Ah)
Reserved RR
819
SPNU562–May 2014 External Memory Interface (EMIF)
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