Datasheet

103
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
6.11 L2RAMW (Level 2 RAM Interface Module)
L2RAMW is the TMS570 level two RAM wrapper. Major features implemented in this device include:
• Supports 512KB of L2 SRAMs
• One 64-bit OCP interface
• Built-in ECC generation and evaluation logic
– The ECC logic is enabled by default.
– When enabled, automatic ECC correction on write data from masters on any write sizes (8-,16-,32-,or 64-bit)
– Less than 64-bit write forces built in read-modify-write
– When enabled, reads due to read-modify-write go through ECC correction before data merging with the
incoming write data
• Redundant address decoding. Same address decode logic block is duplicated and compared to each other
• Data Trace
– Support tracing of both read and write accesses through RTP module
• Auto initialization of memory banks to known values for both data and their corresponding ECC checksum
6.11.1 L2 SRAM Initialization
The entire L2 SRAM can be globally initialized by setting the corresponding bit in SYS.MSINENA register.
When initialized, the memory arrays are written with all zeros for the 64-bit data and the corresponding 8-
bit ECC checksum. Hardware memory initialization eliminates ECC error when the CPU reads from an un-
initialized memory location which can cause an ECC error. For more information, see the device-specific
Technical Reference Manual.
6.12 ECC / Parity Protection for Accesses to Peripheral RAMs
Accesses to some peripheral RAMs are protected by either odd/even parity checking or ECC checking.
During a read access the parity or ECC is calculated based on the data read from the peripheral RAM and
compared with the good parity or ECC value stored in the peripheral RAM for that peripheral. If any word
fails the parity or ECC check, the module generates a ECC/parity error signal that is mapped to the Error
Signaling Module. The module also captures the peripheral RAM address that caused the parity error.
The parity or ECC protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity or ECC protection for
accesses to its RAM.
NOTE
For peripherals with parity protection the CPU read access gets the actual data from the
peripheral. The application can choose to generate an interrupt whenever a peripheral RAM
parity error is detected.