Datasheet

EMIF_CLK

EMIF_nCS[n]

EMIF_nDQM

EMIF_A/EMIF_BA

EMIF_D

EMIF_nOE

EMIF_nWE

Setup

Strobe

Hold

Address

Data

Byte enable

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EMIF Module Architecture

Table 21-19. Asynchronous Read Operation in Normal Mode (continued)

Time Interval Pin Activity in Normal Mode

End of the hold At the end of the hold period:

period

• The address pins EMIF_A and EMIF_BA become invalid

• EMIF_nCS[4:2] rises (if no more operations are required to complete the current request)

EMIF may be required to issue additional read operations to a device with a small data bus width in order to

complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another

operation without incurring the turn-round cycle delay. The setup, strobe, and hold values are not updated in this

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF

instead enters directly into the turnaround period for the pending read or write operation.

Figure 21-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode

791

SPNU562–May 2014 External Memory Interface (EMIF)

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