Datasheet

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Table 21-18. Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR) (continued)
Parameter Description
AT_MASK_CLR Asynchronous Timeout Mask Clear.
Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout
occurs.
21.2.6.4 Read and Write Operations in Normal Mode
Normal Mode is the asynchronous interface's default mode of operation. It is selected when the SS bit in
the asynchronous n configuration register (CEnCFG) is cleared to 0. In this mode, the EMIF_nDQM pins
operate as byte enables. Section 21.2.6.4.1 and Section 21.2.6.4.2 explain the details of read and write
operations while in Normal Mode.
21.2.6.4.1 Asynchronous Read Operations (Normal Mode)
NOTE: During an entire asynchronous read operation, the EMIF_nWE pin is driven high.
An asynchronous read is performed when any of the requesters mentioned in Section 21.2.2 request a
read from the attached asynchronous memory. After the request is received, a read operation is initiated
once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 21.2.13. In the event that the read request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous read operation in Normal Mode are described in Table 21-19. Also,
Figure 21-10 shows an example timing diagram of a basic read operation.
Table 21-19. Asynchronous Read Operation in Normal Mode
Time Interval Pin Activity in Normal Mode
Turn-around Once the read operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
period number of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (CEnCFG). There are two exceptions
to this rule:
• If the current read operation was directly proceeded by another read operation, no turnaround cycles are
inserted.
• If the current read operation was directly proceeded by a write operation and the TA field has been cleared
to 0, one turn-around cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it again checks to make sure that the read
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.
Start of the The following actions occur at the start of the setup period:
setup period
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values in
CEnCFG.
• The address pins EMIF_A and EMIF_BA become valid and carry the values described in Section 21.2.6.1.
• EMIF_nCS[4:2] falls to enable the external device (if not already low from a previous operation)
Strobe period The following actions occur during the strobe period of a read operation:
1. EMIF_nOE falls at the start of the strobe period
2. On the rising edge of the clock which is concurrent with the end of the strobe period:
• EMIF_nOE rises
• The data on the EMIF_D bus is sampled by the EMIF.
In Figure 21-10, EMIF_nWAIT is inactive. If EMIF_nWAIT is instead activated, the strobe period can be extended
by the external device to give it more time to provide the data. Section 21.2.6.6 contains more details on using the
EMIF_nWAIT pin.
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External Memory Interface (EMIF) SPNU562–May 2014
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