Datasheet

MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register
MRC p15,#0,r1,c9,c12,#0
101
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
Submit Documentation Feedback
Product Folder Links: RM57L843
System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Table 6-30. EEPROM Flash Bank
MEMORY ARRAYS (OR BANKS)
SECTOR
NO.
SEGMENT LOW ADDRESS HIGH ADDRESS
BANK7 (128KB) for EEPROM emulation
0 4KB 0xF020_0000 0xF020_0FFF
"
"
"
"
"
"
"
"
"
"
"
"
31 4KB 0xF021_F000 0xF021_FFFF
6.10.2 Main Features of Flash Module
• Support for multiple flash banks for program and/or data storage
• Simultaneous read accesses on two banks while performing program or erase operation on any other bank
• Integrated state machines to automate flash erase and program operations
• Software interface for flash program and erase operations
• Pipelined mode operation to improve instruction access interface bandwidth
• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R5F CPU
• Support for a rich set of diagnostic features
6.10.3 ECC Protection for Flash Accesses
All accesses to the L2 program flash memory are protected by SECDED logic embedded inside the CPU.
The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash
memory. The CPU calculates the expected ECC code based on the 64 bits data received and compares it
with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU,
while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling
mechanism is not enabled by default and must be enabled by setting the 'X' bit of the Performance
Monitor Control Register, c9.
NOTE
ECC is permanently enabled in the CPU L2 interface.
6.10.4 Flash Access Speeds
For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.