Datasheet

EMIF_nCS[0]
EMIF_nCAS
EMIF_nRAS
EMIF_nWE
EMIF_CLK
EMIF_CKE
EMIF_BA[1:0]
EMIF_A[11:0]
EMIF_nDQM[0]
EMIF_nDQM[1]
EMIF_D[15:0]
EMIF
nCE
nCAS
nRAS
nWE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
SDRAM
2M x 16
x 4 bank
PRE
EMIF_CLK
EMIF_nCS[0]
EMIF_BA
EMIF_A
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
Bank
EMIF_A[10]=0
EMIF_nDQM
www.ti.com EMIF Module Architecture
Figure 21-2. Timing Waveform of SDRAM PRE Command
21.2.5.2 Interfacing to SDRAM
The EMIF supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• The number of column address bits is 8, 9, 10, or 11.
• The number of row address bits is 13, 14, 15, or 16.
• The number of internal banks is 1, 2, or 4.
Figure 21-3 shows an interface between the EMIF and a 2M × 16 × 4 bank SDRAM device, and
Figure 21-4 shows an interface between the EMIF and a 512K × 16 × 2 bank SDRAM device. For devices
supporting 16-bit interface, refer to Table 21-6 for list of commonly-supported SDRAM devices and the
required connections for the address pins.
Figure 21-3. EMIF to 2M × 16 × 4 bank SDRAM Interface
775
SPNU562–May 2014 External Memory Interface (EMIF)
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