Datasheet

100
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
6.10 Flash Memory
6.10.1 Flash Memory Configuration
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
Table 6-29. Flash Memory Banks and Sectors
MEMORY ARRAYS (OR BANKS)
SECTOR
NO.
SEGMENT LOW ADDRESS HIGH ADDRESS
BANK0 (2.0MB)
0 16KB 0x0000_0000 0x0000_3FFF
1 16KB 0x0000_4000 0x0000_7FFF
2 16KB 0x0000_8000 0x0000_BFFF
3 16KB 0x0000_C000 0x0000_FFFF
4 16KB 0x0001_0000 0x0001_3FFF
5 16KB 0x0001_4000 0x0001_7FFF
6 32KB 0x0001_8000 0x0001_FFFF
7 128KB 0x0002_0000 0x0003_FFFF
8 128KB 0x0004_0000 0x0005_FFFF
9 128KB 0x0006_0000 0x0007_FFFF
10 256KB 0x0008_0000 0x000B_FFFF
11 256KB 0x000C_0000 0x000F_FFFF
12 256KB 0x0010_0000 0x0013_FFFF
13 256KB 0x0014_0000 0x0017_FFFF
14 256KB 0x0018_0000 0x001B_FFFF
15 256KB 0x001C_0000 0x001F_FFFF
BANK1 (2.0MB)
0 128KB 0x0020_0000 0x0021_FFFF
1 128KB 0x0022_0000 0x0023_FFFF
2 128KB 0x0024_0000 0x0025_FFFF
3 128KB 0x0026_0000 0x0027_FFFF
4 128KB 0x0028_0000 0x0029_FFFF
5 128KB 0x002A_0000 0x002B_FFFF
6 128KB 0x002C_0000 0x002D_FFFF
7 128KB 0x002E_0000 0x002F_FFFF
8 128KB 0x0030_0000 0x0031_FFFF
9 128KB 0x0032_0000 0x0033_FFFF
10 128KB 0x0034_0000 0x0035_FFFF
11 128KB 0x0036_0000 0x0037_FFFF
12 128KB 0x0038_0000 0x0039_FFFF
13 128KB 0x003A_0000 0x003B_FFFF
14 128KB 0x003C_0000 0x003D_FFFF
15 128KB 0x003E_0000 0x003F_FFFF