Product Folder Sample & Buy Technical Documents Tools & Software Support & Community RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 RM57L843 Hercules™ Microcontroller Based on the ARM® Cortex®-R Core 1 Device Overview 1.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 1.2 • 2 www.ti.
RM57L843 www.ti.com 1.3 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Description The RM57L843 device is part of the Hercules RM series of high-performance ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of IEC 61508 functional safety applications. Start evaluating today with the Hercules RM57x LaunchPad Development Kit.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The Ethernet module supports MII, RMII, and Management Data I/O (MDIO) interfaces. The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds of 100 and 400 kbps.
RM57L843 www.ti.com 1.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table of Contents 1 2 3 4 Device Overview ......................................... 1 On-Chip SRAM Initialization and Testing .......... 104 1.2 Applications ........................................... 2 6.14 External Memory Interface (EMIF) ................. 108 1.3 Description ............................................ 3 6.15 Vectored Interrupt Manager ........................ 115 1.4 Functional Block Diagram ...............
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 2 Revision History This data manual revision history highlights the technical changes made to the SPNS215B device-specific data manual to make it an SPNS215C revision. These devices are now in the Production Data (PD) stage of development.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 3 Device Comparison Table 3-1 lists the features of the RM57L843 devices. Table 3-1.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4 Terminal Configuration and Functions 4.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2 www.ti.com Terminal Functions Table 4-1 through Table 4-26 identify the external signal names, the associated terminal numbers along with the mechanical package designator, the terminal type (Input, Output, I/O, Power, or Ground), whether the terminal has any internal pullup/pulldown, whether the terminal can be configured as a GIO, and a functional terminal description. The first signal name listed is the primary function for that terminal.
RM57L843 www.ti.com 4.2.1 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 ZWT Package 4.2.1.1 Multibuffered Analog-to-Digital Converters (MibADC) Table 4-1.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 4-1.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-1. ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued) TERMINAL SIGNAL NAME 337 ZWT SIGNAL TYPE DEFAULT PULL STATE PULL TYPE OUTPUT BUFFER DRIVE STRENGTH DESCRIPTION VCCAD W15(3) Input - - - Operating supply for ADC VSSAD W16(3) Input - - - ADC supply ground VSSAD W19(3) Input - - - ADC supply ground (1) This ADC channel is also multiplexed with an internal temperature sensor.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.2 www.ti.com Enhanced High-End Timer Modules (N2HET) Table 4-2.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-2.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 4-2.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-2.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.3 www.ti.com RAM Trace Port (RTP) Table 4-3.
RM57L843 www.ti.com 4.2.1.4 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Enhanced Capture Modules (eCAP) Table 4-4.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.5 www.ti.com Enhanced Quadrature Encoder Pulse Modules (eQEP) Table 4-5.
RM57L843 www.ti.com 4.2.1.6 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Enhanced Pulse-Width Modulator Modules (ePWM) Table 4-6.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.7 22 www.ti.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-7.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.8 www.ti.com General-Purpose Input / Output (GIO) Table 4-8.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-8.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.9 www.ti.com Controller Area Network Controllers (DCAN) Table 4-9.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.10 Local Interconnect Network Interface Module (LIN) Table 4-10.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 4.2.1.11 Standard Serial Communication Interface (SCI) Table 4-11.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.12 Inter-Integrated Circuit Interface Module (I2C) Table 4-12.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 4.2.1.13 Multibuffered Serial Peripheral Interface Modules (MibSPI) Table 4-13.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-13.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 4.2.1.14 Ethernet Controller Table 4-14.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-16.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 4-16. ZWT Ethernet Controller: Media Independent Interface (MII) (continued) Terminal Signal Name 337 ZWT MII_TXEN E4 MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19(1) Signal Type Default Pull State Pull Type Output Buffer Drive Strength Output - - 8mA Description Transmit enable (1) This is the secondary terminal at which the signal is also available. See Section 4.2.2.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.15 External Memory Interface (EMIF) Table 4-17.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 4-17.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-17.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 4.2.1.16 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5) Table 4-18.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-18.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 4.2.1.17 System Module Interface Table 4-19.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.19 Test and Debug Modules Interface Table 4-21.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 4.2.1.21 Supply for Core Logic: 1.2-V Nominal Table 4-23. ZWT Supply for Core Logic: 1.2-V Nominal Terminal Signal Name 337 ZWT VCC P10 Pull Type Output Buffer Drive Strength Description - - - Core supply Signal Type Default Pull State 1.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.22 Supply for I/O Cells: 3.3-V Nominal Table 4-24. ZWT Supply for I/O Cells: 3.3-V Nominal Terminal Signal Type Default Pull State Pull Type Output Buffer Drive Strength 3.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 4.2.1.23 Ground Reference for All Supplies Except VCCAD Table 4-25.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.1.24 Other Supplies Table 4-26. Other Supplies TERMINAL SIGNAL NAME 337 ZWT SIGNAL TYPE DEFAULT PULL STATE PULL TYPE OUTPUT BUFFER DRIVE STRENGTH – – DESCRIPTION Supply for PLL: 1.2-V nominal VCCPLL P11 1.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.2 www.ti.com Multiplexing This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as required by the target application. The multiplexing is mostly on the output signals. A few inputs are also multiplexed to allow the same input signal to be driven in from an alternative terminal. For more information on multiplexing, refer to the IOMM chapter of the device specific technical reference manual. 4.2.2.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-27.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 4-27.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-27.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 4-27.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.2.1.1 Notes on Output Multiplexing Table 4-27 lists the output signal multiplexing and control signals for selecting the desired functionality for each pad. • • 337 ZWT BALL The pads default to the signal defined by the "Default Function" in Table 4-27. The CTRL x columns in Table 4-27 contain a value of type x[y] which indicates the control register PINMMRx, bit y.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 4.2.2.2 www.ti.com Input Multiplexing Some signals are connected to more than one terminals, so that the inputs for these signals can come from either of these terminals. A multiplexor is implemented to let the application choose the terminal that will be used for providing the input signal from among the available options. The input path selection is done based on two bits in the PINMMR control registers as listed in Table 4-28. Table 4-28.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 4-28.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 5 Specifications Absolute Maximum Ratings (1) 5.1 Over Operating Free-Air Temperature Range Supply voltage Input voltage Input clamp current: MIN MAX VCC (2) –0.3 1.43 VCCIO, VCCP (2) –0.3 4.6 VCCAD –0.3 6.25 All input pins, with exception of ADC pins –0.3 4.6 ADC input pins –0.3 6.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Device Recommended Operating Conditions (1) 5.4 MIN NOM MAX UNIT VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V VCCPLL PLL supply voltage 1.14 1.2 1.32 V VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V VCCAD MibADC supply voltage 3 5.25 V VCCP Flash pump supply voltage 3 3.6 V VSS Digital logic supply ground VSSAD MibADC supply ground VADREFHI VADREFLO TA TJ (1) 3.3 0 V –0.1 0.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 5.5 www.ti.com Switching Characteristics over Recommended Operating Conditions for Clock Domains Table 5-2.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 L2 flash is clocked by HCLK and is limited to maximum 150 MHz. The L2 flash can support zero data wait state up to 45 MHz.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 5.7 www.ti.com Power Consumption Summary Over Recommended Operating Conditions PARAMETER TEST CONDITIONS fGCLK = 330 MHz, fHCLK = 110 MHz, fVCLK = 110 MHz, fVCLK2 = 110 MHz, fVCLK3 = 110 MHz VCC digital supply and PLL current (operating mode) ICC MIN TYP (1) MAX UNIT (2) mA 970 1350 (3) (4) mA 595 880 VCC digital supply and PLL current (LBIST mode, or PBIST mode) LBIST clock rate = 82.
RM57L843 www.ti.com 5.8 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Input/Output Electrical Characteristics Over Recommended Operating Conditions (1) PARAMETER Vhys VIL Input hysteresis Low-level input voltage VIH High-level input voltage TEST CONDITIONS All inputs MIN Low-level output voltage VOH High-level output voltage IIC Input clamp current (I/O pins) II IOL Input current (I/O pins) Low-level output current High-level output current UNIT mV –0.3 0.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 5.9 www.ti.com Thermal Resistance Characteristics for the BGA Package (ZWT) Over operating free-air temperature range (unless otherwise noted) (1) °C / W RΘJA Junction-to-free air thermal resistance, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 14.3 RΘJB Junction-to-board thermal resistance (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 5.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 5.10.2 Output Timings Table 5-4. Switching Characteristics for Output Timings versus Load Capacitance (CL) PARAMETER MIN CL = 15 pF CL = 50 pF Rise time, tr 8 mA low EMI pins Rise time, tr 4 mA low EMI pins Fall time, tf Rise time, tr 2 mA-z low EMI pins Fall time, tf Rise time, tr 8 mA mode Fall time, tf Selectable 8mA / 2mA-z pins Rise time, tr 2 mA-z mode Fall time, tf 4 7.2 CL = 150 pF 12.5 CL = 15 pF 2.5 4 CL = 100 pF 7.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com tr tf V OH Output VCCIO VOH VOL VOL 0 Figure 5-3. CMOS-Level Outputs Table 5-5. Timing Requirements for Outputs (1) MIN td(parallel_out) (1) 62 Delay between low to high, or high to low transition of general-purpose output signals that can be configured by an application in parallel, for example, all signals in a GIOA port, or all N2HET1 signals, and so forth.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6 System Information and Electrical Specifications 6.1 Device Power Domains The device core logic is split up into multiple virtual power domains to optimize the power for a given application use case. This device has six logic power domains: PD1, PD2, PD3, PD4, PD5, and PD6. PD1 is a domain which cannot turn off of its clocks at once through the Power-Management Module (PMM).
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.2 www.ti.com Voltage Monitor Characteristics A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies. 6.2.1 Important Considerations • • 6.2.2 The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range.
RM57L843 www.ti.com 6.3 6.3.1 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Power Sequencing and Power-On Reset Power-Up Sequence There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The powerup sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (for more details, see Table 6-3), core voltage rising above the minimum core supply threshold and the release of power-on reset.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.3.2 www.ti.com Power-Down Sequence The different supplies to the device can be powered down in any order. 6.3.3 Power-On Reset: nPORRST This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown. 6.3.3.1 nPORRST Electrical and Timing Requirements Table 6-4.
RM57L843 www.ti.com 6.4 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Warm Reset (nRST) This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.5 6.5.1 www.ti.com ARM Cortex-R5F CPU Information Summary of ARM Cortex-R5F CPU Features The features of the ARM Cortex-R5F CPU include: • An integer unit with integral Embedded ICE-RT logic. • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 PDx Outputs from CPU2 to the system PDy cpu1clk Outputs from CPU1 to the system CCM-R5F 2 cycle delay CPU Bus Compare PD Inactivity Monitor Checker CPU Inactivity Monitor Compare errors ESM VIM Bus Compare Safe values (values that will force the Z l Œ Wh[• }µš‰µš• to inactive states) VIM1 CPU1 (Main CPU) VIM2 CPU2 (Checker CPU) 2 cycle delay cpu2clk Inputs to CPU1 Figure 6-2. Dual Core Implementation 6.5.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com CCM-R5F also produces a signal to ESM GP1.92 to indicate its current status whether it is out of lockstep or is in self-test mode. This ensures that any lock step fault is reported to the CPU. 6.5.4.1.2 Self-Test Mode In self-test mode the CCM-R5F is checked for faults, by applying internally generated, series of test patterns to look for any hardware faults inside the module. During self-test the compare error signal is deactivated.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 .text .state32 .global __clearRegisters_ .
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.5.5 www.ti.com CPU Self-Test The CPU STC (Self-Test Controller) is used to test the two Cortex-R5F CPU Cores using the Deterministic Logic BIST Controller as the test engine.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-9. CPU Self-Test Coverage INTERVALS TEST COVERAGE, % 0 0 TEST CYCLES 0 1 56.85 1629 2 64.19 3258 3 68.76 4887 4 71.99 6516 5 75 8145 6 76.61 9774 7 78.08 11403 8 79.2 13032 9 80.18 14661 10 81.03 16290 11 81.9 17919 12 82.58 19548 13 83.24 21177 14 83.73 22806 15 84.15 24435 16 84.52 26064 17 84.9 27693 18 85.26 29322 19 85.68 30951 20 86.05 32580 21 86.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.5.6 www.ti.com N2HET STC / LBIST Self-Test Coverage Logic BIST self-test capability for N2HETs is available in this device. The STC2 can be configured to perform self-test for both N2HETs at the same time or one at the time. The default value of the N2HET LBIST clock prescaler is divide-by-1. However, the maximum clock rate for the N2HET STC / LBIST is VCLK/2. N2HET STC test should not be executed concurrently with CPU STC test. Table 6-10.
RM57L843 www.ti.com 6.6 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Clocks 6.6.1 Clock Sources Table 6-11 lists the available clock sources on the device. Each clock source can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source. Table 6-11 also lists the default state of each clock source. Table 6-11. Available Clock Sources CLOCK SOURCE NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.6.1.1.1 Timing Requirements for Main Oscillator Table 6-12.
RM57L843 www.ti.com 6.6.1.2 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Low-Power Oscillator The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro. 6.6.1.2.1 Features The main features of the LPO are: • Supplies a clock at extremely low power to reduce power consumption. This is connected as clock source 4 of the Global Clock Module (GCM). • Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source 5 of the GCM.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.6.1.3 www.ti.com Phase-Locked Loop (PLL) Clock Modules The PLL is used to multiply the input frequency to some higher frequency. The main features of the PLL are: • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled.
RM57L843 www.ti.com 6.6.1.4 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 External Clock Inputs The device supports up to two external clock inputs. This clock input must be a square-wave input. Table 6-15 specifies the electrical and timing requirements for these clock inputs. Table 6-15.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.6.2 www.ti.com Clock Domains 6.6.2.1 Clock Domain Descriptions Table 6-16 lists the device clock domains and their default clock sources. Table 6-16 also lists the system module control register that is used to select an available clock source for each clock domain. Table 6-16. Clock Domain Descriptions CLOCK DOMAIN CLOCK DISABLE BIT DEFAULT SOURCE SOURCE SELECTION REGISTER SPECIAL CONSIDERATIONS • GCLK1 SYS.CDDIS.0 OSCIN SYS.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-16. Clock Domain Descriptions (continued) CLOCK DOMAIN CLOCK DISABLE BIT DEFAULT SOURCE SOURCE SELECTION REGISTER SPECIAL CONSIDERATIONS • • VCLKA4_DIVR SYS.VCLKACON1.20 VCLK SYS.VCLKACON1[19:16] • • • • RTICLK1 SYS.CDDIS.6 VCLK SYS.RCLKSRC[3:0] • • Copyright © 2014–2016, Texas Instruments Incorporated Divided down from VCLKA4 using the VCLKA4R field of the VCLKACON1 register Frequency can be VCLKA4/1, VCLKA4/2, ...
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.6.2.2 www.ti.com Mapping of Clock Domains to Device Modules Each clock domain has a dedicated functionality as shown in Figure 6-6. GCM 0 OSCIN FMzPLL X1..256 /1..64 Low Power Oscillator GCLK, GCLK2 (to CPU, CCM) (SSPLL) /1..32 /1..8 /1..4 1 * 80kHz 4 10MHz 5 PLL # 2 (SSPLL) /1..64 X1..256 /1..8 * the frequency at this node must not exceed the maximum HCLK specifiation. /1..32 3 EXTCLKIN 1 /1..
RM57L843 www.ti.com 6.6.3 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC The MII interface requires VCLKA4_DIVR_EMAC VCLKA4_DIVR_EAMC to be 50 MHz. to be 25 MHz and the RMII requires These different frequencies are supported by adding special dedicated clock source selection options for the VCLKA4_DIVR_EMAC clock domain. This logic is shown in Figure 6-7.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.6.4 www.ti.com Clock Test Mode The RM57Lx platform architecture defines a special mode that allows various clock signals to be selected and output on the ECLK1 terminal and N2HET1[12] device outputs. This special mode, Clock Test Mode, is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. See Table 6-18 and Table 6-19 for the CLKTEST bits value and signal selection. Table 6-18.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-19.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.7 www.ti.com Clock Monitoring The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO. The LPO provides two different clock sources – a low frequency (CLK80K) and a high frequency (CLK10M). The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN).
RM57L843 www.ti.com 6.7.3.2 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Mapping of DCC Clock Source Inputs Table 6-20. DCC1 Counter 0 Clock Sources CLOCK SOURCE[3:0] CLOCK NAME Others Oscillator (OSCIN) 0x5 High-frequency LPO 0xA Test clock (TCK) Table 6-21.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.8 www.ti.com Glitch Filters Table 6-24 lists the signals with glitch filters present . Table 6-24.
RM57L843 www.ti.com 6.9 6.9.1 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Device Memory Map Memory Map Diagram Figure 6-9 shows the device memory map.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.9.2 www.ti.com Memory Map Table Table 6-25.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-25.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-25.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-25.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-25.
RM57L843 www.ti.com 6.9.3 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program status register (CPSR).
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.9.4 www.ti.com Master/Slave Access Privileges Table 6-26 and Table 6-27 list the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device. Each slave module on either the CPU Interconnect Subsystem or the Peripheral Interconnect Subsystem is listed in Table 6-27. Allowed indicates that the module listed in the MASTERS column can access that slave module. Table 6-26.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 bit MasterID access protection register is defined. Each bit grants or denies the permission of the corresponding binary coded decimal MasterID. For example, if bit 5 of the access permission register is set, it grants MasterID 5 to access the peripheral. If bit 7 is clear, it denies MasterID 7 to access the peripheral. Figure 6-10 shows the MasterID filtering scheme. Table 6-27 lists the MasterID of each master, which can access the PCRx.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-28. CPU Interconnect Subsystem SDC Register Bit Field Mapping Register name ERR_GENERIC_PARITY bit 0 PS_SCR_M bit 1 POM bit 2 DMA_PORTA bit 3 Reserved bit 4 CPU AXI-M bit 5 ACP-M bit 6 Remark • Each bit indicates the transaction processing block inside the interconnect corresponding to the master that is detected by the interconnect checker to have a fault.
RM57L843 www.ti.com 6.9.7 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Parameter Overlay Module (POM) Considerations The Parameter Overlay Module (POM) is implemented as part of the L2FMC module. It is used to redirect flash memory accesses to external memory interfaces or internal SRAM. The POM has an OCP master port to redirect accesses. The POM MMRs are located in a separate block and read/writes will happen through the Debug APB port on the L2FMC. The POM master port is capable of read accesses only.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.10 Flash Memory 6.10.1 Flash Memory Configuration Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic. Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-30. EEPROM Flash Bank MEMORY ARRAYS (OR BANKS) SECTOR NO. SEGMENT LOW ADDRESS HIGH ADDRESS 0 4KB 0xF020_0000 0xF020_0FFF " " " " " " " " " " " " 31 4KB 0xF021_F000 0xF021_FFFF BANK7 (128KB) for EEPROM emulation 6.10.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.10.5 Flash Program and Erase Timings 6.10.5.1 Flash Program and Erase Timings for Program Flash Table 6-31. Timing Requirements for Program Flash MIN tprog(288bits) Wide Word (288-bits) programming time NOM MAX UNIT 40 300 µs 21.3 s –40°C to 105°C tprog(Total) 4.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.11 L2RAMW (Level 2 RAM Interface Module) L2RAMW is the TMS570 level two RAM wrapper. Major features implemented in this device include: • • • • • • Supports 512KB of L2 SRAMs One 64-bit OCP interface Built-in ECC generation and evaluation logic – The ECC logic is enabled by default.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.13 On-Chip SRAM Initialization and Testing 6.13.1 On-Chip SRAM Self-Test Using PBIST 6.13.1.1 Features • • • Extensive instruction set to support various memory test algorithms ROM-based algorithms allow application to run TI production-level memory tests Independent testing of all on-chip SRAM 6.13.1.2 PBIST RAM Groups Table 6-33. PBIST RAM Grouping TEST PATTERN (ALGORITHM) MEMORY RAM GROUP TEST CLOCK RGS RDS MEM TYPE NO.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-33. PBIST RAM Grouping (continued) TEST PATTERN (ALGORITHM) MEMORY L2RAMW R5_ICACHE R5_DCACHE Reserved Reserved RAM GROUP 30 31 32 33 34 TEST CLOCK GCM_HCLK GCM_GCLK1 GCM_GCLK1 GCM_GCLK2 GCM_GCLK2 RGS 32 40 41 43 44 RDS MEM TYPE NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.13.2 On-Chip SRAM Auto Initialization This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the system module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 NOTE Peripheral memories not listed in the table either do not support auto-initialization or have implemented auto-initialization controlled directly by their respective peripherals.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.14 External Memory Interface (EMIF) 6.14.1 Features The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or SDRAM devices.
RM57L843 www.ti.com EMIF_nCS[3:2] SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 SETUP Extended Due to EMIF_WAIT STROBE STROBE HOLD EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DATA[15:0] 14 11 EMIF_nOE 2 EMIF_WAIT 2 Asserted Deasserted Figure 6-12. EMIFnWAIT Read Timing Requirements 6.14.2.2 Write Timing (Asynchronous RAM) 15 1 EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_nDQM[1:0] 16 17 18 19 20 22 24 21 23 EMIF_nWE 27 26 EMIF_DATA[15:0] EMIF_nOE Figure 6-13.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 SETUP www.ti.com Extended Due to EMIF_WAIT STROBE STROBE HOLD EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DATA[15:0] 28 25 EMIF_nWE 2 EMIF_WAIT 2 Asserted Deasserted Figure 6-14. EMIFnWAIT Write Timing Requirements 6.14.2.3 EMIF Asynchronous Memory Timing Table 6-35. EMIF Asynchronous Memory Timing Requirements (1) NO.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-36. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued) NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.14.2.4 Read Timing (Synchronous RAM) BASIC SDRAM READ OPERATION 1 2 2 EMIF_CLK 4 3 EMIF_nCS[0] 6 5 EMIF_nDQM[1:0] 7 8 7 8 EMIF_BA[1:0] EMIF_ADDR[21:0] 19 2 EM_CLK Delay 17 20 18 EMIF_DATA[15:0] 11 12 EMIF_nRAS 13 14 EMIF_nCAS EMIF_nWE Figure 6-15.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.14.2.5 Write Timing (Synchronous RAM) BASIC SDRAM WRITE OPERATION 1 2 2 EMIF_CLK 4 3 EMIF_CS[0] 6 5 EMIF_DQM[1:0] 7 8 7 8 EMIF_BA[1:0] EMIF_ADDR[21:0] 9 10 EMIF_DATA[15:0] 11 12 EMIF_nRAS 13 EMIF_nCAS 15 16 EMIF_nWE Figure 6-16. Basic SDRAM Write Operation EMIF Synchronous Memory Timing Table 6-37. EMIF Synchronous Memory Timing Requirements NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-38. EMIF Synchronous Memory Switching Characteristics (continued) NO.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.15 Vectored Interrupt Manager There are two on-chip Vector Interrupt Manager (VIM) modules. The VIM module provides hardware assistance for prioritizing and controlling the many interrupt sources present on a device. Interrupts are caused by events outside of the normal flow of program execution.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.15.3 Interrupt Request Assignments Table 6-39.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-39.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-39.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 NOTE The application can change the mapping of interrupt sources to the interrupt channels through the interrupt channel control registers (CHANCTRLx) inside the VIM module. 6.16 ECC Error Event Monitoring and Profiling This device includes an Error Profiling Controller (EPC) module.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.16.1 EPC Module Operation 6.16.1.1 Correctable Error Handling When a correctable error is detected in the system by an IP, it sends the error signal along with the error address to EPC module. The EPC module will scan this error address in the 16-entry CAM. If there is a match then the address is discard and no error is generated to ESM by the ECP. It takes one cycle to scan one address at a time through the CAM.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.17 DMA Controller The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations. Typically, the DMA is used to: • • • Transfer blocks of data between external and internal data memories Restructure portions of internal data memory Continually service a peripheral 6.17.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.17.3 Default DMA Request Map The DMA module on this microcontroller has 32 channels and up to 48 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on. Some DMA requests have multiple sources, see Table 6-41.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-41.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.17.4 Using a GIO terminal as a DMA Request Input Each GIO terminal can also directly be used as DMA request input as listed in Table 6-41. The polarity of the GIO terminal to trigger a DMA request can be selected inside the DMA module. To use the GIO terminal as a DMA request input, the corresponding select bit must be set to low. See Figure 6-19 for an illustration. For more information see the technical reference guide SPNU562.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.18 Real-Time Interrupt Module The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the time bases needed for scheduling an operating system.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 31 0 Update compare RTIUDCPy + 31 0 DMAREQy Compare RTICOMPy From counter block 0 = INTy From counter block 1 Compare control Figure 6-21. Compare Block Diagram 6.18.3 Clock Source Options The RTI module uses the RTI1CLK clock domain for generating the RTI time bases. The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the system module at address 0xFFFFFF50.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.19 Error Signaling Module The Error Signaling Module (ESM) manages the various error conditions on the TMS570LCx microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. The nERROR can be used as an indicator to an external monitor circuit to put the system into a safe state. 6.19.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-45.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-45.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-45.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-45.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.20 Reset / Abort / Error Sources Table 6-46. Reset/Abort/Error Sources SYSTEM MODE ERROR RESPONSE ESM HOOKUP GROUP.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-46. Reset/Abort/Error Sources (continued) SYSTEM MODE ERROR RESPONSE ESM HOOKUP GROUP.CHANNE L User/Privilege ESM 1.89 Memory access permission violation User/Privilege ESM 1.2 Memory ECC uncorrectable error User/Privilege ESM 1.3 Transaction Error: that is, Bus Parity Error User/Privilege ESM 1.70 Memory ECC single bit error User/Privilege ESM 1.82 DMA register soft error User/Privilege ESM 1.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 6-46. Reset/Abort/Error Sources (continued) SYSTEM MODE ERROR RESPONSE ESM HOOKUP GROUP.CHANNE L DCAN2 memory ECC single error User/Privilege ESM 1.74 DCAN3 memory ECC single error User/Privilege ESM 1.75 DCAN4 memory ECC single error User/Privilege ESM 1.76 PLL1 slip error User/Privilege ESM 1.10 PLL2 slip error User/Privilege ESM 1.42 User/Privilege ESM 1.11 DCC1 error User/Privilege ESM 1.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-46. Reset/Abort/Error Sources (continued) SYSTEM MODE ERROR RESPONSE ESM HOOKUP GROUP.CHANNE L Power-Up Reset N/A Reset N/A Oscillator fail / PLL slip (2) N/A Reset N/A Watchdog exception N/A Reset N/A CPUx Reset N/A Reset N/A Software Reset N/A Reset N/A External Reset N/A Reset N/A User/Privilege ESM 1.90 Diagnostic error User/Privilege ESM => Error terminal 3.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.21 Digital Windowed Watchdog This device includes a Digital Windowed Watchdog (DWWD) module that protects against runaway code execution (see Figure 6-22). The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.22 Debug Subsystem 6.22.1 Block Diagram The device contains an ICEPICK module (version C) to allow JTAG access to the scan chains (see Figure 6-23).
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.22.2 Debug Components Memory Map Table 6-47.
RM57L843 www.ti.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com NOTE ETM-R5, Cortex-R5F and CTI1 run at same frequency. Table 6-48.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 CTI3 TPIU FLUSHIN CTITRIGOUT[1] TRIGIN CTITRIGOUT[0] FLUSHINACK CTITRIGOUTACK[1] TRIGINACK CTITRIGOUTACK[0] 1 TIHSBYPASS[7:2] 0 CTITRIGOUTACK[7:2] Figure 6-26. CTI3 Mapping NOTE TPIU and CTI3 run at different frequencies. Table 6-49.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 6-50.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.22.4 JTAG Identification Code The JTAG ID code for this device is the same as the device ICEPick Identification Code. For the JTAG ID Code per silicon revision, see Table 6-52. Table 6-52. JTAG ID Code SILICON REVISION ID Rev A 0x0B95A02F Rev B 0x1B95A02F 6.22.5 Debug ROM The Debug ROM stores the location of the components on the Debug APB bus (see Table 6-53). Table 6-53.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.22.6 JTAG Scan Interface Timings Table 6-54. JTAG Scan Interface Timing (1) NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 6.22.7 Advanced JTAG Security Module This device includes a an Advanced JTAG Security Module (AJSM) module. The AJSM provides maximum security to the memory content of the device by letting users secure the device after programming. Flash Module Output OTP Contents (example) H L H ... ...
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.22.8 Embedded Trace Macrocell (ETM-R5) The device contains a ETM-R5 module with a 32-bit internal data port. The ETM-R5 module is connected to a Trace Port Interface Unit (TPIU) with a 32-bit data bus. The TPIU provides a 35-bit (32-bit data, 3-bit control) external interface for trace. The ETM-R5 is CoreSight compliant and follows the ETM v3 specification. For more details, see the ARM CoreSight ETM-R5 TRM specification. 6.22.8.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com ETMTRACECLK ETMDATA tsu(ETM) th(ETM) tsu(ETM) th(ETM) Figure 6-31. ETMDATA Timing Table 6-57. ETMDATA Timing PARAMETER MIN MAX UNIT tsu(ETM) Data setup time 2.5 ns th(ETM) Data hold time 1.5 ns NOTE The ETMTRACECLK and ETMDATA timing is based on a 15-pF load and for ambient temperatures lower than 85°C.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.22.9 RAM Trace Port (RTP) The RTP provides the ability to datalog the RAM contents of the RM57Dx devices or accesses to peripherals without program intrusion. It can trace all data write or read accesses to internal RAM. In addition, it provides the capability to directly transfer data to a FIFO to support a CPU-controlled transmission of the data. The trace data is transmitted over a dedicated external interface. 6.22.9.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com tssu(RTP) tsh(RTP) RTPSYNC RTPCLK RTPDATA tdsu(RTP) tdh(RTP) Figure 6-33. RTPDATA Timing Table 6-59.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.22.10 Data Modification Module (DMM) The Data Modification Module (DMM) provides the capability to modify data in the entire 4GB address space of the RM57Dx devices from an external peripheral, with minimal interruption of the application. 6.22.10.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com tssu(DMM) tsh(DMM) DMMSYNC DMMCLK DMMDATA tdsu(DMM) tdh(DMM) Figure 6-36. DMMDATA Timing Figure 6-37 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been received and synchronized to the HCLK domain.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 6.22.11 Boundary Scan Chain The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 6-38). Device Pins (conceptual) RTCK TDI TDO IC E P ICK TRST TMS TCK Boundary Scan Interface Boundary Scan TDI TDO BSDL Figure 6-38.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 7 Peripheral Information and Electrical Specifications 7.1 Enhanced Translator PWM Modules (ePWM) Figure 7-1 shows the connections between the seven ePWM modules (ePWM1–ePWM7) on the device.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Figure 7-2 shows the detailed input synchronization selection (asynchronous, double-synchronous, or double synchronous + filter width) for ePWMx. double sync TZxn (x = 1, 2, or 3) ePWMx (x = 1 through 7) 6 VCLK3 Cycles Filter Figure 7-2. ePWMx Input Synchronization Selection Detail 7.1.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.1.3 www.ti.com Synchronizing all ePWM Modules to the N2HET1 Module Time Base The connection between the NHET1_LOOP_SYNC and the SYNCI input of ePWM1 module is implemented as shown in Figure 7-3. N2HET1 N2HET1_LOOP_SYNC EXT_LOOP_SYNC N2HET2 PINMMR165[24]=0 and PINMMR165[25]=1 2 VCLK3 cycles Pulse Stretch SYNCI ePWM1 EPWM1SYNCI double sync 6 VCLK3 Cycles Filter Figure 7-3. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules 7.
RM57L843 www.ti.com 7.1.6 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 ePWM Trip Zones The ePWMx modules have 6 trip zone inputs each. These are active-low signals. The application can control the ePWMx module response to each of the trip zone input separately. The timing requirements from the assertion of the trip zone inputs to the actual response are specified in the electrical and timing section of this document. 7.1.6.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.1.6.3 www.ti.com Trip Zone TZ5n This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted whenever an oscillator failure or a PLL slip is detected on the device. The applciation can use this trip zone input for each ePWMx module to prevent the external system from going out of control when the device clocks are not within expected range (system running at limp clock).
RM57L843 www.ti.com 7.2 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Enhanced Capture Modules (eCAP) Figure 7-4 shows how the eCAP modules are interconnected on this microcontroller. EPWM1SYNCO ECAP1SYNCI see Note A VIM ECAP1INTn ECAP1 eCAP1 VBus32 VCLK3, SYS_nRST ECAP1ENCLK ECAP1SYNCO ECAP2SYNCI VIM ECAP2INTn eCAP 2/3/4/5 ECAP2 IOMUX see Note A VBus32 VCLK3, SYS_nRST ECAP2ENCLK ECAP2SYNCO ECAP6SYNCI see Note A VIM ECAP6INTn eCAP 6 ECAP6 VBus32 VCLK3, SYS_nRST ECAP6ENCLK ECAP6SYNCO A.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Figure 7-5 shows the detailed input synchronization selection (asynchronous, double-synchronous, or double synchronous + filter width) for eCAPx. ECAPx (x = 1, 2, 3, 4, 5, or 6) double sync eCAPx 6 VCLK3 Cycles Filter (x = 1 through 6) Figure 7-5. eCAPx Input Synchronization Selection Detail 7.2.
RM57L843 www.ti.com 7.2.4 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Enhanced Capture Module (eCAP) Electrical Data/Timing Table 7-9. eCAPx Timing Requirements TEST CONDITIONS tw(CAP) (1) MIN Synchronous Pulse width, capture input Synchronous with input filter MAX UNIT 2 tc(VCLK3) cycles 2 tc(VCLK3) + filter width (1) cycles The filter width is 6 VCLK3 cycles. Table 7-10.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.3 www.ti.com Enhanced Quadrature Encoder (eQEP) Figure 7-6 shows the eQEP module interconnections on the device. VBus32 see Note A EQEP1ENCLK VCLK3 SYS_nRST EPWM1/../7 VIM EQEP1I EQEP1IO EQEP1IOE EQEP1 Module EQEP1INTn EQEP1A EQEP1B EQEP1ERR TZ4n EQEP1S EQEP1SO EQEP1SOE IO Mux VBus32 see Note A EQEP2ENCLK VCLK3 SYS_nRST VIM Connection Selection Mux A.
RM57L843 www.ti.com 7.3.2 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Using eQEPx Phase Error to Trip ePWMx Outputs The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection multiplexer. This multiplexer is defined in Table 7-3. As shown in Figure 7-6, the output of this selection multiplexer is inverted and connected to the TZ4n trip-zone input of all ePWMx modules.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.4 www.ti.com 12-bit Multibuffered Analog-to-Digital Converter (MibADC) The MibADC has a separate power bus for its analog circuitry that enhances the Analog-to-Digital (A-to-D) performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO, unless otherwise noted. Table 7-15.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 7-16. MibADC1 Event Trigger Selection GROUP SOURCE SELECT BITS (G1SRC, G2SRC OR EVSRC) EVENT NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com NOTE For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring ADEVT as an output function on to the pad (through the mux control), or by driving the ADEVT signal from an external trigger source as input.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 7-17. MibADC2 Event Trigger Selection GROUP SOURCE SELECT BITS (G1SRC, G2SRC, or EVSRC) EVENT NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com NOTE For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring AD2EVT as an output function on to the pad (through the mux control), or by driving the AD2EVT signal from an external trigger source as input.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 SOCAEN, SOCBEN bits inside ePWMx modules Controlled by PINMMR EPWM1SOCA EPWM1 module EPWM1SOCB EPWM2SOCA EPWM2 module EPWM2SOCB EPWM3SOCA EPWM3 module EPWM3SOCB EPWM4SOCA EPWM4 module EPWM4SOCB EPWM5SOCA EPWM5 module EPWM5SOCB EPWM6SOCA EPWM6 module EPWM6SOCB EPWM7SOCA EPWM7 module EPWM7SOCB ePWM_B ePWM_A1 ePWM_A2 ePWM_AB Figure 7-8.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 7-18. Control Bit to SOC Output CONTROL BIT SOC OUTPUT PINMMR164[0] SOC1A_SEL PINMMR164[8] SOC2A_SEL PINMMR164[16] SOC3A_SEL PINMMR164[24] SOC4A_SEL PINMMR165[0] SOC5A_SEL PINMMR165[8] SOC6A_SEL PINMMR165[16] SOC7A_SEL The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-8. This switch is implemented by using the control registers in the PINMMR module.
RM57L843 www.ti.com 7.4.3 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 ADC Electrical and Timing Specifications Table 7-19. MibADC Recommended Operating Conditions PARAMETER MIN MAX (1) V V ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD ADREFLO A-to-D low-voltage reference source VSSAD (1) ADREFHI VAI Analog input voltage ADREFLO ADREFHI IAIC Analog input clamp current (2) (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Rext www.ti.com Pin VS1 Smux Rmux Smux Rmux IAOSB Cext On-State Bias Current Rext Pin VS2 IAIL Cext IAIL IAIL Off-State Leakages Rext Pin Smux Rmux Ssamp Rsamp VS24 IAIL Csamp Cmux Cext IAIL IAIL Figure 7-10. MibADC Input Equivalent Circuit Table 7-21. MibADC Timing Specifications PARAMETER tc(ADCLK) (1) td(SH) (2) MIN Cycle time, MibADC clock Delay time, sample and hold time NOM MAX UNIT 0.033 µs 0.2 µs 0.4 µs 0.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 7-22. MibADC Operating Characteristics Over 3.0 V to 3.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.4.4 www.ti.com Performance (Accuracy) Specifications 7.4.4.1 MibADC Nonlinearity Errors The differential nonlinearity error shown in Figure 7-11 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 0 ... 011 Differential Linearity Error (–½ LSB) 1 LSB 0 ... 010 Differential Linearity Error (–½ LSB) 0 ...
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 The integral nonlinearity error shown in Figure 7-12 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 0 ... 110 Ideal Transition Digital Output Code 0 ... 101 Actual Transition 0 ... 100 At Transition 011/100 (–½ LSB) 0 ... 011 0 ... 010 End-Point Lin. Error 0 ... 001 At Transition 001/010 (–1/4 LSB) 0 ...
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.4.4.2 www.ti.com MibADC Total Error The absolute accuracy or total error of an MibADC as shown in Figure 7-13 is the maximum value of the difference between an analog value and the ideal midstep value. 0 ... 111 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 Total Error At Step 0 ... 101 (–1 1/4 LSB) 0 ... 011 0 ... 010 Total Error At Step 0 ... 001 (1/2 LSB) 0 ... 001 0 ... 000 0 1 2 3 4 5 6 7 Analog Input Value (LSB) A.
RM57L843 www.ti.com 7.5 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 General-Purpose Input/Output The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and bit-programmable. Both GIOA and GIOB support external interrupt capability. 7.5.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.6 www.ti.com Enhanced High-End Timer (N2HET) The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O..
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 7-24.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.6.5 www.ti.com N2HET Checking 7.6.5.1 Internal Monitoring To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be used to monitor each other’s signals as shown in Figure 7-16. The direction of the monitoring is controlled by the I/O multiplexing control module.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 For more information on DCC see Section 6.7.3. 7.6.6 Disabling N2HET Outputs Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET module provides this capability through the "Pin Disable" input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.6.7 www.ti.com High-End Timer Transfer Unit (HET-TU) A High End Timer Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HET-TU. 7.6.7.1 • • • • • • • • • 7.6.7.
RM57L843 www.ti.com 7.7 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Controller Area Network (DCAN) The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.8 www.ti.com Local Interconnect Network Interface (LIN) The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility. The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a Kline.
RM57L843 www.ti.com 7.9 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Serial Communication Interface (SCI) 7.9.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 7.10 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between the RM4x microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C compatible device. 7.10.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.10.2 I2C I/O Timing Specifications Table 7-28. I2C Signals (SDA and SCL) Switching Characteristics (1) STANDARD MODE PARAMETER FAST MODE UNIT MIN MAX MIN MAX 75.2 149 75.2 149 ns 0 100 0 400 kHz tc(I2CCLK) Cycle time, Internal Module clock for I2C, prescaled from VCLK f(SCL) SCL Clock frequency tc(SCL) Cycle time, SCL 10 2.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com NOTE • • • • 188 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.11 Multibuffered / Standard Serial Peripheral Interface The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and analog-to-digital converters. 7.11.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 7.11.3.1 MIBSPI1 Event Trigger Hookup Table 7-30.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.11.3.2 MIBSPI2 Event Trigger Hookup Table 7-31.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 7-32. MIBSPI3 Event Trigger Hookup (continued) Event # TGxCTRL TRIGSRC[3:0] Trigger EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 Intern Tick counter NOTE For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary).
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.11.3.4 MIBSPI4 Event Trigger Hookup Table 7-33.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com Table 7-34. MIBSPI5 Event Trigger Hookup (continued) EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 Intern Tick counter NOTE For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary).
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications Table 7-35. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. 1 2 (5) 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 (6) 9 (6) (1) (2) (3) (4) (5) (6) Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 SPISIMO 5 Master Out Data Is Valid 6 7 Master In Data Must Be Valid SPISOMI Figure 7-18. SPI Master Mode External Timing (CLOCK PHASE = 0) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 7-19.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 7-36. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 Master Out Data Is Valid SPISIMO 6 Data Valid 7 Master In Data Must Be Valid SPISOMI Figure 7-20. SPI Master Mode External Timing (CLOCK PHASE = 1) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 7-21.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.11.5 SPI Slave Mode I/O Timings Table 7-37. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI Data Is Valid SPISOMI 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-22. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn Figure 7-23.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Table 7-38. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI SPISOMI Data Is Valid 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-24. SPI Slave Mode External Timing (CLOCK PHASE = 1) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn 10 SPISOMI Slave Out Data Is Valid Figure 7-25.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.12 Ethernet Media Access Controller The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QoS) support. The EMAC controls the flow of packet data from the device to the PHY.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 1 MII_TX_CLK MII_TXD[3:0] MII_TXEN VALID Figure 7-27. MII Transmit Timing Table 7-40.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 7.12.2 Ethernet RMII Timing 1 2 3 RMII_REFCLK 5 5 RMII_TXEN 4 RMII_TXD[1:0] 6 7 RMII_RXD[1:0] 8 RMII_CRS_DV 9 10 11 RMII_RX_ER Figure 7-28. RMII Timing Diagram Table 7-41. RMII Timing Requirements NO.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 7.12.3 Management Data Input/Output (MDIO) 1 3 3 MDCLK 4 5 MDIO (input) Figure 7-29. MDIO Input Timing Table 7-42. MDIO Input Timing Requirements NO.
RM57L843 www.ti.com SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 8 Applications, Implementation, and Layout NOTE Information in the following sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support Texas Instruments (TI) offers an extensive line of development tools for the Hercules™ Safety generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
RM57L843 www.ti.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 9.2 9.2.1 www.ti.com Documentation Support Related Documentation from Texas Instruments The following documents describe the RM57L843 microcontroller.. 9.2.2 SPNU562 RM57x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.
RM57L843 www.ti.com 9.6 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Device Identification 9.6.1 Device Identification Code Register The device identification code register is memory mapped to address FFFF FFF0h and identifies several aspects of the device including the silicon version. The details of the device identification code register are provided in Table 9-1.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 9.6.2 www.ti.com Die Identification Registers The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit die id with the information as listed in Table 9-2. Table 9-2. Die-ID Registers 212 Item # of Bits Bit Location X Coord. on Wafer 12 0xFFFFFF7C[11:0] Y Coord.
RM57L843 www.ti.com 9.7 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 Module Certifications The following communications modules have received certification of adherence to a standard.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 9.7.1 www.ti.com DCAN Certification Figure 9-3.
RM57L843 www.ti.com 9.7.2 9.7.2.1 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 LIN Certification LIN Master Mode Figure 9-4.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 9.7.2.2 www.ti.com LIN Slave Mode - Fixed Baud Rate Figure 9-5.
RM57L843 www.ti.com 9.7.2.3 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 LIN Slave Mode - Adaptive Baud Rate Figure 9-6.
RM57L843 SPNS215C – FEBRUARY 2014 – REVISED JUNE 2016 www.ti.com 10 Mechanical Data 10.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM www.ti.com 7-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) RM57L843BZWTT ACTIVE Package Type Package Pins Package Drawing Qty NFBGA ZWT 337 90 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 105 RM57 L843BZWTT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM www.ti.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
RM57Lx 16/32-Bit RISC Flash Microcontroller Technical Reference Manual Literature Number: SPNU562 May 2014
Contents Preface....................................................................................................................................... 94 1 Introduction ....................................................................................................................... 95 1.1 1.2 1.3 2 Architecture ..................................................................................................................... 101 2.1 2.2 2.3 2.4 2.5 3 Introduction ..........................
www.ti.com 3.4 4 244 245 245 246 247 248 248 249 249 Interconnect ..................................................................................................................... 250 4.1 4.2 4.3 4.4 5 3.3.3 How to Configure Timeout Check ............................................................................. SCM Registers ............................................................................................................ 3.4.1 SCM REVID Register (SCMREVID).........................
www.ti.com 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.4.10 5.4.11 5.4.12 5.4.13 5.4.14 5.4.15 5.4.16 6 6.6 6.7 Overview .................................................................................................................. Main Features of I/O Multiplexing Module (IOMM) ................................................................... Control of Multiplexed Outputs .......................................................................................... Control of Multiplexed Inputs ...............
www.ti.com 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.1.2 Definition of Terms............................................................................................... 7.1.3 F021 Flash Tools ................................................................................................ Default Flash Configuration ............................................................................................. EEPROM Emulation Support..................................................................
www.ti.com 7.12 8 8.3 Overview ................................................................................................................... Module Operation ......................................................................................................... 8.2.1 RAM Memory Map ............................................................................................... 8.2.2 Safety Features ..................................................................................................
www.ti.com 9.6 10 9.5.10 ROM Mask Register (ROM) ................................................................................... 9.5.11 ROM Algorithm Mask Register (ALGO) ..................................................................... 9.5.12 RAM Info Mask Lower Register (RINFOL) .................................................................. 9.5.13 RAM Info Mask Upper Register (RINFOU) .................................................................. PBIST Configuration Example ............
www.ti.com 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 11.4.9 11.4.10 11.4.11 11.4.12 11.4.13 12 12.3 12.4 Overview ................................................................................................................... Module Operation ......................................................................................................... 12.2.1 Uncorrectable Fault Operation ................................................................................ 12.2.
www.ti.com 14 Oscillator and PLL ............................................................................................................ 498 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 15 Introduction ................................................................................................................ 14.1.1 Features.......................................................................................................... Quick Start ......................................................
www.ti.com 16 Error Signaling Module (ESM) ............................................................................................ 538 16.1 16.2 16.3 16.4 17 539 539 539 541 541 542 543 544 545 546 546 547 547 548 548 549 549 550 550 551 552 553 553 554 554 555 555 556 556 557 557 558 559 559 560 560 561 561 562 Real-Time Interrupt (RTI) Module ........................................................................................ 563 17.1 17.2 17.3 10 Overview ..............................
www.ti.com 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 17.3.6 17.3.7 17.3.8 17.3.9 17.3.10 17.3.11 17.3.12 17.3.13 17.3.14 17.3.15 17.3.16 17.3.17 17.3.18 17.3.19 17.3.20 17.3.21 17.3.22 17.3.23 17.3.24 17.3.25 17.3.26 17.3.27 17.3.28 17.3.29 17.3.30 17.3.31 17.3.32 17.3.33 17.3.34 17.3.35 17.3.36 17.3.37 17.3.38 17.3.39 18 RTI Global Control Register (RTIGCTRL) ................................................................... RTI Timebase Control Register (RTITBCTRL) ...........................................
www.ti.com 18.3 18.4 19 614 617 617 618 618 618 619 620 620 621 622 622 623 624 626 628 630 631 631 632 632 633 633 634 634 634 635 635 635 636 636 636 637 637 638 638 639 639 639 640 640 640 641 641 Vectored Interrupt Manager (VIM) Module ............................................................................ 642 19.1 19.2 19.3 19.4 12 18.2.10 Interrupt ......................................................................................................... 18.2.11 Power Down Mode ............
www.ti.com 19.5 19.6 19.7 19.8 19.9 20 19.4.2 VIM Input Channel Management ............................................................................. Interrupt Vector Table (VIM RAM) ...................................................................................... 19.5.1 Interrupt Vector Table Operation ............................................................................. 19.5.2 VIM ECC Syndrome ............................................................................................
www.ti.com 20.3 21 21.2 21.3 21.4 Introduction ................................................................................................................ 21.1.1 Purpose of the Peripheral ..................................................................................... 21.1.2 Features.......................................................................................................... 21.1.3 Functional Block Diagram .........................................................................
www.ti.com 22.3 22.2.8 ADEVT Pin General Purpose I/O Functionality ............................................................. ADC Registers ............................................................................................................ 22.3.1 ADC Reset Control Register (ADRSTCR) .................................................................. 22.3.2 ADC Operating Mode Control Register (ADOPMODECR) ............................................... 22.3.
www.ti.com 22.3.52 22.3.53 22.3.54 22.3.55 22.3.56 22.3.57 22.3.58 22.3.59 22.3.60 22.3.61 22.3.62 22.3.63 22.3.64 22.3.65 22.3.66 22.3.67 22.3.68 22.3.69 22.3.70 22.3.71 22.3.72 22.3.73 22.3.74 22.3.75 22.3.76 22.3.77 23 Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ........................ Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) ........................ Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) .............................
www.ti.com 23.5 24 23.4.11 Interrupt Flag Register (HETFLG) .......................................................................... 23.4.12 AND Share Control Register (HETAND) .................................................................. 23.4.13 HR Share Control Register (HETHRSH) ................................................................... 23.4.14 XOR Share Control Register (HETXOR) ................................................................... 23.4.
www.ti.com 24.5 24.6 25 1092 1093 1094 1096 1096 1097 1098 1098 1099 1100 1100 1101 1102 1103 1104 1107 1107 1108 1109 1109 1110 1111 1112 1113 1114 1115 1115 1115 1116 General-Purpose Input/Output (GIO) Module ...................................................................... 1117 25.1 25.2 25.3 25.4 25.5 18 24.4.12 Interrupt Offset Register 0 (HTU INTOFF0) .............................................................. 24.4.13 Interrupt Offset Register 1 (HTU INTOFF1) .........................
www.ti.com 25.6 26 25.5.14 GIO Data Set Registers (GIODSET[A-B]) ................................................................ 25.5.15 GIO Data Clear Registers (GIODCLR[A-B]) ............................................................. 25.5.16 GIO Open Drain Registers (GIOPDR[A-B]) .............................................................. 25.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]) .......................................................... 25.5.
www.ti.com 26.9 26.10 26.11 26.12 26.13 26.14 26.15 26.16 26.17 20 26.8.12 Reading from a FIFO Buffer ............................................................................... CAN Message Transfer ................................................................................................ 26.9.1 Automatic Retransmission ................................................................................... 26.9.2 Auto-Bus-On ....................................................................
www.ti.com 26.17.27 26.17.28 26.17.29 26.17.30 26.17.31 26.17.32 26.17.33 26.17.34 27 IF3 Observation Register (DCAN IF3OBS) ............................................................. IF3 Mask Register (DCAN IF3MSK) ..................................................................... IF3 Arbitration Register (DCAN IF3ARB) ............................................................... IF3 Message Control Register (DCAN IF3MCTL) .....................................................
www.ti.com 27.4 27.5 27.6 28 1300 1301 1302 1303 1304 1305 1308 1310 1311 1312 1313 1314 1316 1317 1318 1320 1322 1323 1324 1325 1326 1327 1328 1328 1329 1331 1333 1336 1337 1338 1338 1340 1341 1341 Serial Communication Interface (SCI)/Local Interconnect Network (LIN) Module ..................... 1342 28.1 28.2 28.3 28.4 22 27.3.28 Transfer Group Interrupt Level Set Register (TGITLVST).............................................. 27.3.29 Transfer Group Interrupt Level Clear Register (TGITLVCR) .
www.ti.com 28.5 28.6 28.7 29 28.4.3 Wakeup Timeouts ............................................................................................. Emulation Mode ......................................................................................................... GPIO Functionality ...................................................................................................... 28.6.1 GPIO Functionality ............................................................................................
www.ti.com 29.4 29.5 29.6 29.7 29.8 30 1448 1449 1449 1449 1451 1451 1452 1452 1453 1454 1455 1456 1459 1461 1463 1464 1466 1470 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1481 1482 1484 1484 1484 1485 1485 1485 Inter-Integrated Circuit (I2C) Module .................................................................................. 1486 30.1 30.2 30.3 24 29.3.4 Error Interrupts ................................................................................................
www.ti.com 30.4 30.5 30.6 30.7 31 30.3.3 Slave Transmitter Mode ...................................................................................... 30.3.4 Slave Receiver Mode ........................................................................................ 30.3.5 Low Power Mode .............................................................................................. 30.3.6 Free Run Mode ................................................................................................ 30.
www.ti.com 31.3 31.4 31.5 26 31.2.2 Memory Map ................................................................................................... 31.2.3 Signal Descriptions............................................................................................ 31.2.4 MII / RMII Signal Multiplexing Control ...................................................................... 31.2.5 Ethernet Protocol Overview .................................................................................. 31.2.
www.ti.com 31.5.6 31.5.7 31.5.8 31.5.9 31.5.10 31.5.11 31.5.12 31.5.13 31.5.14 31.5.15 31.5.16 31.5.17 31.5.18 31.5.19 31.5.20 31.5.21 31.5.22 31.5.23 31.5.24 31.5.25 31.5.26 31.5.27 31.5.28 31.5.29 31.5.30 31.5.31 31.5.32 31.5.33 31.5.34 31.5.35 31.5.36 31.5.37 31.5.38 31.5.39 31.5.40 31.5.41 31.5.42 31.5.43 31.5.44 31.5.45 31.5.46 31.5.47 31.5.48 31.5.49 31.5.50 32 Receive Teardown Register (RXTEARDOWN) ...........................................................
www.ti.com 32.4 32.5 33 32.3.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger .................................... 32.3.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ...................... 32.3.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger .................................. 32.3.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger .................... Application of the APWM Mode ................................
www.ti.com 34.1 34.2 34.3 34.4 35 Introduction ............................................................................................................... 34.1.1 Submodule Overview ......................................................................................... 34.1.2 Register Mapping ............................................................................................. ePWM Submodules .................................................................................................
www.ti.com 35.3.13 35.3.14 35.3.15 35.3.16 35.3.17 35.3.18 35.3.19 35.3.20 35.3.21 35.3.22 35.3.23 35.3.24 36 36.2 36.3 Overview.................................................................................................................. 36.1.1 Features ........................................................................................................ 36.1.2 Block Diagram ................................................................................................. Module Operation .......
www.ti.com 37.4.5 EFC Self Test Signature Register (EFCSTSIG) ..........................................................
www.ti.com List of Figures 1-1. Block Diagram .............................................................................................................. 99 1-2. Example: SPIDELAY – 0xFFF7F448 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 2-10. 2-11. 2-12. 2-13. 2-14. 2-15. 2-16. 2-17. 2-18. 2-19. 2-20. 2-21. 2-22. 2-23. 2-24. 2-25. 2-26. 2-27. 2-28. 2-29. 2-30. 2-31. 2-32. 2-33. 2-34. 2-35. 2-36. 2-37. 2-38. 2-39. 2-40. 2-41. 2-42. 2-43. 2-44. 2-45. 32 ..............................................
www.ti.com 2-46. RAM Control Register (RAMGCR) (offset = C0h) .................................................................... 179 2-47. Bus Matrix Module Control Register 1 (BMMCR) (offset = C4h) ................................................... 180 2-48. CPU Reset Control Register (CPURSTCR) (offset = CCh) 2-49. Clock Control Register (CLKCNTL) (offset = D0h) ................................................................... 181 2-50. ECP Control Register (ECPCNTL) (offset = D4h) ........
www.ti.com 2-95. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) (offset = ACh) ................................... 222 2-96. Debug Frame Powerdown Set Register (PDPWRDWNSET) (offset = C0h) 2-97. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) (offset = C4h) ................................... 223 2-98. MasterID Protection Write Enable Register (MSTIDWRENA) (offset = 200h) .................................... 223 2-99. MasterID Enable Register (MSTIDENA) (offset = 204h) ...................
www.ti.com 5-8. Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0) (offset = 40h) ..................... 276 5-9. Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1) (offset = 44h) ..................... 277 5-10. Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2) (offset = 48h) ..................... 278 5-11. Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3) (offset = 4Ch) ..................... 279 5-12.
www.ti.com 7-16. Primary Address Tag Register (FPRIM_ADD_TAG) (offset = 28h) ................................................ 346 7-17. Duplicate Address Tag Register (FDUP_ADD_TAG) (offset = 2Ch) 346 7-18. Flash Bank Protection Register (FBPROT) (offset = 30h) 347 7-19. 7-20. 7-21. 7-22. 7-23. 7-24. 7-25. 7-26. 7-27. 7-28. 7-29. 7-30. 7-31. 7-32. 7-33. 7-34. 7-35. 7-36. 7-37. 7-38. 7-39. 7-40. 7-41. 7-42. 7-43. 7-44. 7-45. 7-46. 7-47. 7-48. 7-49. 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. 8-8. 8-9. 8-10.
www.ti.com 9-5. PBIST Activate/ROM Clock Enable Register (PACT) [offset = 0180h] ............................................ 398 9-6. PBIST ID Register [offset = 184h] ...................................................................................... 399 9-7. Override Register (OVER) [offset = 0188h] ........................................................................... 400 9-8. Fail Status Fail Register 0 (FSRF0) [offset = 0190h] 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18.
www.ti.com 11-9. MPU Error Address Register (MPUERRADDR) (offset = 14h) ..................................................... 457 11-10. MPU Control Register 1 (MPUCTRL1) (offset = 20h)................................................................ 457 11-11. MPU Control Register 2 (MPUCTRL2) (offset = 24h)................................................................ 458 11-12. MPU Type Register (MPUTYPE) (offset = 2Ch) ...................................................................... 459 11-13.
www.ti.com 15-7. 15-8. 15-9. 15-10. 15-11. 15-12. 15-13. 15-14. 15-15. 15-16. 15-17. 16-1. 16-2. 16-3. 16-4. 16-5. 16-6. 16-7. 16-8. 16-9. 16-10. 16-11. 16-12. 16-13. 16-14. 16-15. 16-16. 16-17. 16-18. 16-19. 16-20. 16-21. 16-22. 16-23. 16-24. 16-25. 16-26. 16-27. 16-28. 16-29. 16-30. 16-31. 16-32. 16-33. 16-34. 16-35. 16-36. 16-37. 16-38. ................................................................... DCC Revision Id Register (DCCREV) [offset = 4h] ....................................................
www.ti.com 16-39. ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) [offset = 94h] ......................................... 561 16-40. ESM Status Register 7 (ESMSR7) [offset = 98h] .................................................................... 562 17-1. RTI Block Diagram........................................................................................................ 565 17-2. Counter Block Diagram .....................................................................................
www.ti.com 17-48. RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h] ..................................................... 603 17-49. RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h] ..................................................... 604 17-50. RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh] .................................................... 604 18-1. CRC Controller Block Diagram For One Channel .................................................................... 607 18-2.
www.ti.com 19-5. VIM in Default State ...................................................................................................... 650 19-6. VIM in a Programmed State ............................................................................................. 650 19-7. Interrupt Channel Management ......................................................................................... 651 19-8. VIM Interrupt Address Memory Map .............................................................
www.ti.com 20-8. DMA Indexing Example 2 ................................................................................................ 685 20-9. Fixed Priority Scheme .................................................................................................... 685 20-10. Example of Priority Queues ............................................................................................. 686 20-11. Example Channel Assignments ..................................................................
www.ti.com 20-57. FTC Interrupt Flag Register (FTCFLAG) [offset = 124h] ............................................................ 728 ............................................................ ........................................................... 20-60. BTC Interrupt Flag Register (BTCFLAG) [offset = 13Ch]............................................................ 20-61. BER Interrupt Flag Register (BERFLAG) [offset = 144h] ............................................................ 20-62.
www.ti.com 20-106. DMA ECC Single Bit Error Address Register (DMAECCSBE) [offset = 230h] .................................. 759 20-107. FIFO A Status Register (FIFOASTAT) [offset = 240h] ............................................................. 760 20-108. FIFO B Status Register (FIFOBSTAT) [offset = 244h] ............................................................. 760 ......................................... 20-110. DMA Request Polarity Select Register (DMAREQPS0) [offset = 334h] .................
www.ti.com 22-1. 22-2. 22-3. 22-4. 22-5. 22-6. 22-7. 22-8. 22-9. 22-10. 22-11. 22-12. 22-13. 22-14. 22-15. 22-16. 22-17. 22-18. 22-19. 22-20. 22-21. 22-22. 22-23. 22-24. 22-25. 22-26. 22-27. 22-28. 22-29. 22-30. 22-31. 22-32. 22-33. 22-34. 22-35. 22-36. 22-37. 22-38. 22-39. 22-40. 22-41. 22-42. 22-43. 22-44. 22-45. 22-46. 22-47. 22-48. 22-49. 46 ............................................................................ ADC Block Diagram ...................................................................
www.ti.com ...................................................... ADC Group1 Status Register (ADG1SR) [offset = 70h] ............................................................. ADC Group2 Status Register (ADG2SR) [offset = 74h] ............................................................. ADC Event Group Channel Select Register (ADEVSEL) [offset = 78h] ........................................... ADC Group1 Channel Select Register (ADG1SEL) [offset = 7Ch] .................................................
www.ti.com 22-99. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) [offset = 188h] ................................. 923 22-100. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) (offset = 190h) ....................................................................................................................... 924 22-101. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 194h) .... 924 22-102.
www.ti.com 23-39. Offset Index Priority Level 2 Register (HETOFF2) ................................................................... 972 23-40. Interrupt Enable Set Register (HETINTENAS) ....................................................................... 973 23-41. Interrupt Enable Clear (HETINTENAC) ................................................................................ 973 ..............................................................................
www.ti.com 23-88. APCNT Control Field (C31:C0) ........................................................................................ 1015 23-89. APCNT Data Field (D31:D0) ........................................................................................... 1015 23-90. BR Program Field (P31:P0) ............................................................................................ 1018 23-91. BR Control Field (C31:C0) ............................................................................
www.ti.com 23-137. SCMP Control Field (C31:C0) ........................................................................................ 1053 23-138. SCMP Data Field (D31:D0) ........................................................................................... 1053 23-139. SCNT Program Field (P31:P0) ....................................................................................... 1055 23-140. SCNT Control Field (C31:C0) ...........................................................................
www.ti.com 24-36. Module Identification Register (HTU ID) [offset = 60h] ............................................................. 1101 24-37. Parity Control Register (HTU PCR) [offset = 64h] .................................................................. 1102 24-38. Parity Address Register (HTU PAR) [offset = 68h] ................................................................. 1103 24-39. Memory Protection Control and Status Register (HTU MPCS) [offset = 70h]...................................
www.ti.com 26-13. CAN Interrupt Topology 1 .............................................................................................. 1171 26-14. CAN Interrupt Topology 2 .............................................................................................. 1172 26-15. Local Power Down Mode Flow Diagram ............................................................................. 1174 ..............................................................................................
www.ti.com 26-62. IF1 Message Control Register (DCAN IF1MCTL) [offset = 10Ch] ................................................ 1210 26-63. IF2 Message Control Register (DCAN IF2MCTL) [offset = 12Ch] ................................................ 1210 26-64. IF1 Data A Register (DCAN IF1DATA) [offset = 110h] ............................................................. 1212 26-65. IF1 Data B Register (DCAN IF1DATB) [offset = 114h] ............................................................. 1212 26-66.
www.ti.com 27-32. SPI Global Control Register 0 (SPIGCR0) [offset = 00h] .......................................................... 1262 27-33. SPI Global Control Register 1 (SPIGCR1) [offset = 04h] .......................................................... 1263 27-34. SPI Interrupt Register (SPIINT0) [offset = 08h] ..................................................................... 1264 27-35. SPI Interrupt Level Register (SPILVL) [offset = 0Ch] ..........................................................
www.ti.com 27-79. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) [offset = 138h] ...................................................................................................................... 1320 27-80. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) [offset = 13Ch]...................................................................................................................... 1322 27-81.
www.ti.com 28-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence .............................................. 1380 28-26. Wakeup Signal Generation ............................................................................................ 1384 28-27. GPIO Functionality ...................................................................................................... 1386 28-28. SCI Global Control Register 0 (SCIGCR0) (offset = 00) .....................................................
www.ti.com 29-14. SCI Flags Register (SCIFLR) [offset = 1Ch] ......................................................................... 1466 29-15. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h] ...................................................... 1470 29-16. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h] ...................................................... 1470 ....................................................... Baud Rate Selection Register (BRS) [offset = 2Ch] ............
www.ti.com 30-31. I2C Pin Direction Register (I2CPDIR) [offset = 4Ch] ............................................................... 1518 30-32. I2C Data Input Register (I2CDIN) [offset = 50h] .................................................................... 1518 30-33. I2C Data Output Register (I2CDOUT) [offset 0x54] ................................................................ 1519 30-34. I2C Data Set Register (I2CDSET) [offset = 58h] ............................................................
www.ti.com 31-40. Transmit Control Register (TXCONTROL) (offset = 04h) .......................................................... 1600 31-41. Transmit Teardown Register (TXTEARDOWN) (offset = 08h) .................................................... 1601 31-42. Receive Revision ID Register (RXREVID) (offset = 10h) .......................................................... 1601 31-43. Receive Control Register (RXCONTROL) (offset = 14h) .......................................................... 1602 31-44.
www.ti.com 32-1. Capture and APWM Modes of Operation ............................................................................ 1646 32-2. Capture Function Diagram ............................................................................................. 1647 32-3. Event Prescale Control ................................................................................................. 1648 32-4. Prescale Function Waveforms .........................................................................
www.ti.com 33-25. eQEP Index Position Latch Register (QPOSILAT) [offset = 10h] ................................................. 1697 33-26. eQEP Strobe Position Latch Register (QPOSSLAT) [offset = 14h] .............................................. 1697 33-27. eQEP Position Counter Latch Register (QPOSLAT) [offset = 18h]............................................... 1698 33-28. eQEP Unit Timer Register (QUTMR) [offset = 1Ch] ................................................................ 1698 33-29.
www.ti.com EPWMxB — Complementary .......................................................................................... 1743 34-26. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active Low ........................................................................................................................ 1744 34-27. Dead_Band Submodule ................................................................................................ 1745 34-28.
www.ti.com 34-72. Action-Qualifier Software Force Register (AQSFRC) [offset = 1A] ............................................... 1796 34-73. Action-Qualifier Output B Control Register (AQCTLB) [offset = 18h] ............................................ 1797 34-74. Action-Qualifier Continuous Software Force Register (AQCSFRC) [offset = 1Ch] ............................. 1798 ................................................. 34-76. Dead-Band Generator Falling Edge Delay Register (DBFED) [offset = 22h] .
www.ti.com 35-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) [offset = 38h, 48h, 58h, 68h] .............................. 1857 35-22. DMM Pin Control 0 (DMMPC0) [offset = 6Ch] ...................................................................... 1858 35-23. DMM Pin Control 1 (DMMPC1) [offset = 70h] ....................................................................... 1859 35-24. DMM Pin Control 2 (DMMPC2) [offset = 74h] .......................................................................
www.ti.com List of Tables 2-1. Definition of Terms........................................................................................................ 104 2-2. Module Registers / Memories Memory Map 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 2-10. 2-11. 2-12. 2-13. 2-14. 2-15. 2-16. 2-17. 2-18. 2-19. 2-20. 2-21. 2-22. 2-23. 2-24. 2-25. 2-26. 2-27. 2-28. 2-29. 2-30. 2-31. 2-32. 2-33. 2-34. 2-35. 2-36. 2-37. 2-38. 2-39. 2-40. 2-41. 2-42. 2-43. 2-44. 2-45. 2-46. 2-47. 66 .....................................
www.ti.com 2-48. Die Identification Register, Upper Word (DIEIDH) Field Descriptions ............................................. 166 2-49. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions.......................................... 167 2-50. Clock Test Register (CLKTEST) Field Descriptions.................................................................. 170 2-51. DFT Control Register (DFTCTRLREG) Field Descriptions ..........................................................
www.ti.com 2-97. 2-98. 2-99. 2-100. 2-101. 2-102. 2-103. 2-104. 2-105. 2-106. 2-107. 2-108. 2-109. 2-110. 2-111. 2-112. 2-113. 2-114. 2-115. 2-116. 2-117. 2-118. 2-119. 2-120. ....................................... Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions ................... Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions ................... Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) Field Descriptions ...............
www.ti.com 4-11. Error Transaction Signature Register (ERR_TRANS_SIGNATURE) Field Descriptions ........................ 261 4-12. Error Transaction Type Register (ERR_TRANS_TYPE) Field Descriptions ...................................... 261 4-13. Error User Parity Register (ERR_USER_PARITY) Field Descriptions 4-14. Slave Error Unexpected Master ID Register (SERR_UNEXPECTED_MID) Field Descriptions ............... 262 4-15. Slave Error Address Decode Register (SERR_ADDR_DECODED) Field Descriptions..
www.ti.com 7-1. ECC Encoding............................................................................................................. 326 7-2. Syndrome Table 7-3. Alternate Syndrome Table ............................................................................................... 328 7-4. TI OTP Bank 0 Sector Information Field Descriptions ............................................................... 330 7-5. TI OTP Sector Information Address ..............................................
www.ti.com 7-50. POM Flag Register (POMFLG) Field Descriptions ................................................................... 367 7-51. POM Region Start Address Register (POMPROGSTARTx) Field Descriptions.................................. 368 7-52. POM Overlay Region Start Address Register (POMOVLSTARTx) Field Descriptions .......................... 368 7-53. POM Region Size Register (POMREGSIZEx) Field Descriptions .................................................. 369 8-1.
www.ti.com 10-16. CORE1 Current MISR Register (CORE1_CURMISRn) Field Descriptions ....................................... 434 10-17. CORE2 Current MISR Register (CORE2_CURMISRn) Field Descriptions ....................................... 435 10-18. Signature Compare Self-Check Regsiter (STCSCSCR) Field Descriptions ...................................... 436 10-19. STC Current ROM Address Register (STCCADDR2) Field Descriptions ......................................... 436 10-20.
www.ti.com 13-16. CCM-R5F Key Register 4 (CCMKEYR4) Field Descriptions ........................................................ 496 13-17. CCM-R5FPower Domain Status Register 0 (CCMPDSTAT0) Field Descriptions................................ 497 14-1. Valid Frequency Ranges for PLL ....................................................................................... 506 14-2. PLL Value Encoding ......................................................................................................
www.ti.com ................................... ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) Field Descriptions ................................. ESM Interrupt Level Set/Status Register 7 (ESMILSR7) Field Descriptions ...................................... ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) Field Descriptions ................................... ESM Status Register 7 (ESMSR7) Field Descriptions ............................................................... RTI Registers ......
www.ti.com 18-4. CRC Control Registers ................................................................................................... 621 18-5. CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions 622 18-6. CRC Global Control Register 1 (CRC_CTRL1) Field Descriptions 622 18-7. 18-8. 18-9. 18-10. 18-11. 18-12. 18-13. 18-14. 18-15. 18-16. 18-17. 18-18. 18-19. 18-20. 18-21. 18-22. 18-23. 18-24. 18-25. 18-26. 18-27. 18-28. 18-29. 18-30. 18-31. 18-32. 18-33. 18-34. 18-35. 18-36. 18-37.
www.ti.com 19-15. Pending Interrupt Read Location Registers (INTREQ) Field Descriptions ........................................ 667 ................................................ ............................................. Wake-Up Enable Set Registers (WAKEENASET) Field Descriptions ............................................. Wake-Up Enable Clear Registers (WAKEENACLR) Field Descriptions........................................... IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions ........
www.ti.com .......................................... HBC Interrupt Enable Reset Register (HBCINTENAR) Field Descriptions ....................................... BTC Interrupt Enable Reset Register (BTCINTENAS) Field Descriptions ........................................ BTC Interrupt Enable Reset Register (BTCINTENAR) Field Descriptions ........................................ Global Interrupt Flag Register (GINTFLAG) Field Descriptions ....................................................
www.ti.com 20-89. DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) Field Descriptions ................. 756 20-90. DMA Memory Protection Region 6 End Address Register (DMAMPR6E) Field Descriptions .................. 756 20-91. DMA Memory Protection Region 7 Start Address Register (DMAMPR7S) Field Descriptions ................. 757 20-92. DMA Memory Protection Region 7 End Address Register (DMAMPR7E) Field Descriptions .................. 757 20-93.
www.ti.com ................................................... Asynchronous n Configuration Register (CEnCFG) Field Descriptions ........................................... SDRAM Timing Register (SDTIMR) Field Descriptions.............................................................. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ...................................... EMIF Interrupt Raw Register (INTRAW) Field Descriptions ........................................................
www.ti.com 22-34. ADC Event Group Status Register (ADEVSR) Field Descriptions ................................................. 893 ....................................................... ....................................................... ADC Event Group Channel Select Register (ADEVSEL) Field Descriptions ..................................... ADC Group1 Channel Select Register (ADG1SEL) Field Descriptions ...........................................
www.ti.com ................................ ADC Group2 Maximum Count Register (ADG2MAXCOUNT) Field Descriptions ................................ N2HET RAM Base Addresses .......................................................................................... N2HET RAM Bank Structure ............................................................................................ Pin Safe State Upon Parity Error Detection ...........................................................................
www.ti.com 23-48. NHET Pin Disable Register (HETPINDIS) Field Descriptions ...................................................... 993 ..................................................................................................... 994 ...................................................................................... 995 Interrupt Capable Instructions ........................................................................................... 995 Arithmetic / Bitwise Logic Sub-Opcodes .............
www.ti.com 24-24. Interrupt Offset Register 0 (HTU INTOFF0) Field Descriptions ................................................... 1092 24-25. Interrupt Offset Register 1 (HTU INTOFF1) Field Descriptions ................................................... 1093 24-26. Buffer Initialization Mode Register (HTU BIM) Field Descriptions ................................................ 1094 24-27. Buffer Initialization ...............................................................................................
www.ti.com 26-1. Parameters of the CAN Bit Time ...................................................................................... 1147 26-2. Message Object Field Descriptions ................................................................................... 1154 26-3. Message RAM Addressing in Debug/Suspend and RDA Mode .................................................. 1156 26-4. Message Interface Register Sets 1 and 2 26-5. 26-6. 26-7. 26-8. 26-9. 26-10. 26-11. 26-12. 26-13. 26-14. 26-15.
www.ti.com 27-16. SPI Pin Control Register 2 (SPIPC2) Field Descriptions........................................................... 1273 27-17. SPI Pin Control Register 3 (SPIPC3) Field Descriptions........................................................... 1274 27-18. SPI Pin Control Register 4 (SPIPC4) Field Descriptions........................................................... 1275 27-19. SPI Pin Control Register 5 (SPIPC5) Field Descriptions...........................................................
www.ti.com 28-2. 28-3. 28-4. 28-5. 28-6. 28-7. 28-8. 28-9. 28-10. 28-11. 28-12. 28-13. 28-14. 28-15. 28-16. 28-17. 28-18. 28-19. 28-20. 28-21. 28-22. 28-23. 28-24. 28-25. 28-26. 28-27. 28-28. 28-29. 28-30. 28-31. 28-32. 28-33. 28-34. 28-35. 28-36. 28-37. 28-38. 28-39. 28-40. 28-41. 28-42. 28-43. 28-44. 28-45. 28-46. 28-47. 28-48. 29-1. 29-2. 86 ........................................ SCI Mode (Minimum Configuration) ..................................................................................
www.ti.com 29-3. SCI Control Registers Summary ...................................................................................... 1454 29-4. SCI Global Control Register 0 (SCIGCR0) Fied Descriptions ..................................................... 1455 29-5. SCI Global Control Register 1 (SCIGCR1) Field Descriptions .................................................... 1456 29-6. SCI Set Interrupt Register (SCISETINT) Field Descriptions .......................................................
www.ti.com 30-19. I2C Interrupt Vector Register (I2CIVR) Field Descriptions ......................................................... 1514 30-20. Interrupt Codes for INTCODE Bits .................................................................................... 1514 30-21. I2C Extended Mode Register (I2CEMDR) Field Descriptions ..................................................... 1515 30-22. I2C Prescale Register (I2CPSC) Field Descriptions ...............................................................
www.ti.com 31-32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions .... 1590 31-33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .. 1591 31-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions .............................................................................................................. 1592 31-35. MDIO User Access Register 0 (USERACCESS0) Field Descriptions..
www.ti.com 31-79. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ................................... 1629 31-80. Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................. 1630 31-81. Transmit Pause Timer Register (TXPAUSE) Field Descriptions .................................................. 1630 31-82. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions .......................................... 1631 31-83.
www.ti.com 33-27. eQEP Capture Period Latch Register (QCPRDLAT) Field Descriptions ......................................... 1711 34-1. ePWM Module Control and Status Register Set Grouped by Submodule ....................................... 1716 34-2. Submodule Configuration Parameters................................................................................ 1717 34-3. Time-Base Submodule Registers ..................................................................................... 1719 34-4.
www.ti.com 34-49. Event-Trigger Clear Register (ETCLR) Field Descriptions......................................................... 1815 34-50. PWM-Chopper Control Register (PCCTL) Bit Descriptions ....................................................... 1816 34-51. Digital Compare A Control Register (DCACTL) Field Descriptions ............................................... 1818 34-52. Digital Compare Trip Select (DCTRIPSEL) Field Descriptions....................................................
www.ti.com 36-8. RTP Global Control Register (RTPGLBCTRL) Field Descriptions ................................................ 1881 36-9. FIFO Corresponding Addresses....................................................................................... 1883 36-10. Pins Used for Data Communication .................................................................................. 1883 36-11. RTP Trace Enable Register (RTPTRENA) Field Descriptions ....................................................
Preface SPNU562 – May 2014 Read This First About This Manual This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device. Related Documentation From Texas Instruments For a complete listing of related documentation and development-support tools, visit the Texas Instruments website at www.ti.com.
Chapter 1 SPNU562 – May 2014 Introduction Topic 1.1 1.2 1.3 ........................................................................................................................... Page Designed for Safety Applications ......................................................................... 96 Family Description ............................................................................................. 97 Endianism Considerations ...................................................................
Designed for Safety Applications 1.1 www.ti.com Designed for Safety Applications The RM57Lx device architecture has been designed from the ground up to simplify development of functionally safe systems. The basic architectural concept is known as a safe island approach. Power, clock, reset, and basic processing function are protected to a high level of diagnostic coverage in hardware.
Family Description www.ti.com 1.2 Family Description The RM57Lx family of microcontrollers are cache-based architecture based on the ARM® Cortex™-R5F Floating Point CPU which offers an efficient 1.66 DMIPS/MHz performance and has configurations which can run up to 330 MHz providing up to 498 DMIPS. The device supports the little-endian [LE] format. The RM57Lx has up to 4MB integrated Flash and up to 512KB data RAM configurations with single bit error correction and double bit error detection.
Family Description www.ti.com The Direct Memory Access Controller (DMA) is capable of issuing multi-threaded transactions at the same time. It can support up to 48 DMA requests which can be mapped to any one of the 32 channels. 32 control packets implemented in RAM to store channel control information are ECC protected. A first level Memory Protection Unit (MPU) is built into the DMA and a second level standalone Enhanced Memory Protection Unit (NMPU) further protect memory against erroneous transfers.
Family Description www.ti.
Endianism Considerations 1.3 www.ti.com Endianism Considerations 1.3.1 RM57Lx: Little Endian (LE) The RM57Lx family is based on the ARM® Cortex™-R5F core. ARM has designed this core to be used in big-endian and little-endian systems. For the TI RM57Lx family, the endianness has been configured to little-endian. Little-endian systems store the least-significant byte of a multi-byte data field in the lowest memory address. Also, the address of the multi-byte data field is the lowest address.
Chapter 2 SPNU562 – May 2014 Architecture This chapter consists of five sections. The first section describes specific aspects of the device architecture. The second section describes the clocking structure of the microcontrollers. The third section gives an overview of the device memory organization. The fourth section details exceptions on the device, and the last section describes the system and peripheral control registers of the microcontroller. Topic .................................................
Introduction 2.1 www.ti.com Introduction The RM57Lx family of microcontrollers is based on the Texas Instruments TMS570 Architecture. This chapter describes specific aspects of the architecture as applicable to the family of microcontrollers. 2.1.1 Architecture Block Diagram The RM57Lx microcontrollers are based on the TMS570 Platform architecture, which defines the interconnect between the bus masters and the bus slaves.
Introduction www.ti.com Figure 2-1.
Introduction www.ti.com 2.1.2 Definitions of Terms Table 2-1 provides a definition of terms used in the architectural block diagram. Table 2-1. Definition of Terms Acronym/Term Full Form Description ECC Error Correction Code This is a code that is used by the Single Error Correction Double Error Detection (SECDED) logic inside the two Cortex-R5F processors (CPUs) and various modules that support ECC. Depending on the memory configuration, the number of ECC bits may vary.
Introduction www.ti.com Table 2-1. Definition of Terms (continued) Acronym/Term Full Form Description CPU Interconnect Subsystem CPU Side Switched Central Resource Controller This is one of the two main SCRs in the device. It arbitrates between the accesses from multiple bus masters to the bus slaves using a round robin priority scheme.
Introduction www.ti.com Table 2-1. Definition of Terms (continued) Acronym/Term Full Form Description DCANx Controller Area Network controller The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps).
Introduction www.ti.com Table 2-1. Definition of Terms (continued) Acronym/Term Full Form Description EPC Error Profiling Controller This module is used to profile the occurrences of single bit and double bit ECC errors detected by the CPU and the CPU Interconnect Subsystem. SCM SCR Control Module This module is used to change certain configurations such as timeout counters of the CPU Interconnect Subsystem. This module is also used to initiate selftest for the CPU Interconnect Subsystem.
Introduction www.ti.com 2.1.5 Interconnect Subsystem Runtime Status Other than the runtime checker status as described in Section 2.1.4, the CPU Interconnect Subsystems and the Peripheral Interconnect Subsystem in the microcontroller also generates several status onto the system that are captured in the SCM (SCR Control Module). Table 4-4 lists the SCM register bit mapping. 2.1.
Memory Organization www.ti.com 2.2 Memory Organization 2.2.1 Memory Map Overview The Cortex-R5F uses a 32-bit address bus, giving it access to a memory space of 4GB. This space is divided into several regions, each addressed by different memory selects. Figure 2-3 shows the memory map of the microcontroller. The main flash instruction memory is addressed starting at 0x00000000 by default.
Memory Organization www.ti.com Figure 2-3.
Memory Organization www.ti.com 2.2.2 Memory Map Table The control and status registers for each module are mapped within the CPU’s 4GB memory space. Some modules also have associated memories, which are also mapped within this space. Table 2-2 shows the starting and ending addresses of each module’s register frame and any associated memory.
Memory Organization www.ti.com Table 2-2.
Memory Organization www.ti.com Table 2-2.
Memory Organization www.ti.com Table 2-2. Module Registers / Memories Memory Map (continued) Address Range Response for Access to Unimplemented Locations in Frame Target Name Memory Select Start End Frame Size Actual Size MIBADC1 RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128kB 8kB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. 384 bytes Look-Up Table for ADC1 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F.
Memory Organization www.ti.com Table 2-2.
Memory Organization www.ti.com Table 2-2.
Memory Organization www.ti.com Table 2-2.
Memory Organization 2.2.3.1 www.ti.com Flash Bank Sectoring Configuration The bank is divided into multiple sectors. A flash sector is the smallest region in the flash bank that must be erased. The sectoring configuration of each flash bank is shown in Table 2-3. • The Flash banks are 288-bit wide bank with ECC support. • The flash bank7 can be programmed while executing code from flash bank0. • Code execution is not allowed from flash bank7. Table 2-3.
Memory Organization www.ti.com 2.2.3.2 ECC Protection for Flash Accesses The RM57Lx microcontrollers protect all accesses to the on-chip level 2 flash memory by dedicated Single-Error-Correction-Double-Error-Detection (SECDED) logic. The access to the program memory – flash bank 0, 1 and 7 are protected by SECDED logic implemented inside the ARM Cortex-R5F CPU.
Memory Organization www.ti.com Figure 2-4.
Memory Organization www.ti.com Table 2-4.
Memory Organization www.ti.com 2.2.4 On-Chip SRAM Several SRAM modules are implemented on the device to support the functionality of the modules included. Reads from both the level 1 and level 2 SRAM are protected by ECC calculated inside the CPU. Reads from all other memories are protected by either the parity with configurable odd or even parity scheme or ECC that is evaluated in parallel with the actual read.
Memory Organization www.ti.com Table 2-5.
Memory Organization www.ti.com Table 2-6 maps the different algorithms supported in application mode for the RAM groups. The table also lists the background pattern options available for each algorithm. Table 2-6. PBIST Algorithm Mapping Sr. No.
Memory Organization www.ti.com 2.2.4.2 Auto-Initialization of On-Chip SRAM Modules The device system provides the capability to perform a hardware initialization on most memories on the system bus and on the peripheral bus. The intent of having the hardware initialization is to program the memory arrays with error detection capability to a known state based on their error detection scheme – odd/even parity or ECC. For example, the contents of the CPU level 2 SRAM after power-on reset is unknown.
Memory Organization www.ti.com Table 2-7. Memory Initialization Select Mapping Connecting Module Memory Protection Scheme Base Address Ending Address SYS.MSINENA Register Bit # L2RAMW.
Exceptions www.ti.com 2.3 Exceptions An “Exception” is an event that makes the processor temporarily halt the normal flow of program execution, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the processor preserves the critical parts of the current processor state so that the original program can resume when the handler routine has finished. The following sections describe three exceptions – Reset, Abort and the System Software Interrupts.
Exceptions 2.3.2.1 www.ti.com Prefetch Aborts When a Prefetch Abort (PABT) occurs, the processor marks the prefetched instruction as invalid, but does not take the exception until the instruction is to be executed. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. All prefetch aborts are precise aborts. 2.3.2.2 Data Aborts An error occurring on a data memory access can generate a data abort.
Exceptions www.ti.com 2.3.2.5 Conditions That Generate Aborts An Abort is generated under the following conditions on the RM57Lx microcontrollers. • Access to an illegal address (a non-implemented address) • Access to a protected address (protection violation) • Parity / ECC / Time-out Error on a valid access Illegal Addresses: The illegal addresses and the responses to an access to these addresses are defined in Table 2-2.
Clocks 2.4 www.ti.com Clocks This section describes the clocking structure of the RM57Lx microcontrollers. 2.4.1 Clock Sources The devices support up to 7 clock sources. These are shown in Table 2-9. The electrical specifications as well as timing requirements for each of the clock sources are specified in the device data manual. Table 2-9. Clock Sources 2.4.1.1 Clock Source # Clock Source Name 0 OSCIN Main oscillator.
Clocks www.ti.com 2.4.2 Clock Domains The clocking on this device is divided into multiple clock domains for flexibility in control as well as clock source selection. There are 10 clock domains on this device. Each of these are described in Table 2-10. Each of the control registers listed in Table 2-10 are defined in Section 2.5. The AC timing characteristics for each clock domain are specified in the device data manual. Table 2-10.
Clocks www.ti.com Table 2-10. Clock Domains (continued) Clock Domain RTICLK 2.4.2.1 Clock Disable Bit CDDIS.
Clocks www.ti.com 2.4.3 Low Power Modes All clock domains are active in the normal operating mode. This is the default mode of operation. As described in Section 2.4.1.1 and Section 2.4.2.1, the application can choose to disable any particular clock source and domain that it does not plan to use. Also, the peripheral central resource controller (PCR) has control registers to enable / disable the peripheral clock (VCLK) for each peripheral select.
Clocks www.ti.com 2.4.3.1 Typical Software Sequence to Enter a Low-Power Mode 1. Disable all non-CPU bus masters so they do not carry out any further bus transactions. 2. Program the flash banks and flash pump fall-back modes to be “sleep”. The flash pump transitions from active to sleep mode only after all the flash banks have switched from active to sleep mode. 3. Disable the clock sources that are not required to be kept active.
Clocks www.ti.com The signal to be brought out on to the ECLK1 terminal is defined by the SEL_ECP_PIN field, and the signal to be brought out on to the N2HET1[12] terminal is defined by the SEL_GIO_PIN field. The choices for these selections are defined in Table 2-12. Table 2-12.
Clocks www.ti.com 2.4.5 Embedded Trace Macrocell (ETM-R5) The RM57Lx microcontrollers contain an ETM-R5 module with a 32-bit internal data port. The ETM-R5 module is connected to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data and 3-bit control) external interface for trace. The ETM-R5 is CoreSight compliant and follows the ETM v3 specification; for more details see the ARM CoreSight ETM-R5 TRM specification.
Clocks www.ti.com 2.4.6.1 Oscillator Monitor The oscillator clock frequency is monitored by a dedicated circuitry called CLKDET using the HF LPO as the reference clock. The CLKDET flags an oscillator fail condition whenever the OSCIN frequency falls outside of a range which is defined by the HF LPO frequency. The valid OSCIN range is defined as a minimum of f(HF LPO) / 4 to a maximum of f(HF LPO) * 4. The untrimmed HF LPO frequency on this device can range from 5.5 MHz to 19.5 MHz.
Clocks www.ti.com 2.4.6.4.1 DCC1 As can be seen, the main oscillator (OSCIN) can be used for counter 0 as a “known-good” reference clock. The clock for counter 1 can be selected from among 8 options. Refer to the DCC module user guide for more details on the DCC usage. Table 2-14. DCC1 Counter 0 Clock Inputs Clock Source [3–0] Clock / Signal Name All other values oscillator (OSCIN) 5h HF LPO Ah test clock (TCK) Table 2-15.
System and Peripheral Control Registers www.ti.com 2.5 System and Peripheral Control Registers The following sections describe the system and peripheral control registers of the RM57Lx microcontroller. 2.5.1 Primary System Control Registers (SYS) This section describes the SYSTEM registers. These registers are divided into two separate frames. The start address of the primary system module frame is FFFF FF00h. The start address of the secondary system module frame is FFFF E100h.
System and Peripheral Control Registers www.ti.com Table 2-18. Primary System Control Registers (continued) Offset 140 Acronym Register Description BCh SSIR4 System Software Interrupt Request 4 Register Section 2.5.1.38 Section C0h RAMGCR RAM Control Register Section 2.5.1.39 C4h BMMCR1 Bus Matrix Module Control Register 1 Section 2.5.1.40 CCh CPURSTCR CPU Reset Control Register Section 2.5.1.41 D0h CLKCNTL Clock Control Register Section 2.5.1.
System and Peripheral Control Registers www.ti.com 2.5.1.1 SYS Pin Control Register 1 (SYSPC1) The SYSPC1 register, shown in Figure 2-8 and described in Table 2-19, controls the function of the ECLK pin. Figure 2-8. SYS Pin Control Register 1 (SYSPC1) (offset = 00h) 31 16 Reserved R-0 15 1 0 Reserved ECPCLKFUN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-19.
System and Peripheral Control Registers 2.5.1.3 www.ti.com SYS Pin Control Register 3 (SYSPC3) The SYSPC3 register, shown in Figure 2-10 and described in Table 2-21, displays the logic state of the ECLK pin when it is in GIO mode. Figure 2-10. SYS Pin Control Register 3 (SYSPC3) (offset = 08h) 31 16 Reserved R-0 15 1 0 Reserved ECPCLKDIN R-0 R-U LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = Undefined Table 2-21.
System and Peripheral Control Registers www.ti.com 2.5.1.5 SYS Pin Control Register 5 (SYSPC5) The SYSPC5 register, shown in Figure 2-12 and described in Table 2-23, controls the set function of the ECLK pin when it is configured as an output in GIO mode. Figure 2-12. SYS Pin Control Register 5 (SYSPC5) (offset = 10h) 31 16 Reserved R-0 15 1 0 Reserved ECPCLKSET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-23.
System and Peripheral Control Registers 2.5.1.7 www.ti.com SYS Pin Control Register 7 (SYSPC7) The SYSPC7 register, shown in Figure 2-14 and described in Table 2-25, controls the open drain function of the ECLK pin. Figure 2-14. SYS Pin Control Register 7 (SYSPC7) (offset = 18h) 31 16 Reserved R-0 15 1 0 Reserved ECPCLKODE R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-25.
System and Peripheral Control Registers www.ti.com 2.5.1.9 SYS Pin Control Register 9 (SYSPC9) The SYSPC9 register, shown in Figure 2-16 and described in Table 2-27, controls the pull up/pull down configuration of the ECLK pin when it is configured as an input in GIO mode. Figure 2-16. SYS Pin Control Register 9 (SYSPC9) (offset = 20h) 31 16 Reserved R-0 15 1 0 Reserved ECPCLKPS R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-27.
System and Peripheral Control Registers www.ti.com 2.5.1.10 Clock Source Disable Register (CSDIS) The CSDIS register, shown in Figure 2-17 and described in Table 2-28, controls and displays the state of the device clock sources. Figure 2-17.
System and Peripheral Control Registers www.ti.com 2.5.1.11 Clock Source Disable Set Register (CSDISSET) The CSDISSET register, shown in Figure 2-18 and described in Table 2-30, sets clock sources to the disabled state. Figure 2-18.
System and Peripheral Control Registers www.ti.com 2.5.1.12 Clock Source Disable Clear Register (CSDISCLR) The CSDISCLR register, shown in Figure 2-19 and described in Table 2-31, clears clock sources to the enabled state. Figure 2-19.
System and Peripheral Control Registers www.ti.com 2.5.1.13 Clock Domain Disable Register (CDDIS) The CDDIS register, shown in Figure 2-20 and described in Table 2-32, controls the state of the clock domains. NOTE: All the clock domains are enabled on wakeup. The application should guarantee that when HCLK and VCLK_sys are turned off through the HCLKOFF bit, the GCLK domain is also turned off. Figure 2-20.
System and Peripheral Control Registers www.ti.com 2.5.1.14 Clock Domain Disable Set Register (CDDISSET) This CDDISSET register, shown in Figure 2-21 and described in Table 2-33, sets clock domains to the disabled state. Figure 2-21.
System and Peripheral Control Registers www.ti.com Table 2-33. Clock Domain Disable Set Register (CDDISSET) Field Descriptions (continued) Bit 2 Field Value SETVCLKPOFF Description Set VCLK_periph domain. 0 Read: The VCLK_periph domain is enabled. Write: The VCLK_periph domain is unchanged. 1 Read: The VCLK_periph domain is disabled. Write: The VCLK_periph domain is set to the enabled state. 1 SETHCLKOFF Set HCLK and VCLK_sys domains. 0 Read: The HCLK and VCLK_sys domain is enabled.
System and Peripheral Control Registers www.ti.com 2.5.1.15 Clock Domain Disable Clear Register (CDDISCLR) The CDDISCLR register, shown in Figure 2-22 and described in Table 2-34, clears clock domains to the enabled state. Figure 2-22.
System and Peripheral Control Registers www.ti.com Table 2-34. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions (continued) Bit 2 Field Value CLRVCLKPOFF Description Clear VCLK_periph domain. 0 Read: The VCLK_periph domain is enabled. Write: The VCLK_periph domain is unchanged. 1 Read: The VCLK_periph domain is disabled. Write: The VCLK_periph domain is cleared to the enabled state. 1 CLRHCLKOFF Clear HCLK and VCLK_sys domains. 0 Read: The HCLK and VCLK_sys domain is enabled.
System and Peripheral Control Registers www.ti.com 2.5.1.16 GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) The GHVSRC register, shown in Figure 2-23 and described in Table 2-35, controls the clock source configuration for the GCLK, HCLK, VCLK and VCLK2 clock domains. Figure 2-23.
System and Peripheral Control Registers www.ti.com NOTE: Non implemented clock sources should not be enabled or used. A list of the available clock sources is shown in the Table 2-29. 2.5.1.17 Peripheral Asynchronous Clock Source Register (VCLKASRC) The VCLKASRC register, shown in Figure 2-24 and described in Table 2-36, sets the clock source for the asynchronous peripheral clock domains to be configured to run from a specific clock source. Figure 2-24.
System and Peripheral Control Registers www.ti.com 2.5.1.18 RTI Clock Source Register (RCLKSRC) The RCLKSRC register, shown in Figure 2-25 and described in Table 2-37, controls the RTI (Real Time Interrupt) clock source selection. NOTE: Important constraint when the RTI clock source is not VCLK If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI clock needs to be at least three times slower than the VCLK.
System and Peripheral Control Registers www.ti.com 2.5.1.19 Clock Source Valid Status Register (CSVSTAT) The CSVSTAT register, shown in Figure 2-26 and described in Table 2-38, indicates the status of usable clock sources. Figure 2-26.
System and Peripheral Control Registers www.ti.com 2.5.1.20 Memory Self-Test Global Control Register (MSTGCR) The MSTGCR register, shown in Figure 2-27 and described in Table 2-39, controls several aspects of the PBIST (Programmable Built-In Self Test) memory controller. Figure 2-27.
System and Peripheral Control Registers www.ti.com 2.5.1.21 Memory Hardware Initialization Global Control Register (MINITGCR) The MINITGCR register, shown in Figure 2-28 and described in Table 2-40, enables automatic hardware memory initialization. Figure 2-28.
System and Peripheral Control Registers www.ti.com 2.5.1.22 MBIST Controller/ Memory Initialization Enable Register (MSINENA) The MSINENA register, shown in Figure 2-29 and described in Table 2-41, enables PBIST controllers for memory self test and the memory modules initialized during automatic hardware memory initialization. Figure 2-29.
System and Peripheral Control Registers www.ti.com 2.5.1.23 MSTC Global Status Register (MSTCGSTAT) The MSTCGSTAT register, shown in Figure 2-30 and described in Table 2-42, shows the status of the memory hardware initialization and the memory self-test. Figure 2-30.
System and Peripheral Control Registers www.ti.com 2.5.1.24 Memory Hardware Initialization Status Register (MINISTAT) The MINISTAT register, shown in Figure 2-31 and described in Table 2-43, indicates the status of hardware memory initialization. Figure 2-31. Memory Hardware Initialization Status Register (MINISTAT) (offset = 6Ch) 31 16 MIDONE R/WP-0 15 0 MIDONE R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-43.
System and Peripheral Control Registers www.ti.com Table 2-44. PLL Control Register 1 (PLLCTL1) Field Descriptions Bit Field 31 ROS Value Description Reset on PLL Slip 0 Do not reset system when PLL slip is detected 1 Reset when PLL slip is detected Note: BPOS (Bits 30-29) must also be enabled for ROS to be enabled. 30-29 BPOS Bypass of PLL Slip 2h Others Bypass on PLL Slip is disabled. If a PLL Slip is detected no action is taken. Bypass on PLL Slip is enabled.
System and Peripheral Control Registers www.ti.com 2.5.1.26 PLL Control Register 2 (PLLCTL2) The PLLCTL2 register, shown in Figure 2-33 and described in Table 2-45, controls the modulation characteristics and the output divider of the PLL. Figure 2-33.
System and Peripheral Control Registers www.ti.com 2.5.1.27 SYS Pin Control Register 10 (SYSPC10) The SYSPC10 register, shown in Figure 2-34 and described in Table 2-46, controls the function of the ECPCLK slew mode. Figure 2-34. SYS Pin Control Register 10 (SYSPC10) (offset = 78h) 31 16 Reserved R-0 15 1 0 Reserved ECPCLK_SLEW R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-46.
System and Peripheral Control Registers www.ti.com 2.5.1.28 Die Identification Register Lower Word (DIEIDL) The DIEIDL register, shown in Figure 2-35 and described in Table 2-47, contains information about the die lot number, wafer number, and X, Y wafer coordinates. Figure 2-35.
System and Peripheral Control Registers www.ti.com 2.5.1.30 LPO/Clock Monitor Control Register (LPOMONCTL) The LPOMONCTL register, shown in Figure 2-37 and described in Table 2-49, controls the Low Frequency (Clock Source 4) and High Frequency (Clock Source 5) Low Power Oscillator's trim values. Figure 2-37.
System and Peripheral Control Registers www.ti.com Table 2-49. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions (continued) Bit 12-8 Field Value HFTRIM Description High frequency oscillator trim value. This four-bit value is used to center the HF oscillator's frequency. Caution: This value should only be changed when the HF oscillator is not the source for a clock domain, otherwise a system failure could result. The values below are the ratio: f / fo in the F021 process.
System and Peripheral Control Registers www.ti.com Table 2-49. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions (continued) Bit Field 4-0 LFTRIM Value Description Low frequency oscillator trim value. This four-bit value is used to center the LF oscillator's frequency. Caution: This value should only be changed when the LF oscillator is not the source for a clock domain, otherwise a system failure could result. The values below are the ratio: f / fo in the F021 process. 0 20.
System and Peripheral Control Registers www.ti.com 2.5.1.31 Clock Test Register (CLKTEST) The CLKTEST register, shown in Figure 2-38 and described in Table 2-50, controls the clock signal that is supplied to the ECLK pin for test and debug purposes. NOTE: Clock Test Register Usage This register should only be used for test and debug purposes. Figure 2-38.
System and Peripheral Control Registers www.ti.com Table 2-50.
System and Peripheral Control Registers www.ti.com 2.5.1.32 DFT Control Register (DFTCTRLREG) This register is shown in Figure 2-39 and described in Table 2-51. Figure 2-39. DFT Control Register (DFTCTRLREG) (offset = 90h) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 4 3 0 Reserved DFTWRITE Reserved DFTREAD Reserved TEST_MODE_KEY R-0 R/WP-1h R-0 R/WP-1h R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-51.
System and Peripheral Control Registers www.ti.com 2.5.1.33 DFT Control Register 2 (DFTCTRLREG2) This register is shown in Figure 2-40 and described in Table 2-52. For information on filtering the RFSLIP see Section 2.5.2.7. Figure 2-40. DFT Control Register 2 (DFTCTRLREG2) (offset = 94h) 31 16 IMPDF(27:12) R/WP-0 15 4 3 0 IMPDF(11:0) TEST_MODE_KEY R/WP-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-52.
System and Peripheral Control Registers www.ti.com 2.5.1.34 General Purpose Register (GPREG1) This register is shown in Figure 2-41 and described in Table 2-53. For information on filtering the RFSLIP, see Section 2.5.2.7. Figure 2-41.
System and Peripheral Control Registers www.ti.com 2.5.1.35 System Software Interrupt Request 1 Register (SSIR1) The SSIR1 register, shown in Figure 2-42 and described in Table 2-54, is used for software interrupt generation. Figure 2-42. System Software Interrupt Request 1 Register (SSIR1) (offset = B0h) 31 16 Reserved R-0 15 8 7 0 SSKEY1 SSDATA1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-54.
System and Peripheral Control Registers www.ti.com 2.5.1.36 System Software Interrupt Request 2 Register (SSIR2) The SSIR2 register, shown in Figure 2-43 and described in Table 2-55, is used for software interrupt generation. Figure 2-43. System Software Interrupt Request 2 Register (SSIR2) (offset = B4h) 31 16 Reserved R-0 15 8 7 0 SSKEY2 SSDATA2 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-55.
System and Peripheral Control Registers www.ti.com 2.5.1.37 System Software Interrupt Request 3 Register (SSIR3) The SSIR3 register, shown in Figure 2-44 and described in Table 2-56, is used for software interrupt generation. Figure 2-44. System Software Interrupt Request 3 Register (SSIR3) (offset = B8h) 31 16 Reserved R-0 15 8 7 0 SSKEY3 SSDATA3 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-56.
System and Peripheral Control Registers www.ti.com 2.5.1.38 System Software Interrupt Request 4 Register (SSIR4) The SSIR4 register, shown in Figure 2-45 and described in Table 2-57, is used for software interrupt generation. Figure 2-45. System Software Interrupt Request 4 Register (SSIR4) (offset = BCh) 31 16 Reserved R-0 15 8 7 0 SSKEY4 SSDATA4 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-57.
System and Peripheral Control Registers www.ti.com 2.5.1.39 RAM Control Register (RAMGCR) NOTE: The RAM_DFT_EN bits are for TI internal use only. The contents of the RAM_DFT_EN field should not be changed. Figure 2-46.
System and Peripheral Control Registers www.ti.com 2.5.1.40 Bus Matrix Module Control Register 1 (BMMCR1) The BMMCR1 register, shown in Figure 2-47 and described in Table 2-59, allows RAM and Program (Flash) memory addresses to be swapped. Figure 2-47. Bus Matrix Module Control Register 1 (BMMCR) (offset = C4h) 31 16 Reserved R-0 15 4 3 0 Reserved MEMSW R-0 R/WP-Ah LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-59.
System and Peripheral Control Registers www.ti.com 2.5.1.42 Clock Control Register (CLKCNTL) The CLKCNTL register, shown in Figure 2-49 and described in Table 2-61, controls peripheral reset and the peripheral clock divide ratios. NOTE: VCLK and VCLK2 clock ratio restrictions. VCLK2 must always be greater than or equal to VCLK. In addition, the VCLK and VCLK2 clock ratios must not be changed simultaneously.
System and Peripheral Control Registers www.ti.com 2.5.1.43 ECP Control Register (ECPCNTL) The ECP register, shown in Figure 2-50 and described in Table 2-62, configures the ECLK pin in functional mode. NOTE: ECLK Functional mode configuration. The ECLK pin must be placed into Functional mode by setting the ECPCLKFUN bit to 1 in the SYSPC1 register before a clock source will be visible on the ECLK pin. Figure 2-50.
System and Peripheral Control Registers www.ti.com 2.5.1.44 DEV Parity Control Register 1 (DEVCR1) This register is shown in Figure 2-51 and described in Table 2-63. Figure 2-51. DEV Parity Control Register 1 (DEVCR1) (offset = DCh) 31 16 Reserved R-0 15 4 3 0 Reserved DEVPARSEL R-0 R/WP-Ah LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-63.
System and Peripheral Control Registers www.ti.com 2.5.1.46 System Exception Status Register (SYSESR) The SYSESR register, shown in Figure 2-53 and described in Table 2-65, shows the source for different resets encountered. Previous reset source status bits are not automatically cleared if new resets occur. After reading this register, the software should clear any flags that are set so that the source of future resets can be determined. Any bit in this register can be cleared by writing a '1' to the bit.
System and Peripheral Control Registers www.ti.com Table 2-65. System Exception Status Register (SYSESR) Field Descriptions (continued) Bit 5 Field Value CPURST Description CPU reset flag. This bit is set when the CPU is reset. Write 1 will clear this bit. Write 0 has no effect. Note: A CPU reset can be initiated by the CPU self-test controller (LBIST) or by toggling the CPU RESET bit field in CPURSTCR register. 4 0 No CPU reset has occurred. 1 A CPU reset occurred. SWRST Software reset flag.
System and Peripheral Control Registers www.ti.com 2.5.1.47 System Test Abort Status Register (SYSTASR) This register is shown in Figure 2-54 and described in Table 2-66. Figure 2-54. System Test Abort Status Register (SYSTASR) (offset = E8h) 31 16 Reserved R-0 15 5 4 0 Reserved EFUSE_Abort R-0 R/WPC-X/0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; C = Clear; -X = Value unchanged after reset; -n = value after reset Table 2-66.
System and Peripheral Control Registers www.ti.com 2.5.1.48 Global Status Register (GLBSTAT) The GLBSTAT register, shown in Figure 2-55 and described in Table 2-67, indicates the FMzPLL (PLL1) slip status and the oscillator fail status. NOTE: PLL and OSC fail behavior The device behavior after a PLL slip or an oscillator failure is configured in the PLLCTL1 register. Figure 2-55.
System and Peripheral Control Registers www.ti.com 2.5.1.49 Device Identification Register (DEVID) The DEVID is a read-only register. It contains device-specific information that is hard-coded during device manufacture. For the initial silicon version, the device identification code value is 8044 AD05h. This register is shown in Figure 2-56 and described in Table 2-68. Figure 2-56.
System and Peripheral Control Registers www.ti.com 2.5.1.50 Software Interrupt Vector Register (SSIVEC) The SSIVEC register, shown in Figure 2-57 and described in Table 2-69, contains information about software interrupts. Figure 2-57. Software Interrupt Vector Register (SSIVEC) (offset = F4h) 31 16 Reserved R-0 15 8 7 0 SSIDATA SSIVECT R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-69.
System and Peripheral Control Registers www.ti.com 2.5.1.51 System Software Interrupt Flag Register (SSIF) The SSIF register, shown in Figure 2-58 and described in Table 2-70, contains software interrupt flag status information. Figure 2-58.
System and Peripheral Control Registers www.ti.com 2.5.2 Secondary System Control Registers (SYS2) This section describes the secondary frame of system registers. The start address of the secondary system module frame is FFFF E100h. The registers support 8-, 16-, and 32-bit writes. The offset is relative to the system module frame start address. Table 2-71 contains a list of the secondary system control registers. NOTE: All additional registers in the secondary system frame are reserved. Table 2-71.
System and Peripheral Control Registers 2.5.2.1 www.ti.com PLL Control Register 3 (PLLCTL3) The PLLCTL3 register is shown in Figure 2-59 and described in Table 2-72; controls the settings of PLL2 (Clock Source 6 - FPLL). Figure 2-59.
System and Peripheral Control Registers www.ti.com 2.5.2.2 CPU Logic Bist Clock Divider (STCLKDIV) This register is shown in Figure 2-60 and described in Table 2-73. Figure 2-60. CPU Logic BIST Clock Prescaler (STCLKDIV) (offset = 08h) 31 27 26 24 23 16 Reserved CLKDIV Reserved R-0 R/WP-0 R-0 15 0 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-73.
System and Peripheral Control Registers 2.5.2.3 www.ti.com ECP Control Register 1 (ECPCNTL1) The ECP register, shown in Figure 2-61 and described in Table 2-74, configures the ECLK2 pin in functional mode. NOTE: ECLK2 Functional mode configuration. The ECLK2 pin must be placed into Functional mode by setting the ECPCLKFUN bit to 1 in the SYSPC1 register before a clock source will be visible on the ECLK pin. Figure 2-61.
System and Peripheral Control Registers www.ti.com 2.5.2.4 Clock 2 Control Register (CLK2CNTRL) This register is shown in Figure 2-62 and described in Table 2-75. Figure 2-62. Clock 2 Control Register (CLK2CNTRL) (offset = 3Ch) 31 16 Reserved R-0 15 12 11 8 7 4 3 0 Reserved Reserved Reserved VCLK3R R-0 R/WP-1h R-0 R/WP-1h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-75.
System and Peripheral Control Registers 2.5.2.5 www.ti.com Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) This register is shown in Figure 2-63 and described in Table 2-76. Figure 2-63.
System and Peripheral Control Registers www.ti.com Table 2-76. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) Field Descriptions (continued) Bit 10-8 Field Value VCLKA3R Description Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. VCLKA3 domain will be enabled by writing to the CDDIS register and VCLKA3_DIV_CDDIS bit It can inferred that VCLKA3_DIV clock is disabled when VCLKA3_S clock is disabled. 7-5 4 Reserved 0 The ratio is VCLKA3 divided by 1.
System and Peripheral Control Registers 2.5.2.6 www.ti.com HCLK Control Register (HCLKCNTL) This register is shown in Figure 2-64 and described in Table 2-77. Figure 2-64. HCLK Control Register (HCLKCNTL) (offset = 54h) 31 16 Reserved R-0 15 2 1 0 Reserved HCLKR R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-77.
System and Peripheral Control Registers www.ti.com 2.5.2.7 Clock Slip Control Register (CLKSLIP) This register is shown in Figure 2-65 and described in Table 2-78. For information on filtering the FBSLIP, see Section 2.5.1.34. Figure 2-65.
System and Peripheral Control Registers 2.5.2.8 www.ti.com IP ECC Error Enable Register (IP1ECCERREN) This register is shown in Figure 2-66 and described in Table 2-79. Figure 2-66.
System and Peripheral Control Registers www.ti.com 2.5.2.9 EFUSE Controller Control Register (EFC_CTLREG) This register is shown in Figure 2-67 and described in Table 2-80. Figure 2-67. EFUSE Controller Control Register (EFC_CTLREG) (offset = ECh) 31 16 Reserved R-0 15 4 3 0 Reserved EFC_INSTR_WEN R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-80.
System and Peripheral Control Registers www.ti.com 2.5.2.11 Die Identification Register Upper Word (DIEIDH_REG1) This register is shown in Figure 2-69 and described in Table 2-82. Figure 2-69. Die Identification Register, Upper Word (DIEIDH_REG1) [offset = F4h] 31 0 DIEIDH R-X LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -X = Value unchanged after reset Table 2-82.
System and Peripheral Control Registers www.ti.com 2.5.3 Peripheral Central Resource (PCR) Control Registers This section describes the Peripheral Central Resource (PCR) control registers. The are three PCRx in this microcontroller. The start address of the PCR1 register frame is FFFF 1000h. The start address of the PCR2 register frame is FCFF 1000h. The start address of the PCR3 register frame is FFF7 8000h.
System and Peripheral Control Registers www.ti.com Table 2-85. Peripheral Central Resource Control Registers (continued) Offset Acronym Register Description 30Ch PS1MSTID_H Peripheral Frame 1 Master-ID Protection Register_H Section 2.5.3.32 Section 310h PS2MSTID_L Peripheral Frame 2 Master-ID Protection Register_L Section 2.5.3.32 314h PS2MSTID_H Peripheral Frame 2 Master-ID Protection Register_H Section 2.5.3.
System and Peripheral Control Registers www.ti.com Table 2-85. Peripheral Central Resource Control Registers (continued) Offset Acronym Register Description 3C8h PS25MSTID_L Peripheral Frame 25 Master-ID Protection Register_L Section 2.5.3.32 Section 3CCh PS25MSTID_H Peripheral Frame 25 Master-ID Protection Register_H Section 2.5.3.32 3D0h PS26MSTID_L Peripheral Frame 26 Master-ID Protection Register_L Section 2.5.3.
System and Peripheral Control Registers www.ti.com Table 2-85. Peripheral Central Resource Control Registers (continued) Offset Acronym Register Description 468h PPSE5MSTID_L Privilege Peripheral Extended Frame 5 Master-ID Protection Register_L Section 2.5.3.38 46Ch PPSE5MSTID_H Privilege Peripheral Extended Frame 5 Master-ID Protection Register_H Section 2.5.3.38 470h PPSE6MSTID_L Privilege Peripheral Extended Frame 6 Master-ID Protection Register_L Section 2.5.3.
System and Peripheral Control Registers www.ti.com Table 2-85. Peripheral Central Resource Control Registers (continued) Offset Acronym Register Description 4D8h PPSE19MSTID_L Privilege Peripheral Extended Frame 19 Master-ID Protection Register_L Section 2.5.3.38 Section 4DCh PPSE19MSTID_H Privilege Peripheral Extended Frame 19 Master-ID Protection Register_H Section 2.5.3.38 4E0h PPSE20MSTID_L Privilege Peripheral Extended Frame 20 Master-ID Protection Register_L Section 2.5.3.
System and Peripheral Control Registers www.ti.com Table 2-85. Peripheral Central Resource Control Registers (continued) Offset 208 Acronym Register Description 550h PCS4MSTID Peripheral Memory Frame Master-ID Protection Register4 Section 2.5.3.39 Section 554h PCS5MSTID Peripheral Memory Frame Master-ID Protection Register5 Section 2.5.3.39 558h PCS6MSTID Peripheral Memory Frame Master-ID Protection Register6 Section 2.5.3.
System and Peripheral Control Registers www.ti.com 2.5.3.1 Peripheral Memory Protection Set Register 0 (PMPROTSET0) This register is shown in Figure 2-72 and described in Table 2-86. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to non-implemented bits have no effect and reads are 0. Figure 2-72.
System and Peripheral Control Registers 2.5.3.3 www.ti.com Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) This register is shown in Figure 2-74 and described in Table 2-88. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-74.
System and Peripheral Control Registers www.ti.com 2.5.3.5 Peripheral Protection Set Register 0 (PPROTSET0) There is one bit for each quadrant for PS0 to PS7. The following are the ways in which quadrants are used within a PS frame: (a) The slave uses all the four quadrants. Only the bit corresponding to the quadrant 0 of PSn is implemented. It protects the whole 1K-byte frame. The remaining three bits are not implemented. (b) The slave uses two quadrants.
System and Peripheral Control Registers 2.5.3.6 www.ti.com Peripheral Protection Set Register 1 (PPROTSET1) There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in Section 2.5.3.5. This register is shown in Figure 2-77 and described in Table 2-91. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-77.
System and Peripheral Control Registers www.ti.com 2.5.3.8 Peripheral Protection Set Register 3 (PPROTSET3) There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in Section 2.5.3.5. This register is shown in Figure 2-79 and described in Table 2-93. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-79.
System and Peripheral Control Registers www.ti.com 2.5.3.10 Peripheral Protection Clear Register 1 (PPROTCLR1) There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in Section 2.5.3.5. This register is shown in Figure 2-81 and described in Table 2-95. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-81.
System and Peripheral Control Registers www.ti.com 2.5.3.12 Peripheral Protection Clear Register 3 (PPROTCLR3) There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in Section 2.5.3.5. This register is shown in Figure 2-83 and described in Table 2-97. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-83.
System and Peripheral Control Registers www.ti.com 2.5.3.14 Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) This register is shown in Figure 2-85 and described in Table 2-99. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-85.
System and Peripheral Control Registers www.ti.com 2.5.3.16 Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1) This register is shown in Figure 2-87 and described in Table 2-101. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-87.
System and Peripheral Control Registers www.ti.com 2.5.3.17 Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) There is one bit for each quadrant for PS0 to PS7. Each bit of this register corresponds to the bit at the same index in the corresponding PPROT register in that they relate to the same peripheral. These bits are used to power down/power up the clock to the corresponding peripheral.
System and Peripheral Control Registers www.ti.com 2.5.3.18 Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in Section 2.5.3.17. This register is shown in Figure 2-89 and described in Table 2-103. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-89.
System and Peripheral Control Registers www.ti.com 2.5.3.20 Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in Section 2.5.3.17. This register is shown in Figure 2-91 and described in Table 2-105. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-91.
System and Peripheral Control Registers www.ti.com 2.5.3.22 Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in Section 2.5.3.17. This register is shown in Figure 2-93 and described in Table 2-107. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-93.
System and Peripheral Control Registers www.ti.com 2.5.3.24 Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3) There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in Section 2.5.3.17. This register is shown in Figure 2-95 and described in Table 2-109. NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes to unimplemented bits have no effect and reads are 0. Figure 2-95.
System and Peripheral Control Registers www.ti.com 2.5.3.26 Debug Frame Powerdown Clear Register (PDPWRDWNCLR) Figure 2-97. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) (offset = C4h) 31 1 0 Reserved PDWRDWNCLR R-0 R/WP-1 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-111. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) Field Descriptions Bit 31-1 0 Field Value Reserved 0 PDWRDWNCLR Description Read returns 0.
System and Peripheral Control Registers www.ti.com 2.5.3.28 MasterID Enable Register (MSTIDENA) Figure 2-99. MasterID Enable Register (MSTIDENA) (offset = 204h) 31 16 Reserved R-0 15 4 3 0 Reserved MSTID_CHK_ENA R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-113. MasterID Enable Register (MSTIDENA) Field Descriptions Bit Field 31-4 Reserved 3-0 MSTID_CHK_ENA Value 0 Description Read returns 0. Writes have no effect.
System and Peripheral Control Registers www.ti.com 2.5.3.29 MasterID Diagnostic Control Register (MSTIDDIAGCTRL) Figure 2-100. MasterID Diagnostic Control Register (MSTIDDIAGCTRL) (offset = 208h) 31 16 Reserved R-0 15 12 11 8 7 4 3 0 Reserved DIAG_CMP_VALUE Reserved DIAG_MODE_ENA R-0 R/WP-0 R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-114.
System and Peripheral Control Registers www.ti.com 2.5.3.30 Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L) Figure 2-101. Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L) (offset = 300h) 31 16 PS0_QUAD1_MSTID R/WP-FFFFh 15 0 PS0_QUAD0_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-115.
System and Peripheral Control Registers www.ti.com 2.5.3.31 Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H) Figure 2-102. Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H) (offset = 304h) 31 16 PS0_QUAD3_MSTID R/WP-FFFFh 15 0 PS0_QUAD2_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-116.
System and Peripheral Control Registers www.ti.com 2.5.3.32 Peripheral Frame n MasterID Protection Register_L/H (PS[1-31]MSTID_L/H) Figure 2-103. Peripheral Frame n MasterID Protection Register_L/H (PSnMSTID_L/H) (offset = 308h-3FCh) 31 16 PSn_QUAD3_MSTID or PSn_QUAD1_MSTID R/WP-FFFFh 15 0 PSn_QUAD2_MSTID or PSn_QUAD0_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-117.
System and Peripheral Control Registers www.ti.com 2.5.3.33 Privileged Peripheral Frame 0 MasterID Protection Register_L (PPS0MSTID_L) Figure 2-104. Privileged Peripheral Frame 0 MasterID Protection Register_L (PPS0MSTID_L) (offset = 400h) 31 16 PPS0_QUAD1_MSTID R/WP-FFFFh 15 0 PPS0_QUAD0_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-118.
System and Peripheral Control Registers www.ti.com 2.5.3.34 Privileged Peripheral Frame 0 MasterID Protection Register_H (PPS0MSTID_H) Figure 2-105. Privileged Peripheral Frame 0 MasterID Protection Register_H (PPS0MSTID_H) (offset = 404h) 31 16 PPS0_QUAD3_MSTID R/WP-FFFFh 15 0 PPS0_QUAD2_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-119.
System and Peripheral Control Registers www.ti.com 2.5.3.35 Privileged Peripheral Frame n MasterID Protection Register_L/H (PPS[1-7]MSTID_L/H) Figure 2-106. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H) (offset = 408h-43Ch) 31 16 PPSn_QUAD3_MSTID or PPSn_QUAD1_MSTID R/WP-FFFFh 15 0 PPSn_QUAD2_MSTID or PPSn_QUAD0_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-120.
System and Peripheral Control Registers www.ti.com 2.5.3.36 Privileged Peripheral Extended Frame 0 MasterID Protection Register_L (PPSE0MSTID_L) Figure 2-107. Privileged Peripheral Extended Frame 0 MasterID Protection Register_L (PPSE0MSTID_L) (offset = 440h) 31 16 PPSE0_QUAD1_MSTID R/WP-FFFFh 15 0 PPSE0_QUAD0_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-121.
System and Peripheral Control Registers www.ti.com 2.5.3.37 Privileged Peripheral Extended Frame 0 MasterID Protection Register_H (PPSE0MSTID_H) Figure 2-108. Privileged Peripheral Extended Frame 0 MasterID Protection Register_H (PPSE0MSTID_H) (offset = 444h) 31 16 PPSE0_QUAD3_MSTID R/WP-FFFFh 15 0 PPSE0_QUAD2_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-122.
System and Peripheral Control Registers www.ti.com 2.5.3.38 Privileged Peripheral Extended Frame n MasterID Protection Register_L/H (PPSE[131]MSTID_L/H) Figure 2-109. Privileged Peripheral Extended Frame n MasterID Protection Register_L/H (PPSEnMSTID_L/H) (offset = 448h-53Ch) 31 16 PPSEn_QUAD3_MSTID or PPSEn_QUAD1_MSTID R/WP-FFFFh 15 0 PPSEn_QUAD2_MSTID or PPSEn_QUAD0_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-123.
System and Peripheral Control Registers www.ti.com 2.5.3.39 Peripheral Memory Frame MasterID Protection Register (PCS[0-31]MSTID) Figure 2-110. Peripheral Memory Frame MasterID Protection Register (PCSnMSTID) (offset = 540h-5BCh) 31 16 PCS(2n+1)_MSTID R/WP-FFFFh 15 0 PCS(2n)_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-124.
System and Peripheral Control Registers www.ti.com 2.5.3.40 Privileged Peripheral Memory Frame MasterID Protection Register (PPCS[0-7]MSTID) Figure 2-111. Privileged Peripheral Memory Frame MasterID Protection Register (PPCSnMSTID) (offset = 5C0h-5DCh) 31 16 PPCS(2n+1)_MSTID R/WP-FFFFh 15 0 PPCS(2n)_MSTID R/WP-FFFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 2-125.
Chapter 3 SPNU562 – May 2014 SCR Control Module (SCM) This chapter describes the SCR control module (SCM). SCR is the CPU Interconnect Subsystem. Topic ........................................................................................................................... 3.1 3.2 3.3 3.4 Overview ......................................................................................................... Module Operation ....................................................................................
Overview 3.1 www.ti.com Overview The SCR (Switch Central Resource) Control Module (SCM) provides a means to control and monitor the main interconnect. Interconnect hardware checker performs four major functional checks on interconnect: • Arbitration • Timeout • Protocol conversion • Parity on control / address signals Any of these errors will force the interconnect to trigger an error event to ESM group 1 (see ESM group1 mapping).
Overview www.ti.com 3.1.2 System Block Diagram Figure 3-1 shows the system level block diagram of SCM and interconnect (SCR). SCM compares the transaction command request to transaction command accept (req2accept) counters and transaction command request to transaction command response (req2resp) counters of each initiator agent (IA) to the corresponding threshold values (programmable).
Module Operation 3.2 www.ti.com Module Operation 3.2.1 Block Diagram Figure 3-2 shows the block diagram of SCM. Figure 3-2. SCM Block Diagram OCP MMR interface active_ia_o(n-1:0) MMR Registers active_ta_o(m-1:0) Keys/Control signals Req2accept from each IA Threshold Compare Block Req2resp from each IA err_event To_clear Dtc_soft_reset(3:0) CLKSTOPPEDm_0/1 ACPIDLE SCM Control Block Global_error_clr Hwchkr_sdc_soft_reset Parity_diagnostic_enable 3.2.
Module Operation www.ti.com Figure 3-3. Timeout Threshold Compare REQ2ACCPT_MAX REQ2RESP_MAX >= >= IA(n) REQ2ACCEPT IA(n) REQ2RESP error error Error_event SCMIAERR0STAT(n) 3.2.2.1 SCMIAERR1STAT(n) Other compare error Interconnect Timeout Clearing Control Key When the threshold compare block triggers a time out error, the ESM will be notified and can interrupt the main CPU. The interconnect hardware checker real-time counter needs to be reset to 0 in order to restart properly. Section 3.
How to Use SCM 3.2.3.1 www.ti.com Control Key to invert Parity Polarity for Interconnect Hardware Checker Parity Detection Diagnostic The interconnect receives parity bits associated with input control and address signals and does the parity checking. The interconnect also generates parity bits for corresponding control and address signals. To test the parity checking logic, the SCM can invert the parity polarity bit to the interconnect to purposely creates a fail or pass parity checking condition.
How to Use SCM www.ti.com 3.3.2 How to Initiate Self-test Sequence It is necessary to be able to do self-test of the interconnect hardware checker logic to detect residual faults when you decide at appropriate time in the application control loop. The self-test logic will create normal and erroneous transaction from each master to each slave according to the bus connection matrix to verify that the hardware checker and the interconnect functioning properly.
How to Use SCM www.ti.com 3.3.3 How to Configure Timeout Check The threshold compare block takes the real time counters (command request to command accepted and command request to command response) from each IA of the interconnect hardware checker module and compare against the corresponding threshold value in SCM every cycle. If any IA comparison fails, the SCM module will update the corresponding status bit in SCMIAERR0STAT and SCMIAERR1STAT registers.
SCM Registers www.ti.com 3.4 SCM Registers The SCM registers are listed in Table 3-1 . Each register begins on a word boundary. The registers support 8-, 16-, and 32-bit accesses. The address offset is specified from the base address of FFFF 0A00h. Registers are accessed through a dedicated MMR interface. Support only read, write, and write nonposted. Read and write are always returning response status. A write to reserved bits has no effect.
SCM Registers www.ti.com 3.4.2 SCM Control Register (SCMCNTRL) Figure 3-6. SCM Control Register (SCMCNTRL) (offset = 04h) 31 28 27 24 23 20 19 16 Reserved PAR DIAG EN Reserved GLOBAL_ERROR_CLR R-0 R/WP-5h R-0 R/WP-5h 15 12 11 8 7 4 3 0 Reserved DTC_SOFT_RESET Reserved TO_CLEAR R-0 R/WP-5h R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after synchronous reset on system reset Table 3-3.
SCM Registers www.ti.com 3.4.3 SCM Compare Threshold Counter Register (SCMTHRESHOLD) Figure 3-7. SCM Compare Threshold Counter Register (SCMTHRESHOLD) (offset = 08h) 31 16 REQ2RESPONSE_MAX R/WP-400h 15 0 REQ2ACCEPT_MAX R/WP-400h LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after synchronous reset on system reset Table 3-4.
SCM Registers www.ti.com 3.4.4 SCM Initiator Error0 Status Register (SCMIAERR0STAT) Figure 3-8. SCM Initiator Error0 Status Register (SCMIAERR0STAT) (offset = 10h) 31 8 Reserved R-0 7 6 5 4 3 2 1 0 R2A7 R2A6 R2A5 R2A4 R2A3 R2A2 R2A1 R2A0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after synchronous reset by power-on reset Table 3-5.
SCM Registers www.ti.com 3.4.6 SCM Initiator Active Status Register (SCMIASTAT) Figure 3-10. SCM Initiator Active Status Register (SCMIASTAT) (offset = 18h) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 Reserved IAST13 IAST12 IAST11 IAST10 IAST9 IAST8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7 6 5 4 3 2 1 0 IAST7 IAST6 IAST5 IAST4 IAST3 IAST2 IAST1 IAST0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after synchronous reset by system reset Table 3-7.
Chapter 4 SPNU562 – May 2014 Interconnect This chapter describes the two interconnects in the microcontroller. 250 Topic ........................................................................................................................... 4.1 4.2 4.3 4.4 Overview ......................................................................................................... Peripheral Interconnect Subsystem ....................................................................
Overview www.ti.com 4.1 Overview The interconnect is a bus matrix which interconnects the CPU cores, System DMA, other bus masters and device specific slaves within the microcontroller. There are two interconnects in the microcontroller: the CPU Interconnect Subsystem and the Peripheral Interconnect Subsystem. The interconnects direct the access requests by the masters by providing decoding, arbitration, and routing of the requests to the various slaves. 4.1.
Peripheral Interconnect Subsystem www.ti.com 4.2.1 Accessing PCRx and CRCx Slave System peripherals can be accessed via the PCR1 slave port. User peripherals can be accessed via either the PCR2 or PCR3 slave ports. Refer to the datasheet for information on what peripherals are available through each PCR. Peripheral Central Resource (PCR) is responsible to further decode the slave address to select the desired peripheral. There are two CRC modules implemented in the device.
CPU Interconnect Subsystem www.ti.com 4.3 CPU Interconnect Subsystem The masters and slaves are connected to the CPU Interconnect Subsystem. CPU Interconnect Subsystem is not a full cross-bar. Not all masters can access to all slaves. Table 4-3 lists the implemented point to point connections between the masters and slaves.
CPU Interconnect Subsystem 4.3.1.4 www.ti.com Access the Cache Memories Both the instruction and data caches of theCPU are memory mapped in the device and can be accessed via the AXI-S slave port. Only the CPU core has point to point connection to the AXI-S slave port. 4.3.2 ECC Generation and Evaluation CPU core contains the built-in ECC generation and evaluation logic for its AXI interface. Therefore, CPU will generate the ECC checksum along with its write data.
CPU Interconnect Subsystem www.ti.com 4.3.4 Interconnect Self-test CPU Interconnect Subsystem can be put into self-test. When in self-test, the self-test logic will apply test stimulus to each master and slave interface. If an error is detected, the type of error for the corresponding interface is logged. An error is asserted to ESM Group 3 if the self-test does not complete successfully.
CPU Interconnect Subsystem www.ti.com 4.3.6 Interconnect Runtime Status Both the CPU Interconnect Subsystem and the Peripheral Interconnect Subsystem will output its status on each master and slave interface to the SCM indicating if the interface is currently active. The status are captured in the SCMIASTAT register for the master interfaces and SCMTASTAT for the slave interfaces. See Table 4-4 for the mapping between each interface to each bit field. Table 4-4.
SDC MMR Registers www.ti.com 4.4 SDC MMR Registers Table 4-5 lists the Safety Diagnostic Checker registers. The registers support only 32-bit reads. The offset is relative to the base address. The base address for the registers is FA00 0000h. Table 4-5. SDC MMR Registers Offset Acronym Register Description Section 0h SDC_STATUS SDC Status Register Section 4.4.1 4h SDC_CONTROL SDC Control Register Section 4.4.2 8h ERR_GENERIC_PARITY Error Generic Parity Register Section 4.4.
SDC MMR Registers www.ti.com 4.4.1 SDC Status Register (SDC_STATUS) Figure 4-2. SDC Status Register (SDC_STATUS) (offset = 00h) 31 16 Reserved R-0 15 5 R-0 4 3 2 1 0 GLOBAL_ERROR NT_OK NT_RUN PT_OK PT_RUN R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 4-6. SDC Status Register (SDC_STATUS) Field Descriptions Bit 31-5 4 3 2 1 0 258 Field Reserved Value 0 GLOBAL_ERROR Description Reads return 0 and writes have no effect.
SDC MMR Registers www.ti.com 4.4.2 SDC Control Register (SDC_CONTROL) Figure 4-3. SDC Control Register (SDC_STATUS) (offset = 04h) 31 16 Reserved R-0 15 1 0 Reserved MASK_SOFT_RESET R-0 RW-0 LEGEND: R = Read only; -n = value after reset Table 4-7. SDC Control Register (SDC_CONTROL) Field Descriptions Bit 31-1 0 Field Value Reserved 0 MASK_SOFT_RESET Description Reads return 0 and writes have no effect.
SDC MMR Registers www.ti.com 4.4.4 Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) Figure 4-5. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) (offset = 0Ch) 31 16 Reserved R-0 15 6 5 0 Reserved ERR_UNEXPECTED_TRANS R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 4-9.
SDC MMR Registers www.ti.com 4.4.6 Error Transaction Signature Register (ERR_TRANS_SIGNATURE) Figure 4-7. Error Transaction Signature Register (ERR_TRANS_SIGNATURE) (offset = 14h) 31 16 Reserved R-0 15 6 5 0 Reserved ERR_TRANS_SIGNATURE R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 4-11.
SDC MMR Registers www.ti.com 4.4.8 Error User Parity Register (ERR_USER_PARITY) Figure 4-9. Error User Parity Register (ERR_USER_PARITY) (offset = 1Ch) 31 16 Reserved R-0 15 6 5 0 Reserved ERR_USER_PARITY R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 4-13. Error User Parity Register (ERR_USER_PARITY) Field Descriptions Bit Field Value 31-6 Reserved 5-0 ERR_USER_PARITY 0 Description Reads return 0 and writes have no effect. Error related to mismatch on the parity.
SDC MMR Registers www.ti.com 4.4.10 Slave Error Address Decode Register (SERR_ADDR_DECODE) Figure 4-11. Slave Error Address Decode Register (SERR_ADDR_DECODE) (offset = 24h) 31 16 Reserved R-0 15 7 6 0 Reserved SERR_ADDR_DECODE R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 4-15. Slave Error Address Decode Register (SERR_ADDR_DECODED) Field Descriptions Bit Field Value 31-7 Reserved 0 6-0 SERR_ADDR_ DECODE Description Reads return 0 and writes have no effect.
Chapter 5 SPNU562 – May 2014 Power Management Module (PMM) This chapter describes the power management module (PMM). 264 Topic ........................................................................................................................... 5.1 5.2 5.3 5.4 Overview ......................................................................................................... Power Domains ................................................................................................
Overview www.ti.com 5.1 Overview The microcontroller is part of the family of microcontrollers from Texas Instruments for safety-critical applications. Several functions are implemented on this microcontroller targeted towards varied applications. The core logic is divided into several domains that can be independently turned on or off based on the application’s requirements. Turning off a domain has the effect to only turn off the clocks into the domain. Dynamic current is virtually reduced to zero.
Overview www.ti.com Figure 5-1.
Power Domains www.ti.com 5.2 Power Domains Figure 5-2 shows the core domains implemented on the microcontroller. This device has 5 separate core power domains: • PD1 is an always-ON domain and is not controlled by PMM. It contains the CPU as well as other principal modules and the interconnect required for operation of the microcontroller. This domain also includes the level 1 cache memory and the level 2 flash memory and SRAM.
PMM Operation 5.3 www.ti.com PMM Operation It is important to understand some fundamental concepts beforehand. 5.3.1 Power Domain State Each core power domain can be in one of three states: Active, Idle, or Off. In the Active state, a power domain is fully powered with normal supply voltage. In the Idle state, all clocks to a power domain are turned off (driven low). The supply voltage is still maintained at the normal level.
PMM Operation www.ti.com 5.3.4.2 Turning a Power Domain On A power domain can be turned on by writing the correct key to the LOGICPDON register. PMM will automatically restart the clocks to the power domain once the Active power state is restored if the “automatic clock enable upon wake up” option is selected. If this option is not selected, the application can turn on clocks to the power domain by clearing the PDCLK_DIS register manually.
PMM Registers www.ti.com Compare mismatch test: A vector with all 1's is applied to the PSCON diagnostic compare block’s primary input port and the same input is also applied to the secondary input port but with one bit flipped starting from bit position 0. The unequal vectors should cause the PSCON diagnostic compare block to generate a compare mismatch at bit position 0. In case a mismatch is not detected, a self-test error is indicated.
PMM Registers www.ti.com 5.4.1 Logic Power Domain Control Register (LOGICPDPWRCTRL0) The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-3.
PMM Registers www.ti.com 5.4.2 Logic Power Domain Control Register (LOGICPDPWRCTRL1) The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-4.
PMM Registers www.ti.com 5.4.3 Power Domain Clock Disable Register (PDCLKDISREG) The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-5.
PMM Registers www.ti.com 5.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG) The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-6.
PMM Registers www.ti.com 5.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-7.
PMM Registers www.ti.com 5.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0) This is a read-only register. All writes are ignored. The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-8.
PMM Registers www.ti.com 5.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1) This is a read-only register. All writes are ignored. The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-9.
PMM Registers www.ti.com 5.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2) This is a read-only register. All writes are ignored. The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-10.
PMM Registers www.ti.com 5.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3) This is a read-only register. All writes are ignored. The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-11.
PMM Registers www.ti.com 5.4.10 Logic Power Domain PD6 Power Status Register (LOGICPDPWRSTAT4) This is a read-only register. All writes are ignored. The default values of the control fields are determined by the device reset configuration word stored in the TI-OTP region of flash bank 0. Figure 5-12.
PMM Registers www.ti.com 5.4.11 Global Control Register 1 (GLOBALCTRL1) Figure 5-13. Global Control Register 1 (GLOBALCTRL1) (offset = A0h) 31 16 Reserved R-0 15 9 Reserved 8 PMCTRL PWRDN R-0 R/WP-0 7 1 Reserved 0 AUTO CLK WAKE ENA R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 5-12. Global Control Register 1 (GLOBALCTRL1) Field Descriptions Bit Field 31-9 Reserved 8 Value 0 PMCTRL PWRDN Description Read returns 0.
PMM Registers www.ti.com 5.4.12 Global Status Register (GLOBALSTAT) Figure 5-14. Global Status Register (GLOBALSTAT) (offset = A8h) 31 16 Reserved R-0 15 1 0 Reserved PMCTRL IDLE R-0 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-13. Global Status Register (GLOBALSTAT) Field Descriptions Bit Field Value 31-1 Reserved 0 0 PMCTRL IDLE Description Read returns 0. Writes have no effect. State of PMC and all PSCONs.
PMM Registers www.ti.com 5.4.14 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1) Figure 5-16.
PMM Registers www.ti.com 5.4.15 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2) Figure 5-17.
PMM Registers www.ti.com 5.4.16 Isolation Diagnostic Status Register (ISODIAGSTAT) Figure 5-18. Isolation Diagnostic Status Register (ISODIAGSTAT) (offset = C0h) 31 8 Reserved R-0 4 3 2 1 0 Reserved ISO DIAG[4] ISO DIAG[3] ISO DIAG[2] ISO DIAG[1] ISO DIAG[0] R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-17.
Chapter 6 SPNU562 – May 2014 I/O Multiplexing and Control Module (IOMM) This chapter describes the I/O Multiplexing and Control Module (IOMM). 286 Topic ........................................................................................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Overview ........................................................................................................ Main Features of I/O Multiplexing Module (IOMM) .......................................
Overview www.ti.com 6.1 Overview This chapter describes the overall features of the module that control the I/O multiplexing on the device. The mapping of control registers to multiplexing options is specified in Section 6.7.13. 6.2 Main Features of I/O Multiplexing Module (IOMM) The IOMM contains memory-mapped registers (MMR) that control device-specific multiplexed functions.
Control of Multiplexed Inputs www.ti.com – If the application sets one or more reserved bit(s) within the byte 23–16, then the default function will be selected for output on N17. Figure 6-2 shows the multiplexing between the output functions for the N17 ball. This terminal uses an 8mA output buffer. Figure 6-2.
Control of Multiplexed Inputs www.ti.com Table 6-1.
Control of Multiplexed Inputs www.ti.com Table 6-1.
Control of Multiplexed Inputs www.ti.com Table 6-1.
Control of Multiplexed Inputs www.ti.com Table 6-1.
Control of Multiplexed Inputs www.ti.
Control of Multiplexed Inputs www.ti.com Table 6-2.
Control of Multiplexed Inputs www.ti.com Table 6-2.
Control of Multiplexed Inputs www.ti.com Figure 6-3.
Control of Special Multiplexed Options www.ti.com 6.5 Control of Special Multiplexed Options Several of the PINMMR registers are used to control specific functions on this microcontroller. Table 6-3.
Control of Special Multiplexed Options www.ti.com Table 6-3.
Control of Special Multiplexed Options www.ti.com 6.5.1 Control of SDRAM clock (EMIF_CLK) As shown in Table 6-1, PINMMR9[0] is set by default. This blocks the EMIF SDRAM clock signal (EMIF_CLK) from being output from the microcontroller. If the EMIF is used to connect to an external SDRAM module, then the application must enable the SDRAM clock output by clearing the PINMMR9[0] bit and set the PINMMR9[1]. 6.5.
Control of Special Multiplexed Options www.ti.com Table 6-5.
Control of Special Multiplexed Options www.ti.com Figure 6-4.
Control of Special Multiplexed Options www.ti.
Control of Special Multiplexed Options www.ti.com 6.5.6 Control for Generating Interrupt Upon External Fault Indication to N2HETx The N2HET module on this microcontroller allows the application to selectively disable any PWM output from the N2HET module whenever a fault condition is indicated to the N2HET. This fault condition is input to the N2HET module via the PIN_nDISABLE input signal.
Control of Special Multiplexed Options www.ti.com The PIN_nDISABLE signal for the N2HET2 module can also come from two different paths at either the MIBSPI3NCS[0] / AD2EVT / GIOB[2] terminal or the N2HET2[02] / N2HET2_NDIS terminal. By default with PINMMR179[0]=1 and PINMMR179[1]=0 the MIBSPI3NCS[0] / AD2EVT /GIOB[2] terminal is selected as the input for signaling the fault condition.
Control of Special Multiplexed Options www.ti.com 6.5.7 Control for Synchronizing Time Bases for All ePWMx Modules The ePWMx modules implement a mechanism that allows their time bases to be synchronized. This is done by using a signal called TBCLKSYNC, which is a common input to all the ePWMx modules. This TBCLKSYNC is generated by a register bit in the I/O multiplexing module. PINMMR166[1] is the TBCLKSYNC signal. This bit is clear ('0') by default.
Control of Special Multiplexed Options www.ti.com PINMMR165[24] and PINMMR165[25] are used to select between the ePWM1_SYNCI and the stretched N2HET1_LOOP_SYNC signals. • If PINMMR165[24] = 1 and PINMMR165[25] = 0, the SYNCI input to the ePWM1 comes from the ePWM1_SYNCI which is an output from a multiplexor. This is the default connection. There are also three possible selections from which to choose the ePWM1_SYNC1.
Control of Special Multiplexed Options www.ti.com Of the three internal error events for the trip-zone inputs, nTZ4 is connected to the eQEPx error output signal. There are two eQEP modules on this microcontroller, and registers in the I/O multiplexing module are used to allow a flexible scheme for the connection between the eQEPx error signal and the nTZ4 inputs of the ePWMx modules. Table 6-7.
Control of Special Multiplexed Options www.ti.com 6.5.11 Control for Input Connections to eQEPx Modules Each eQEPx module has four inputs from the device terminals. These inputs can be connected to the eQEPx module in two ways: 1. Double-synchronized using VCLK3, or 2. Double-synchronized using VCLK3 and then filtered through a 6-VCLK3-cycle counter Registers in the I/O multiplexing module are used to control these input connections for each eQEPx module. Table 6-9.
Control of Special Multiplexed Options www.ti.com 6.5.11.1 nERROR and nERROR1 Input Multiplexing There are two ESM modules in this microcontroller. When the microcontroller is in lockstep mode, only ESM1 is active. By default, the ESM1 Error Pin Status Register (ESMEPSR) samples the nERROR pin input. The default is achieved with PINMMR174[16] = 1. By setting PINMMR174[16] = 0, the ESM1 Error Pin Status register will sample from the nERROR1 pin instead as illustrated in Figure 6-8. Figure 6-8.
Control of Special Multiplexed Options www.ti.com 6.5.12 Selecting GIO Port for External DMA Request GIOA and GIOB ports can be used to generate external DMA request. See the datasheet for the DMA request mapping. The polarity of the GIO pin to trigger a DMA request can be selected inside the DMA module. In order to use GIO pin as an external DMA request input, the corresponding pin must be first selected by the application. By default, it is unselected. See Figure 6-9 for illustration.
Control of Special Multiplexed Options www.ti.com 6.5.13 Temperature Sensor Selection There are three instances of temperature sensors in this microcontroller. The measured temperatures are analog signals. These analog signals are connected to the on chip ADCs for conversion. Before the temperature sensors can be used, they must be enabled. By default, they are disabled with PINMMR174[24] = 1. To enable the temperature sensors, PINMMR174[24] must be cleared to 0.
Safety Features 6.6 www.ti.com Safety Features The IOMM supports certain safety functions that are designed to prevent unintentional changes to the I/O multiplexing configuration. These are described in the following sections. 6.6.1 Locking Mechanism for Memory-Mapped Registers The IOMM contains a mechanism to prevent any spurious writes from changing any of the PINMMR values. The PINMMRs are locked by default and after any system reset. None of the IOMM registers can be written under this condition.
IOMM Registers www.ti.com 6.7 IOMM Registers Table 6-12 lists the control registers in the IOMM. The address offset is specified from the base address of FFFF 1C00h. Table 6-12. IOMM Registers Offset Acronym Register Description 00h REVISION_REG Revision Register Section 6.7.1 Section 20h BOOT_REG Boot Mode Register Section 6.7.2 38h KICK_REG0 Kicker Register 0 Section 6.7.3 3Ch KICK_REG1 Kicker Register 1 Section 6.7.
IOMM Registers www.ti.com 6.7.2 BOOT_REG: Boot Mode Register Figure 6-11. BOOT_REG: Boot Mode Register (Offset = 20h) 31 16 Reserved R-0 15 1 0 Reserved ENDIAN R-0 R-D LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; R-D = Value read is determined by external configuration Table 6-14. Boot Mode Register Field Descriptions Bit Field 31-1 Reserved 0 ENDIAN Value 0 Description Reads return zeros, writes have no effect.
IOMM Registers www.ti.com 6.7.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register This register shows the status of the error conditions (before enabling) and allows setting the error status. Figure 6-14. ERR_RAW_STATUS_REG: Error Raw Status / Set Register (Offset = E0h) 31 8 Reserved R-0 7 1 0 Reserved 2 ADDR_ERR PROT_ERR R-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 6-17.
IOMM Registers www.ti.com 6.7.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register This register shows the status of the error conditions and allows clearing of the error status. Figure 6-15. ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register (Offset = E4h) 31 8 Reserved R-0 7 2 Reserved R-0 1 0 ENABLED_ ADDR_ERR ENABLED_ PROT_ERR R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 6-18.
IOMM Registers www.ti.com 6.7.7 ERR_ENABLE_REG: Error Signaling Enable Register This register shows the interrupt enable status and allows enabling of the interrupts. Figure 6-16. ERR_ENABLE_REG: Error Signaling Enable Register (Offset = E8h) 31 8 Reserved R-0 7 2 Reserved 1 ADDR_ERR_EN R-0 R/WP-0 0 PROT_ERR_EN R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 6-19.
IOMM Registers www.ti.com 6.7.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register This register shows the error signaling enable status and allows disabling of the error signaling. Figure 6-17. ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register (Offset = ECh) 31 8 Reserved R-0 7 1 0 Reserved 2 ADDR_ERR_ EN_CLR PROT_ERR_ EN_CLR R-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 6-20.
IOMM Registers www.ti.com 6.7.10 FAULT_STATUS_REG: Fault Status Register This register holds the status and attributes of the first fault transfer. Figure 6-19. FAULT_STATUS_REG: Fault Status Register (Offset = F8h) 31 28 27 24 23 16 Reserved FAULT_ID FAULT_MSTID R-0 R-0 R-0 15 13 12 9 Reserved FAULT_PRIVID R-0 R-0 8 Rsvd 7 FAULT_NS R-0 R-0 6 5 0 Rsvd FAULT_TYPE R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset Table 6-22.
IOMM Registers www.ti.com 6.7.11 FAULT_CLEAR_REG: Fault Clear Register This register allows the application to clear the current fault so that another can be captured when 1 is written to this register. Figure 6-20. FAULT_CLEAR_REG: Fault Clear Register (Offset = FCh) 31 16 Reserved R-0 15 1 0 Reserved FAULT_CLEAR R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 6-23.
IOMM Registers www.ti.com 6.7.13 PINMMRnn: Input Pin Multiplexing Control Registers These registers control the input multiplexing of the functionality available on each pad on the microcontroller. There are 20 such registers – PINMMR80 through PINMMR99. Each 8-bit field of a PINMMR register controls the functionality of a single ball/pin. The mapping between the PINMMRx control registers and the functionality selected on a given terminal is defined in Table 6-2. Figure 6-22.
Chapter 7 SPNU562 – May 2014 F021 Level 2 Flash Module Controller (L2FMC) The Flash electrically erasable programmable read-only memory module is a type of nonvolatile memory that has fast read access times and is able to be reprogrammed in the field or in the application. It also allows remapping of the flash to RAM spaces in order to save on repeated program/erase cycles. This chapter describes the Level 2 F021 Flash module controller (L2FMC). Topic 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.
Overview www.ti.com 7.1 Overview The F021 Flash is used to provide non-volatile memory for instruction execution or data storage. The Flash can be electrically programmed and erased many times to ease code development. Refer to the following documents for support on how to initialize and use the on-chip Flash and its API: • F021 (Texas Instruments 65nm Flash) Flash API Reference Guide (literature number SPNU501) 7.1.
Overview • • • • • • • • • www.ti.com OTP (one-time programmable): A program-only-once Flash sector (cannot be erased) Sector: A contiguous region of Flash memory that must be erased simultaneously. Wide_Word - the width of the data output from the Flash bank. This is 288 bits wide for main Flash banks and 72 bits wide for the FEE bank. Prefetch Mode - Provides higher performance by fetching the subsequent cache line ahead of the actual request.
SECDED www.ti.com 7.4 SECDED The Flash memory can be protected by Single Error Correction Double Error Detection (SECDED). This protection is enabled by the SECDED circuit inside of the bus master. 7.4.1 SECDED Initialization Flash error detection and correction is enabled at reset. The ECC values for all of the flash memory space (flash banks 0 through 6) must be programmed into the flash before the program/data can be read.
SECDED www.ti.com Table 7-1.
SECDED www.ti.com 7.4.3 Syndrome Table: Decode to Bit in Error The syndrome is an 8-bit value that decodes to the bit in error. The bit in error can be a bit among the 64 data bits or a bit among the 8 ECC check bits. A syndrome value of 0000 0000 indicates there is no error. Any other syndrome combinations not shown in the table are uncorrectable multi-bit error. Errors of three of more bits may escape detection. The syndrome decoding is shown in Table 7-2. Table 7-2.
SECDED www.ti.com 7.4.4 Syndrome Table: An Alternate Method Table 7-3.
Memory Map www.ti.com 7.5 Memory Map The Flash module contains the program memory, which is mapped starting at location zero, and one Customer OTP sector and one TI OTP sector per bank. The Customer OTP sectors may be programmed by the customer, but cannot be erased. They are typically blank in new parts. The TI OTP sectors are used to contain manufacturing information. They may be read by the customer but can not be programmed or erased.
Memory Map www.ti.com 7.5.2 OTP Memory 7.5.2.1 Flash Bank and Sector Sizes Flash Bank/Sectoring information can be determined from the device-specific datasheet or can be computed by reading locations in the TI OTP and L2FMC registers. The number of banks, which banks are available, and the number of sectors for bank 0 can be read from TI OTP location F008 0158h as shown in Figure 7-2 and described in Table 7-4. Figure 7-2.
Memory Map www.ti.com 7.5.2.2 Package and Memory Size Package and memory size information can be determined from the device-specific datasheet, or can be computed by reading locations in the TI OTP Bank 0 registers. The package and memory size can be read from TI OTP location F008 015Ch as shown in Figure 7-3 and described in Table 7-6. Figure 7-3. TI OTP Bank 0 Package and Memory Size Information 31 28 27 16 Reserved PACKAGE R R 15 0 MEMORY_SIZE R LEGEND: R = Read only Table 7-6.
Memory Map 7.5.2.4 www.ti.com Part Number Symbolization Device part number symbolization information can be determined from the device-specific datasheet or can be computed by reading locations in the TI OTP bank 0 registers. For example the device part number symbolization "RM57L843ZWT" can be read from TI OTP bank 0 location F008 01E0h through F008 01FFh as shown in Figure 7-5. The part number is stored as a null terminated ASCII string. Figure 7-5.
Deliberate ECC Errors for FMC ECC Checking www.ti.com Table 7-8. TI OTP Bank 0 Temperature Sensor Calibration Information Field Descriptions 7.6 Address Width Field Description F008 03x0h 16 bits SxTEMP1 The temperature in degrees Kelvin at which the lowest calibration measurement was taken. F008 03x2h 16 bits SxTEMP1VAL The value read from the ADC for this sensor at the lowest calibration temperature.
Power On, Power Off Considerations 7.7 www.ti.com Power On, Power Off Considerations 7.7.1 Error Checking at Power On As the device is coming out of the device reset sequence, the flash wrapper reads a configuration word from the TI OTP section of bank zero. These are known as Implicit Reads. This is also readable from a bus master at address 0xF0080140. During these reads ECC is enabled. Single bit errors are corrected and uncorrectable errors will generate an error event.
Emulation and SIL3 Diagnostic Modes www.ti.com 7.8.2.1 Address Tag Register Test Mode 5: DIAGMODE = 5 There are six sets of address tag registers, two for PortA and four for PortB. Each set consists of a primary and a duplicate address tag registers. Normally, these registers store the recently issued CPU addresses during prefetch mode. To detect errors in these registers, the primary and duplicate address tag registers are continuously compared to each other if the buffer is valid.
Emulation and SIL3 Diagnostic Modes 7.8.2.2 www.ti.com ECC Data Correction Diagnostic Mode 7: DIAGMODE = 7 Testing the error correction and ECC logic in the CPU involves corrupting the ECC value returned to the CPU. By inverting one or more bits of the ECC, the CPU will detect errors in a selected data or ECC bit, or in any possible value returned by the ECC. To set an error for a particular bit use the syndrome, see Table 7-3.
Emulation and SIL3 Diagnostic Modes www.ti.com 7.8.4 SECDED Software Diagnostic The SECDED block is used to perform error detection and correction on the implicit reads made after reset by L2FMC. To simplify the diagnostic for this logic, a software mechanism is used. To check that the SECDED module correctly performed its operation following steps must be used: 1. CPU reads the 64bit memory location of the implicit read. For example, implicit read location is at 0xF008_0140. 2.
Summary of L2FMC Errors www.ti.com 7.10 Summary of L2FMC Errors Table 7-11. Errors in L2FMC 338 Scenario Does this error cause a Bus Error? Does this error go to ESM? Is a flag in L2FMC set? Name of Flag Access parity error/Internal parity errors Yes Yes Yes FEDAC_PxSTATUS. ADD_PAR_ERR Port A/B Idle State parity error No Yes Yes FEDAC_PxSTATUS. MCMD_PAR_ERR Address tag error Yes Yes Yes FEDAC_PxSTATUS.
Flash Control Registers www.ti.com 7.11 Flash Control Registers This section details the Flash module registers, summarized in Table 7-12. The Flash module control registers can only be read and/or written by the CPU while in privileged mode. Each register begins on a word boundary. All registers are 32-bit, 16-bit and 8-bit accessible. The start address of the Flash module is FFF8 7000h. Table 7-12.
Flash Control Registers www.ti.com 7.11.1 Flash Read Control Register (FRDCNTL) FRDCNTL supports prefetch mode. This register controls flash timings for the main flash banks. For the equivalent register that controls flash timings for the EEPROM Emulation flash bank (bank 7), see Section 7.11.31. Figure 7-10.
Flash Control Registers www.ti.com 7.11.2 EEPROM Error Correction Control Register (EE_FEDACCTRL1) When a EEPROM bank is erased or zeroed out, the contents will be all 1's or all 0's respectively. In such a case the ECC will be incorrect. EE_FEDACCTRL1 lets the L2FMC ignore an all 1's and all 0's condition on reads from the EEPROM bank.. Figure 7-11.
Flash Control Registers www.ti.com 7.11.3 Flash PortA Error and Status Register (FEDAC_PASTATUS) This register applies to accesses made to the main or EEPROM flash banks through PortA. . All these error status bits can be cleared by writing a 1 to the bit; writing a 0 has no effect. Figure 7-12.
Flash Control Registers www.ti.com 7.11.4 Flash PortB Error and Status Register (FEDAC_PBSTATUS) This register applies to accesses made to the main or EEPROM flash banks through PortB. . All these error status bits can be cleared by writing a 1 to the bit; writing a 0 has no effect. Figure 7-13.
Flash Control Registers www.ti.com 7.11.5 Flash Global Error and Status Register (FEDAC_GBLSTATUS) This register applies to global error and status flags in L2FMC. All these status bits can be cleared by writing a 1 to the bit; writing a 0 has no effect. Figure 7-14.
Flash Control Registers www.ti.com 7.11.6 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) This register is used to disable the SECDED function for one or two sectors from the EEPROM Emulation flash (bank 7). An additional two sectors can have SECDED disabled by the use of the FEDACSDIS2 register (see Section 7.11.27). Figure 7-15.
Flash Control Registers www.ti.com 7.11.7 Primary Address Tag Register (FPRIM_ADD_TAG) This register is used to test the prefetch address tag registers. (see Section 7.8.2.1) Figure 7-16. Primary Address Tag Register (FPRIM_ADD_TAG) (offset = 28h) 31 16 PRIM_ADD_TAG RWP-0 15 5 4 0 PRIM_ADD_TAG Reserved RWP-0 R-0 LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode;; -n = value after reset; Table 7-19.
Flash Control Registers www.ti.com 7.11.9 Flash Bank Protection Register (FBPROT) Figure 7-18. Flash Bank Protection Register (FBPROT) (offset = 30h) 31 16 Reserved R-0 15 1 0 Reserved PROTL1DIS R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset Table 7-21. Flash Bank Protection Register (FBPROT) Field Descriptions Bit 31-1 0 Field Value Reserved 0 PROTL1DIS Description Reads return 0. Writes have no effect.
Flash Control Registers www.ti.com 7.11.11 Flash Bank Busy Register (FBBUSY) Figure 7-20. Flash Bank Busy Register (FBBUSY) (offset = 38h) 31 16 Reserved R-0 15 8 7 0 Reserved BUSY[7:0] R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 7-23. Flash Bank Busy Register (FBBUSY) Field Descriptions Bit Field 31-8 Reserved 7-0 BUSY Value 0 Description Reads return 0. Writes have no effect. Bank Busy. Each bit corresponds to a Flash bank.
Flash Control Registers www.ti.com 7.11.13 Flash Bank Power Mode Register (FBPWRMODE) Figure 7-22. Flash Bank Power Mode Register (FBPWRMODE) (offset = 40h) 31 16 Reserved R-505h 15 14 13 4 3 2 1 0 BANKPWR7 Reserved BANKPWR1 BANKPWR0 R/WP-3h R-3FFh R/WP-3h R/WP-3h LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset Table 7-25.
Flash Control Registers www.ti.com 7.11.14 Flash Bank/Pump Ready Register (FBPRDY) FBPRDY register allows the user to determine if the pump and banks are ready for performing read access. Figure 7-23.
Flash Control Registers www.ti.com 7.11.15 Flash Pump Access Control Register 1 (FPAC1) Figure 7-24. Flash Pump Access Control Register 1 (FPAC1) (offset = 48h) 31 27 26 16 Reserved PSLEEP R-0 R/WP-64h 15 1 0 Reserved PUMPPWR R-0 R/WP-1 LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset Table 7-27. Flash Pump Access Control Register 1 (FPAC1) Field Descriptions Bit Field 31-12 Reserved 26-16 PSLEEP Value 0 Description Reads return 0.
Flash Control Registers www.ti.com 7.11.16 Flash Module Access Control Register (FMAC) Figure 7-25. Flash Module Access Control Register (FMAC) (offset = 50h) 31 16 Reserved R-0 15 3 2 0 Reserved BANK R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset Table 7-28. Flash Module Access Control Register (FMAC) Field Descriptions Bit 31-16 2-0 Field Reserved BANK Value 0 0-7h Description Reads return 0. Writes have no effect. Bank Enable.
Flash Control Registers www.ti.com 7.11.17 Flash Module Status Register (FMSTAT) Figure 7-26.
Flash Control Registers www.ti.com Table 7-29. Flash Module Status Register (FMSTAT) Field Descriptions (continued) Bit Field 10 EV Value Erase Verify 1 9 CV BUSY 7 ERS PGM INVDAT CSTAT VOLTSTAT ESUSP When set, this bit indicates that the core voltage generator of the pump power supply dipped below the lower limit allowable during a program or erase operation. This bit is cleared by the Clear Status command.
Flash Control Registers www.ti.com 7.11.18 EEPROM Emulation Data MSW Register (FEMU_DMSW) Figure 7-27. EEPROM Emulation Data MSW Register (FEMU_DMSW) (offset = 58h) 31 16 EMU_DMSW[63:48] R/WP-0h 15 0 EMU_DMSW[47:32] R/WP-0h LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset Table 7-30. EEPROM Emulation Data MSW Register (FEMU_DMSW) Field Descriptions Bit 31-0 Field Description EMU_DMSW This register can be written by the CPU in any mode.
Flash Control Registers www.ti.com 7.11.20 EEPROM Emulation ECC Register (FEMU_ECC) Figure 7-29. EEPROM Emulation ECC Register (FEMU_ECC) (offset = 60h) 31 16 Reserved R-0 15 8 7 0 Reserved EMU_ECC[7:0] R-0 R/WP-0h LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset Table 7-32. EEPROM Emulation ECC Register (FEMU_ECC) Field Descriptions Bit Field 31-8 Reserved 7-0 EMU_ECC Value 0 Description Reads return 0. Writes have no effect.
Flash Control Registers www.ti.com 7.11.22 Diagnostic Control Register (FDIAGCTRL) First set the DIAGMODE and the DIAG_EN_KEY bits before setting up the other registers to block the other registers from causing a false error. The final write should set the DIAG_TRIG bit to activate the test. Running out of RAM will prevent problems with the diagnostic test corrupting the flash access in some of the modes. Figure 7-31.
Flash Control Registers 7.11.23 www.ti.com Raw Address Register (FRAW_ADDR) Figure 7-32. Raw Address Register (FRAW_ADDR) (offset = 74h) 31 5 4 0 RAW_DATA[31:5] Reserved RWP-u R-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset -u = Unchanged value on internal reset, cleared on power up Table 7-35. Raw Address Register (FRAW_ADDR) Field Descriptions Bit 31-5 Field Description RAW_DATA Raw Address.
Flash Control Registers www.ti.com 7.11.24 Parity Override Register (FPAR_OVR) This register allows overriding the parity that is internally computed by the L2FMC for checking the parity circuit. Figure 7-33. Parity Override Register (FPAR_OVR) (offset = 7Ch) 31 18 15 12 17 16 Reserved PAR_OVR_SEL R-0 R/WP-0 11 9 8 0 PAR_DIS_KEY PAR_OVR_KEY Reserved R/WP-5h R/WP-2h R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-36.
Flash Control Registers www.ti.com 7.11.25 Reset Configuration Valid Register (RCR_VALID) This register reflects the validity of the implicit read. Figure 7-34. Reset Configuration Valid Register (RCR_VALID) (offset = B4h) 31 16 Reserved R-0 15 1 0 Reserved 2 JSM_VALID RCR_VALID R-0 R-1 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-37.
Flash Control Registers www.ti.com 7.11.27 Flash Error Detection and Correction Sector Disable Register 2 (FEDACSDIS2) This register is used to disable the SECDED function on additional two sectors on the EEPROM Emulation flash (bank 7). Figure 7-36.
Flash Control Registers www.ti.com 7.11.28 Lower Word of Reset Configuration Read Register (RCR_VALUE0) When L2FMC completes the implicit read, it populates this register with the lower 32 bits of the data. This is useful to perform a software diagnostic of the SECDED module Figure 7-37.
Flash Control Registers www.ti.com 7.11.30 FSM Register Write Enable Register (FSM_WR_ENA) Figure 7-39. FSM Register Write Enable Register (FSM_WR_ENA) (offset = 288h) 31 16 Reserved R-0 15 3 2 0 Reserved WR_ENA R-0 R/WP-2h LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset Table 7-42. FSM Register Write Enable Register (FSM_WR_ENA) Field Descriptions Bit Field 31-3 Reserved 2-0 WR_ENA Value Description 0 Reads return 0. Writes have no effect.
Flash Control Registers www.ti.com 7.11.32 FSM Sector Register 1 (FSM_SECTOR1) This is a banked register. A separate register is implemented for each bank, but they all occupy the same address. The correct bank must be selected in the FMAC register before reading or writing this register. See Section 7.11.16. Figure 7-41.
Flash Control Registers www.ti.com 7.11.34 Flash Bank Configuration Register (FCFG_BANK) Figure 7-43. Flash Bank Configuration Register (FCFG_BANK) (offset = 400h) 31 20 19 16 EE_BANK_WIDTH Reserved R-48h R-1 15 4 3 0 MAIN_BANK_WIDTH Reserved R-90h R-2h LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up Table 7-46.
POM Control Registers www.ti.com 7.12 POM Control Registers This section details the POM module registers listed in Table 7-47. The POM module control registers can only be read and/or written while in privileged or debug mode. Each register begins on a word boundary. All registers are 32-bit, 16-bit and 8-bit accessible. The start address of the POM module is FFA0 4000h. Table 7-47. POM Control Registers Offset Acronym Register Description 00h POMGLBCTRL POM Global Control Register Section 7.12.
POM Control Registers www.ti.com 7.12.2 POM Revision ID Register (POMREV) Figure 7-45. POM Revision ID Register (POMREV) (offset = 04h) 31 16 REVID R-0108h 15 0 REVID R-CA03h LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up Table 7-49. POM Revision ID Register (POMREV) Field Descriptions Bit Field 31-0 REVID Value Description 0108CA03h Revision ID of POM 7.12.
POM Control Registers www.ti.com 7.12.4 POM Region Start Address Register (POMPROGSTARTx) This set of registers contains the start address of each region which is to be remapped. These registers are at an offset 200h + (10h x region number). Region numbers are counted from 0 onwards. Figure 7-47. POM Region Start Address Register (POMPROGSTARTx) (offset = 200h, 210h,..
POM Control Registers www.ti.com 7.12.6 POM Region Size Register (POMREGSIZEx) Contains the size of the program memory and overlay memory region. Figure 7-49. POM Region Size Register (POMREGSIZEx) (offset = 208h, 218h, ...) 31 16 Reserved R-0 15 4 3 0 Reserved SIZE R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset Table 7-53.
Chapter 8 SPNU562 – May 2014 Level 2 RAM (L2RAMW) Module This chapter describes the Level II RAM (L2RAM) module. Topic 8.1 8.2 8.3 370 ........................................................................................................................... Page Overview ......................................................................................................... 371 Module Operation .............................................................................................
Overview www.ti.com 8.1 Overview The Level 2 RAM (L2RAM) module controls and decodes RAM memory accesses on this device.
Module Operation www.ti.com NOTE: No ECC Error Generated for Accesses to ECC Memory: A read from the ECC memory itself would generate an ECC value on both the read data bus as well as the 8-bit ECC bus. This could result in the detection of a multi-bit error by the SECDED logic inside the CPU. The L2RAMW interface module ignores the ECC errors that are indicated by the CPU when accessing ECC space. Figure 8-1.
Module Operation www.ti.com 8.2.2.2 Memory Scrubbing To increase memory reliability, the L2RAMW has an optional "memory scrubbing" feature, which automatically corrects single bit errors whenever they are detected during any RAM read. The reason for performing this action is that if a single bit error occurs on the RAM, and no immediate action is taken to correct it, it is possible that a nearby bit cell will be corrupted as well at some point.
Module Operation 8.2.2.5 www.ti.com Support for Cortex-R5F CPU's Address and Control Bus Parity Checking The Cortex-R5F CPU provides parity bits for the address and control signals going to L2RAMW. The L2RAMW module also computes the parity bits based on the CPU's address bus and control signals. The computed parity bits are compared against the parity bits received from the CPU.
Module Operation www.ti.com 8.2.3 L2RAMW Auto-Initialization The RAM memory can be initialized by using the dedicated auto-initialization hardware. The L2RAMW module initializes the entire memory when the auto-init is enabled for the RAM. All RAM data memory is initialized to zeros and the ECC memory is initialized to the correct ECC value for zeros, that is, 0Ch. 8.2.
Control and Status Registers 8.3 www.ti.com Control and Status Registers The L2RAMW Module registers listed in Table 8-2 are accessed through the system module register space in the Cortex-R5F CPUs memory map. All registers are 32-bit wide and are located on a 32-bit boundary. Reads and writes to registers are supported in 8-, 16-, and 32-bit accesses. The base address for the L2RAMW control registers is FFFF F900h. Table 8-2.
Control and Status Registers www.ti.com Table 8-3. L2RAMW Module Control Register (RAMCTRL) Field Descriptions (continued) Bit Field Value 27-24 ADDR PARITY OVERRIDE 23-21 Reserved 20 Description Address Parity Override. This field, when set to Ah, will invert the parity scheme selected by the device global parity selection. The address parity checker would then work on the inverted parity scheme. By default, the parity scheme is the same as the global device parity scheme.
Control and Status Registers www.ti.com 8.3.2 L2RAMW Error Status Register (RAMERRSTATUS) The RAMERRSTATUS register, shown in Figure 8-3 and described in Table 8-4, indicates the status of the various error conditions monitored by the L2RAMW Module. Figure 8-3.
Control and Status Registers www.ti.com Table 8-4. L2RAMW Module Error Status Register (RAMERRSTATUS) Field Descriptions (continued) Bit Field 16 MSACP 15 Reserved 13 MIE 11 10 9 8 7 0 An address control parity error did not occur during memory scrubbing write back 1 An address control parity error occurred during memory scrubbing write back Command Parity Error on Idle. This bit indicates an error occurred for an idle command with parity error.
Control and Status Registers www.ti.com Table 8-4. L2RAMW Module Error Status Register (RAMERRSTATUS) Field Descriptions (continued) Bit Field 4 ADDE 3 2 1 0 380 Value Description Redundant address decoding diagnostic error. This bit indicates that the redundant address decode logic diagnostic test has detected that a compare element has malfunctioned during the testing of the logic. This bit is only set in test mode.
Control and Status Registers www.ti.com 8.3.3 L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H) The DIAG_DATA_VECTOR_H register, shown in Figure 8-4 and described in Table 8-5, is used in conjunction with the RAMTEST register to perform diagnostic tests. Figure 8-4. L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H) (offset = 24h) 31 0 DIAGNOSTIC VECTOR[63:32] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 8-5.
Control and Status Registers www.ti.com 8.3.5 L2RAMW Diagnostic ECC Vector Register (DIAG_ECC) The DIAG_ECC register, shown in Figure 8-6 and described in Table 8-7, captures the address for which the Cortex-R5F CPU detected a multi-bit error. Figure 8-6.
Control and Status Registers www.ti.com 8.3.6 L2RAMW RAM Test Mode Control Register (RAMTEST) The RAMTEST register, shown in Figure 8-7 and described in Table 8-8, controls the test mode of the L2RAMW Module. Figure 8-7.
Control and Status Registers www.ti.com 8.3.7 L2RAMW RAM Address Decode Vector Test Register (RAMADDRDEC_VECT) The RAMADDRDEC_VECT register, shown in Figure 8-8 and described in Table 8-9, is used for testing the redundant address decode and compare logic of the L2RAMW Module. Figure 8-8.
Control and Status Registers www.ti.com 8.3.8 L2RAMW Memory Initialization Domain Register (MEMINIT_DOMAIN) The MEMINIT_DOMAIN register, shown in Figure 8-9 and described in Table 8-10, stores the address for which an address-parity error was detected. Figure 8-9.
Control and Status Registers www.ti.com 8.3.9 L2RAMW Bank to Domain Mapping Register0 (BANK_DOMAIN_MAP0) The BANK_DOMAIN_MAP0 register, shown in Figure 8-10 and described in Table 8-11, stores the address for which an address-parity error was detected. Figure 8-10.
Control and Status Registers www.ti.com Figure 8-11.
Chapter 9 SPNU562 – May 2014 Programmable Built-In Self-Test (PBIST) Module This chapter describes the programmable built-in self-test (PBIST) controller module used for testing the on-chip memories. 388 Topic ........................................................................................................................... 9.1 9.2 9.3 9.4 9.5 9.6 Overview ......................................................................................................... RAM Grouping and Algorithm ......
Overview www.ti.com 9.1 Overview The PBIST (Programmable Built-In Self-Test) controller architecture provides a run-time-programmable memory BIST engine for varying levels of coverage across many embedded memory instances. 9.1.
RAM Grouping and Algorithm 9.1.3.1 www.ti.com On-chip ROM The on-chip ROM contains the information regarding the algorithms and memories to be tested. 9.1.3.2 Host Processor Interface to the PBIST Controller Registers The Cortex-R5F CPU can select the algorithm and RAM groups for the memories' self-test from the onchip ROM based on the application requirements.
PBIST Flow www.ti.com 9.3 PBIST Flow Figure 9-1 illustrates the memory self-test flow. Figure 9-2. PBIST Memory Self-Test Flow Diagram Yes Is system in reset = 1? No Setup memories, peripheral and clock tree like HCLK, VCLK peripheral and ROMCLK as required for the PBIST test. Enable PBIST controller by by writing MSIENA = 0x01 Reset the PBIST controller by writing MSTGCR=0x0A Wait for approximately N vbus clocks.
PBIST Flow www.ti.com 9.3.1 PBIST Sequence Before starting the PBIST sequence, users should ensure that both the instruction cache and data cache are disabled. By default, PBIST will test all on-chip SRAMs including both the instruction and data cache memories. After reset, cache is disabled by default. If cache has been enabled, then follow the below code example to disable the cache.
PBIST Flow www.ti.com 14. After required Memory tests are completed, Resume or Start the Normal Application software. NOTE: The contents of the selected memory before the test will be completely lost. User software must take care of data backup if required. Typically the PBIST tests are carried out at the beginning of Application software. NOTE: Memory test fail information is reported in terms of RGS:RDS and not RAM GROUP.
Memory Test Algorithms on the On-chip ROM 9.4 www.ti.com Memory Test Algorithms on the On-chip ROM This section provides a brief description for some of the test algorithms used for memory self-test. 1. March13N: • March13N is the baseline test algorithm for SRAM testing. It provides the highest overall coverage. The other algorithms provide additional coverage of otherwise missed boundary conditions of the SRAM operation.
PBIST Control Registers www.ti.com 9.5 PBIST Control Registers PBIST controller uses configuration registers for programming the algorithm and its execution. All the configuration registers are memory mapped for access by the CPU through the Peripheral Bus interface. The base address for the control registers is FFFF E400h. NOTE: There is no watchdog functionality implemented in the PBIST controller. If a bad code is executed, the PBIST will run forever.
PBIST Control Registers www.ti.com 9.5.1 RAM Configuration Register (RAMT) This register is divided into following internal registers, none of which have a default value after reset. Figure 9-3 and Table 9-2 illustrate this register. This register provides the information regarding the memory being currently tested. In case of a PBIST failure, the application can read this register to identify the RGS:RDS values for the memory that failed the self-test. Figure 9-3.
PBIST Control Registers www.ti.com 9.5.2 Datalogger Register (DLR) This register puts the PBIST controller into the appropriate comparison modes for data logging. Figure 9-4 and Table 9-3 illustrate this register. Figure 9-4. Datalogger Register (DLR) [offset = 0164h] 31 16 Reserved R-0 15 4 3 2 Reserved 5 DLR4 Rsvd DLR2 1 Reserved 0 R-0 R/W-0 R/W-1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-3.
PBIST Control Registers www.ti.com 9.5.3 PBIST Activate/ROM Clock Enable Register (PACT) This is the first register that needs to be programmed to activate the PBIST controller. Bit [0] is used for static clock gating, and unless a ‘1’ is written to this bit, all the internal PBIST clocks are shut off. Bit [1] is for turning on the clock going to the instruction ROM. Figure 9-5 and Table 9-4 illustrate this register. Figure 9-5.
PBIST Control Registers www.ti.com 9.5.4 PBIST ID Register Functionality of the register is described in Figure 9-6 and Table 9-5. Figure 9-6. PBIST ID Register [offset = 184h] 31 16 Reserved R-0 15 8 7 0 Reserved PBIST ID R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-5. PBIST ID Register Field Descriptions Bit Field 31-8 Reserved 7-0 PBIST ID Value 0 SPNU562 – May 2014 Submit Documentation Feedback Description Reads return 0. Writes have no effect.
PBIST Control Registers www.ti.com 9.5.5 Override Register (OVER) Functionality of the register is described in Figure 9-7 and Table 9-6. Figure 9-7. Override Register (OVER) [offset = 0188h] 31 16 Reserved R-0 15 3 2 1 0 Reserved Reserved OVER0 R-0 R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-6. Override Register (OVER) Field Descriptions Bit Field Value Description 31-3 Reserved 0 Read returns 0. Writes have no effect.
PBIST Control Registers www.ti.com 9.5.6 Fail Status Fail Registers (FSRF0 and FSRF1) These registers indicate if a failure occurred during a memory self-test. Bit 0 gets set whenever a failure occurs. FSRF0 indicates Port0 failures and FSRF1 indicates Port1 failures. The PBIST controller has these two ports in order to optimize testing of single-port and dual-port RAMs. Figure 9-8 and Table 9-7 illustrate the FSRF0 register, while Figure 9-9 and Table 9-8 illustrate the FSRF1 register. Figure 9-8.
PBIST Control Registers www.ti.com 9.5.7 Fail Status Count Registers (FSRC0 and FSRC1) These registers keep count of the number of failures observed during the memory self-test. The PBIST controller stops executing the memory self-test whenever a failure occurs in any memory instance for any of the test algorithms. The value in FSRC0 / FSRC1 gets incremented by one whenever a failure occurs and gets decremented by one when the failure is processed. FSRC0 is for Port 0 and FSRC1 is for Port 1.
PBIST Control Registers www.ti.com 9.5.8 Fail Status Address Registers (FSRA0 and FSRA1) These registers capture the memory address of the first failure on port 0 and port 1 respectively. Figure 912 and Table 9-11 illustrate the FSRA0 register, while Figure 9-13 and Table 9-12 illustrate the FSRA1 register. Figure 9-12. Fail Status Address Register 0 (FSRA0) [offset = 01A0h] 31 16 Reserved R-0 15 0 FSRA0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-11.
PBIST Control Registers www.ti.com 9.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) These registers are used to capture the failure data in case of a memory self-test failure. FSRDL0 corresponds to Port 0, while FSRDL1 corresponds to Port 1. Figure 9-14 and Table 9-13 illustrate the FSRDL0 register, while Figure 9-15 and Table 9-14 illustrate the FSRDL1 register. Figure 9-14.
PBIST Control Registers www.ti.com 9.5.10 ROM Mask Register (ROM) This two-bit register sets appropriate ROM access modes for the PBIST controller. The default value is 11b. This register is illustrated in Figure 9-16. It can be programmed according to Table 9-15. Figure 9-16. ROM Mask Register (ROM) [offset = 01C0h] 31 16 Reserved R-0 15 2 1 0 Reserved ROM R-0 R/W-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-15.
PBIST Control Registers www.ti.com 9.5.11 ROM Algorithm Mask Register (ALGO) This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. For example, bit 0 controls whether algorithm 1 is enabled or not. Figure 9-17 and Table 9-16 illustrate this register. Figure 9-17.
PBIST Control Registers www.ti.com 9.5.12 RAM Info Mask Lower Register (RINFOL) This register is to select RAM groups to run the algorithms selected in the ALGO register. For an algorithm to be executed on a particular RAM group, the corresponding bit in this register must be set to ‘1’. The default value of this register is all ‘1’s, which means all the RAM Groups are selected. Figure 9-18 and Table 9-17 illustrate this register.
PBIST Control Registers www.ti.com 9.5.13 RAM Info Mask Upper Register (RINFOU) This register is to select RAM groups to run the algorithms selected in the ALGO register. For an algorithm to be executed on a particular RAM group, the corresponding bit in this register should be set to ‘1’. The default value of this register is all ‘1’s, which means all the RAM Info Groups would be selected. Figure 919 and Table 9-18 illustrate this register. Figure 9-19.
PBIST Configuration Example www.ti.com 9.6 PBIST Configuration Example The following examples assume that the PLL is locked and selected as clock source with GCLK = 300 MHz and VCLK = 75 MHz. 9.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM This example explains the configurations for running March13 algorithm on DCAN1. 1. Program the GCLK to PBIST ROM clock ratio to 1:4 in System Module. MSTGCR[9:8] = 2 2. Enable PBIST Controller in System Module.
PBIST Configuration Example www.ti.com 9.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups This example explains the configurations for running March13 algorithm on all RAM groups defined in the PBIST ROM. 1. Program the GCLK to PBIST ROM clock ratio to 1:4 in System Module. MSTGCR[9:8] = 2 2. Enable PBIST Controller in System Module. MSIENA[31:0] = 0x00000001 3. Enable the PBIST self-test in System Module. MSTGCR[3:0] = 0xA 4.
Chapter 10 SPNU562 – May 2014 Self-Test Controller (STC) Module This chapter describes the basics and configuration of the on chip self-test controller (STC) modules. Topic ........................................................................................................................... 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 General Description .......................................................................................... STC Module Assignments ..........................
General Description www.ti.com 10.1 General Description The self-test controller (STC) module is used to test the ARM CPU core and other complex digital IPs using the 'Deterministic Logic Built-in Self-Test' (LBIST) controller as the test engine. To achieve better coverage for the self-test of complex cores like Cortex-R5F, on-chip logic BIST is the preferred solution over software based self-test. There are two STC modules implemented on this device. STC1 for redundant CPUs and their µSCU block.
General Description www.ti.com 10.1.2 Terminology Interval: An interval corresponds to a test set that is the basic test unit for the STC module Segment: A self-test segment corresponds to a portion of the unique/discrete safety critical logic which can be tested in isolation from the rest of the system by the self-test controller and DBIST logic. A self-test segment may correspond to a logic like CPU core (for example, Cortex-R5F) or an IP (for example, µSCU or nHET) or a sub-system.
General Description www.ti.com 10.1.3.3 Peripheral Bus (VBUSP) Interface STC control registers are accessed through Peripheral Bus (VBUSP) Interface. During application programming, configuration registers are programmed through the Peripheral Bus Interface to enable and run the self-test controller. Figure 10-1.
General Description www.ti.com Figure 10-2.
General Description www.ti.com Figure 10-3.
General Description www.ti.com Figure 10-4.
General Description www.ti.com Figure 10-5.
STC Module Assignments www.ti.com 10.2 STC Module Assignments There are two instances of STC modules available on this device, see Table 10-1. STC1 is used for running self-test on the redundant CPUs and µSCU. STC2 is used for running self-test on the two nHET modules. The two instances are independent of each other. Table 10-1.
STC Programmers Flow www.ti.com 10.3 STC Programmers Flow Figure 10-6. STC Programmers Flow Chart SYSTEM RESET N Is SYS_NRST = 1 Y Is PLL_LOCK = 1? N Y Y Is ST_ACTIVE Key Active? Program SYS GHVSRC to select PLL and program CLKCNTL registers N N Read back CORE_SEL.
Application Self-Test Flow www.ti.com 10.4 Application Self-Test Flow This section describes the STC module configuration and the application self-test flow that you should follow for successful execution. The following two configurations must be part of the STC initialization code: • STC clock rate configuration, STC clock divider (STCCLKDIV) register is used to divide system clock to generate STCCLK for each segment. • Clear SYSESR register before triggering an STC test. 10.4.
Application Self-Test Flow www.ti.com 10.4.3 Entering CPU Idle Mode After enabling the STC test by writing the STC enable key, the test is triggered only after the CPU is taken to idle mode by executing the CPU Idle Instruction asm(“ WFI”). 10.4.4 Entering nHET Idle Mode After enabling the STC test by writing the STC enable key, the test is triggered only after the nHET module is put in reset state by writing to bit 0 the HETGCR Global Configuration Register in the nHET module. 10.4.
Application Self-Test Flow www.ti.com Figure 10-7.
STC1 Segment 0 (CPU) Test Coverage and Duration www.ti.com 10.5 STC1 Segment 0 (CPU) Test Coverage and Duration The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in Table 10-2. Table 10-2. STC1 Segment 0 Test Coverage and Duration Intervals Test Coverage Test Time (Cycles) Intervals Test Coverage Test Time (Cycles) 0 0 0 63 92.24 102627 1 56.85 1629 64 92.31 104256 2 64.19 3258 65 92.38 105885 3 68.76 4887 66 92.44 107514 4 71.
STC1 Segment 0 (CPU) Test Coverage and Duration www.ti.com Table 10-2. STC1 Segment 0 Test Coverage and Duration (continued) Intervals Test Coverage Test Time (Cycles) Intervals Test Coverage Test Time (Cycles) 44 90.57 71676 107 94.72 174303 45 90.67 73305 108 94.78 175932 46 90.77 74934 109 94.82 177561 47 90.89 76563 110 94.86 179190 48 91.00 78192 111 94.91 180819 49 91.08 79821 112 94.95 182448 50 91.17 81450 113 94.99 184077 51 91.26 83079 114 95.
STC1 Segment 1 (uSCU) Test Coverage and Duration www.ti.com 10.6 STC1 Segment 1 (uSCU) Test Coverage and Duration The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in Table 10-4. Table 10-4. STC1 Segment 1 Test Coverage and Duration Intervals Test Coverage Test Time (Cycles) Intervals Test Coverage Test Time (Cycles) 0 0 0 2 87.96 3258 1 84.79 1629 3 88.
STC2 (nHET) Test Coverage and Duration www.ti.com 10.7 STC2 (nHET) Test Coverage and Duration The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in Table 10-6. Table 10-6. STC2 Test Coverage and Duration Intervals Test Coverage Test Time (Cycles) Intervals Test Coverage Test Time (Cycles) 0 0 0 29 94.97 39585 1 70.01 1365 30 95.03 40950 2 77.89 2730 31 95.10 42315 3 81.73 4095 32 95.16 43680 4 84.11 5460 33 95.22 45045 5 86.
STC Control Registers www.ti.com 10.8 STC Control Registers STC control registers are accessed through Peripheral Bus (VBUSP) interface. Read and write access in 8,16, and 32 bit are supported. The base address for the control registers of STC1 is FFFF E600h. The base address for the control registers of STC2 is FFFF 0800h. NOTE: In suspend mode, all registers can be written irrespective of user or privilege mode and reads will not clear the 'read-clear' bits. Table 10-8.
STC Control Registers www.ti.com 10.8.1 STC Global Control Register 0 (STCGCR0) This register is described in Figure 10-8 and Table 10-9. NOTE: On a powerup reset or system reset this register gets reset to its default values. Figure 10-8.
STC Control Registers www.ti.com 10.8.2 STC Global Control Register 1 (STCGCR1) This register is described in Figure 10-9 and Table 10-10. NOTE: On a powerup reset or system reset this register resets to its default values. Also this register automatically resets to its default values at the completion of a self-test run. Figure 10-9.
STC Control Registers www.ti.com 10.8.4 STC Current ROM Address Register - CORE1 (STCCADDR1) This register is described in Figure 10-11 and Table 10-12. NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 on the start of a self-test run, or on a powerup reset or system reset, this register resets to all zeroes. Figure 10-11. STC Current ROM Address Register (STCCADDR1) [offset = 0Ch] 31 0 ADDR R-0 LEGEND: R = Read only; -n = value after nPORST (power on reset) or System reset Table 10-12.
STC Control Registers www.ti.com 10.8.6 Self-Test Global Status Register (STCGSTAT) This register is described in Figure 10-13 and Table 10-14. NOTE: The two status bits can be cleared to their default values on a write of 1 to the bits. Additionally when the STC_ENA key is written from a disabled state to enabled state, the two status flags get cleared to their default values. This register gets reset to its default value with power on reset assertion. Figure 10-13.
STC Control Registers www.ti.com 10.8.7 Self-Test Fail Status Register (STCFSTAT) This register is described in Figure 10-14 and Table 10-15. NOTE: The three status bits can be cleared to their default values on a write of 1 to the bits. Additionally when the STC_ENA key in STCGCR1 is written from a disabled state to an enabled state, the three status bits get cleared to their default values. This register gets reset to its default value with power on reset assertion.
STC Control Registers www.ti.com 10.8.8 CORE1 Current MISR Registers (CORE1_CURMISR[3:0]) This register is described in Figure 10-15 through Figure 10-18 and Table 10-16. NOTE: This register gets reset to its default value with power-on or system reset assertion. Figure 10-15. CORE1 Current MISR Register (CORE1_CURMISR3) [offset = 1Ch] 31 16 MISR[31:16] R-0 15 0 MISR[15:0] R-0 LEGEND: R = Read only; -n = value after reset Figure 10-16.
STC Control Registers www.ti.com 10.8.9 CORE2 Current MISR Registers (CORE2_CURMISR[3:0]) This register is described in Figure 10-19 through Figure 10-22 and Table 10-17. NOTE: This register gets reset to its default value with power-on or system reset assertion. Figure 10-19. CORE2 Current MISR Register (CORE2_CURMISR3) [offset = 2Ch] 31 16 MISR[31:16] R-0 15 0 MISR[15:0] R-0 LEGEND: R = Read only; -n = value after reset Figure 10-20.
STC Control Registers www.ti.com 10.8.10 Signature Compare Self-Check Register (STCSCSCR) This register is described in Figure 10-23. This register is used to enable the self-check feature of the CPU Self-Test Controller's (STC) signature compare logic. Self-check can only be done for the STC interval 0 by setting the RS_CNT bit in STCGCR0 to 1 to restart the self-test. The STC run will fail for signature miss-compare, provided the signature compare logic is operating correctly.
STC Control Registers www.ti.com 10.8.12 STC Clock Prescalar Register (STCCLKDIV) This register is described in Figure 10-25. This register is used to configure STC clock divider ratio for each segment. STCCLK is derived from the system clock (GCLK for STC1 and VCLK2 for STC2) and the configured ratio is applied when the corresponding segment is under test.
STC Control Registers www.ti.com 10.8.13 Segment Interval Preload Register (STCSEGPLR) This register is described in Figure 10-26. This register is used to specify the segment for which the first interval will be run. The address of the first interval of the selected segment is loaded to the STC ROM address counter before the test is started. Figure 10-26.
STC Configuration Example www.ti.com 10.9 STC Configuration Example The following example provides steps to configure STC1 to run self-test on CPUs and the uSCU unit. It that the PLL is locked and selected as the system clock source with GCLK = 330 MHz and HCLK = 110 MHz prior to going through the following configurations. 10.9.1 Example: STC1 Self-Test Run This example explains the configurations for running STC Test for on 40 test intervals. 1.
Self-Test Controller Diagnostics www.ti.com 10.10 Self-Test Controller Diagnostics This section provides the recommended flow for the self-test controller diagnostics. This test is recommended to be done at the application startup only, not with individual interval runs during the application. Step 1: Configure the interval count to 1 in STCGCR0 register.
Chapter 11 SPNU562 – May 2014 System Memory Protection Unit (NMPU) This chapter describes the System Memory Protection Unit (NMPU). Topic 11.1 11.2 11.3 11.4 ........................................................................................................................... Overview ......................................................................................................... Module Operation .............................................................................................
Overview www.ti.com 11.1 Overview The System Memory Protection Unit module(s) provide an mechanism to control the memory access rights of bus masters in the system other than the host CPU. The programmer's model for the System Memory Protection unit is similar to but a subset of the host CPU's own memory protection unit. It allows memory partition into multiple regions and allows individual access protection for each region from a bus master point of view.
Overview www.ti.com 11.1.3 Block Diagram Figure 11-1 shows the block diagram of NMPU. Figure 11-1. NMPU Block Diagram Input Bus Master Interface Int addr Diagnostic Logic MPU Register Block Diag mode control Error Pulse and Response Generation 0 ... Address and Access Permission Comparator 7 Priority Mux fail Error ...
Module Operation www.ti.com 11.2 Module Operation 11.2.1 Functional Mode On reset, NMPU is disabled and no filtering will be done on the bus. User must ensure that no bus transaction from the master is on going while NMPU is getting disabled or enabled. This is similar to the need to flush transactions using memory barrier instructions on the CPU before changing CPU MPU setting.
Module Operation www.ti.com Figure 11-2. MPU Region Priority Highest Priority Yes Region N-1 Enable? Region N-1 Address Match Yes No Region N-1 Permission Match Yes No Region N-2 Enable? Yes Region N-2 Address Match Yes No Region N-2 Permission Match Yes No Lowest Priority Region 0 Enable? No Yes Region 0 Address Match Yes No Yes Update ERRSTAT and ERRADDR.
Module Operation www.ti.com 11.2.2 Diagnostic Mode Diagnostic mode can be used to verify the MPU address and access permission comparator logic. Entering or exiting the diagnostic mode will automatically clear the MPUERRSTAT and MPUERRADDR registers. Memory protection must be disabled while entering or exiting diagnostic mode. There are two different diagnostic modes: internal diagnostic mode and external diagnostic mode. 11.2.2.
How to Use NMPU www.ti.com 11.2.3.2 Lock Feature for NMPU Lock feature prevents unintentional updates to NMPU registers. Writes to registers other than MPUERRSTAT is possible only when NMPU is unlocked by writing 0xAh to LOCK key bits of MPULOCK register. On reset, these bits are set to 0x5h and hence the NMPU registers are in the locked state. All NMPU registers are writable only in privilege mode. There is no built in protection based on master ID.
How to Use NMPU www.ti.com Figure 11-3.
How to Use NMPU www.ti.com 7. Program the MPUREGSENA register (Section 11.4.11) to set the size, and enable MPU region number indicated by step 5 above. Notice that this is not yet enabling the NMPU module. 8. Program the MPUREGACR register (Section 11.4.12) to set access permission for user or privilege mode. 9. Repeat steps 5 to 8 for the remaining MPU regions available for the particular NMPU instance. 10. Write 0xA to MPUENA field of MPUCTRL1 register (Section 11.4.
How to Use NMPU www.ti.com 11.3.2.1 How to Run Internal Diagnostic Mode In internal diagnostic mode, diagnostic logic inside the NMPU module drives the input of the MPU address and access permission comparator logic. User can program the address for which comparison needs to be performed and the type of transaction (read/write and user/privilege).
How to Use NMPU www.ti.com 11.3.2.2 How to Run External Diagnostic Mode In external diagnostic mode, the actual bus master initiates the memory transaction. Address from the bus master is replaced by the address in MPUDIAGADDR register before the address reaches the address comparator logic. In this mode, both bus error response and ERROR pulse to ESM (if ERRENA field of MPUCTRL2 register is set to 0xAh) are generated for accesses that violate the access permissions.
NMPU Registers www.ti.com 11.4 NMPU Registers The new memory protection unit (NMPU) registers listed in Table 11-3 are accessed through the system module register space in the Cortex-R5F CPUs memory map. All registers are 32-bit wide and are located on a 32-bit boundary. Reads and writes to registers are supported in 8-, 16-, and 32-bit accesses. Refer to the device specific datasheet for the base address of each instance of NMPU in the device.
NMPU Registers www.ti.com 11.4.1 MPU Revision ID Register (MPUREV) Figure 11-4. MPU Revision ID Register (MPUREV) (offset = 00h) 31 30 29 28 27 16 SCHEME Reserved FUNC R-1 R-0 R-A0Ch 15 11 10 8 7 6 5 0 RTL MAJOR CUSTOM MINOR R-0 R-1 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 11-4. MPU Revision ID Register (MPUREV) Field Descriptions Bit Field Value Description 31-30 SCHEME 1 Identification scheme. 29-28 Reserved 0 Reserved. Reads return 0.
NMPU Registers www.ti.com 11.4.3 MPU Diagnostics Control Register (MPUDIAGCTRL) Figure 11-6. MPU Diagnostics Control Register (MPUDIAGCTRL) (offset = 08h) 31 24 Reserved R-0 23 19 18 17 16 Reserved U_P R_W INT_EXT R-0 R/WP-0 R/WP-0 R/WP-0 15 8 7 4 3 0 Reserved DIAGKEY Reserved R-0 R/WP-5h R-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 11-6.
NMPU Registers www.ti.com 11.4.4 MPU Diagnostic Address Register (MPUDIAGADDR) Figure 11-7. MPU Diagnostic Address Register (MPUDIAGADDR) (offset = 0Ch) 31 0 DIAG ADDRESS R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 11-7. MPU Diagnostic Address Register (MPUDIAGADDR) Field Descriptions Bit 31-0 Field Description DIAG ADDRESS Diagnostic address.
NMPU Registers www.ti.com Table 11-8. MPU Error Status Register (MPUERRSTAT) Field Descriptions (continued) Bit Field 25 APERR 24-19 Reserved 18-16 REGION 15-14 Reserved 13-8 MASTERID Value Description Access Permission Error. This field is read only and is automatically reset by clearing the ERRFLAG bit. This field is not updated when the ERRFLAG bit is set. Writes have no effect. 0 Access permission violation did not occur in any of the enabled MPU regions.
NMPU Registers www.ti.com 11.4.6 MPU Error Address Register (MPUERRADDR) Figure 11-9. MPU Error Address Register (MPUERRADDR) (offset = 14h) 31 0 COMPARE FAIL ADDRESS R-0 LEGEND: R = Read only; -n = value after reset Table 11-9. MPU Error Address Register (MPUERRADDR) Field Descriptions Bit 31-0 Field Description COMPARE FAIL ADDRESS Address for MPU compare fail.
NMPU Registers www.ti.com 11.4.8 MPU Control Register 2 (MPUCTRL2) Figure 11-11. MPU Control Register 2 (MPUCTRL2) (offset = 24h) 31 16 Reserved R-0 15 4 3 0 Reserved ERRENA R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 11-11. MPU Control Register 2 (MPUCTRL2) Field Descriptions Bit Field 31-4 Reserved 3-0 ERRENA Value 0 Description Reserved. Reads return 0. MPU Error Pulse Enable.
NMPU Registers www.ti.com 11.4.9 MPU Type Register (MPUTYPE) Figure 11-12. MPU Type Register (MPUTYPE) (offset = 2Ch) 31 16 Reserved R-0 15 8 7 0 NUMREG Reserved R-x R-0 LEGEND: R = Read only; -x = value is implementation defined Table 11-12. MPU Type Register (MPUTYPE) Field Descriptions Bit Field 31-16 Reserved 15-8 NUMREG Value 0 Reserved. Reads return 0. Number of MPU Regions. Indicates the number of implemented MPU regions. 0 Reserved 1h 1 MPU region is implemented.
NMPU Registers www.ti.com 11.4.10 MPU Region Base Address Register (MPUREGBASE) NOTE: MPUREGBASE0-7 registers are memory-mapped to the same address. Which region register is selected for read/write access is decided by the REGION field in the MPU region number register (MPUREGNUM). Figure 11-13.
NMPU Registers www.ti.com Table 11-14. MPU Region Size and Enable Register (MPUREGSENA) Field Descriptions (continued) Bit Field 5-1 REG_SIZE Value Description MPU Region size. This field determines the size of an MPU region. Read: Returns current value of REG SIZE. Write in Privilege: Defines the size of an MPU region.
NMPU Registers www.ti.com 11.4.12 MPU Region Access Control Register (MPUREGACR) NOTE: MPUREGACR0-7 registers are memory-mapped to the same address. Which region register is selected for read/write access is decided by the REGION field in the MPU region number register (MPUREGNUM). Figure 11-15.
NMPU Registers www.ti.com 11.4.13 MPU Region Number Register (MPUREGNUM) NOTE: MPUREGBASE0-7, MPUREGSENA0-7, MPUREGACR0-7, MPUREGAM0-7, MPUREGTA07, and MPUREGMT0-7 registers are memory-mapped to just six different addresses. Which region register is selected for read/write access is decided by the REGION field in the MPU region number register (MPUREGNUM). Figure 11-16.
Chapter 12 SPNU562 – May 2014 Error Profiling Controller (EPC) This chapter describes overall functionality and how to use the Error Profiling Controller (EPC). Topic 12.1 12.2 12.3 12.4 464 ........................................................................................................................... Overview ......................................................................................................... Module Operation .............................................................
Overview www.ti.com 12.1 Overview The EPC is used as a diagnostic for functional safety purposes. The primary goal of this module is to provide a unified correctable ECC error (single bit ECC fault) profiling capability and error address cache on ECC failures in system bus memory slaves like Flash, FEE, and SRAM. The secondary goal of this module is to provide an ECC error reporting capability for bus masters which are not natively built to manage ECC error like the interconnect.
Module Operation www.ti.com Figure 12-1. EPC System Block Diagram serr_valid CPU serr_event serr_addr uerr_event ESM 32 cam_fifo_full_int serr_valid EPC IP0 serr_addr VIM 32 uerr_valid IP1 uerr_addr 32 12.2.1 Uncorrectable Fault Operation EPC will capture full 32-bit addresses of uncorrectable fault from interconnect and RAM IP modules to UERRADDR_(0,1) registers and set the corresponding uncorrectable status bit in UERRSTAT register.
Module Operation www.ti.com The 64-bit aligned address of the correctable fault from each IP FIFO is sent to the CAM to check if the correctable fault is unique or repetitive. If it is a repetitive address for the correctable fault, then the correctable fault and its address are discarded and no further indication to the CPU. If it is a unique address, then the address will be remembered in the CAM content and CAM index will be set to occupied.
How to Use EPC www.ti.com 12.3 How to Use EPC 12.3.1 Functional Mode Following steps are the recommended sequences to initialize EPC: 1. Set up correct values for SERRENA and CAMFIFO FULL ENA bits in EPCCNTRL. Setting SERRENA will enable correctable error event generation to ESM. Setting CAMFIFO FULL ENA will enable CAM full or FIFO full interrupt to the CPU. You need to set these values in according to their safety application requirement. 2.
How to Use EPC www.ti.com 12.3.2 CAM Diagnostic Mode In order to test the CAM logic and error event generation functionality, you need to diagnose the CAM at diagnostic time in their control loop. Following sequences are recommended to diagnose the CAM and error event generation: 1. Configure EPC in diagnostic mode by setting the DIAG_ENA_KEY to Ah in EPCCNTRL register. 2. Backing up the CAM content and CAM index to system RAM. 3.
EPC Control Registers www.ti.com 12.4.1 EPC REVID Register (EPCREVID) Figure 12-2. EPC REVID Register (EPCREVID) (offset = 00h) 31 30 29 28 27 16 SCHEME Reserved FUNC R-1 R-0 R-A0Ah 15 11 10 8 7 6 5 0 RTL MAJOR CUSTOM MINOR R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after synchronous reset on system reset Table 12-2. EPC REVID Register (EPCREVID) Field Descriptions Bit Field Value Description 31-30 SCHEME 1 Identification scheme 29-28 Reserved 0 Reserved.
EPC Control Registers www.ti.com 12.4.2 EPC Control Register (EPCCNTRL) Figure 12-3. EPC Control Register (EPCCNTRL) (offset = 04h) 31 25 24 23 16 Reserved CAM/FIFO_ FULL_ENA Reserved R-0 R/WP-0 R-0 15 12 11 8 7 4 3 0 Reserved DIA_ENA_KEY Reserved SERRENA R-0 R/WP-5h R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after synchronous reset on system reset Table 12-3.
EPC Control Registers www.ti.com 12.4.3 Uncorrectable Error Status Register (UERRSTAT) Figure 12-4. Uncorrectable Error Status Register (UERRSTAT) (offset = 08h) 31 16 Reserved R-0 15 2 1 0 Reserved UE1 UE0 R-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after asynchronous reset by power-on reset Table 12-4.
EPC Control Registers www.ti.com 12.4.4 EPC Error Status Register (EPCERRSTAT) Figure 12-5. EPC Error Status Register (EPCERRSTAT) (offset = 0Ch) 31 16 Reserved R-0 15 3 2 1 0 Reserved CAM_FULL BUS_ERR CAM_OVFLW R-0 R/WP-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after asynchronous reset by power-on reset Table 12-5.
EPC Control Registers www.ti.com 12.4.5 FIFO Full Status Register (FIFOFULLSTAT) Figure 12-6. FIFO Full Status Register (FIFOFULLSTAT) (offset = 10h) 31 16 Reserved R-0 15 5 4 3 2 1 0 Reserved FULL4 FULL3 FULL2 FULL1 FULL0 R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after asynchronous reset by power-on reset Table 12-6.
EPC Control Registers www.ti.com 12.4.6 IP Interface FIFO Overflow Status Register (OVRFLWSTAT) Figure 12-7. IP Interface FIFO Overflow Status Register (OVRFLWSTAT) (offset = 14h) 31 16 Reserved R-0 15 5 4 3 2 1 0 Reserved OVFL4 OVFL3 OVFL2 OVFL1 OVFL0 R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after asynchronous reset by power-on reset Table 12-7.
EPC Control Registers www.ti.com 12.4.8 Uncorrectable Error Address Register n (UERR_ADDR) Figure 12-9. Uncorrectable Error Address Register n (UERR_ADDR) (offset = 20h-24h) 31 0 UERR_ADDR R-0 LEGEND: R = Read only; -n = value after asynchronous reset on power-on reset Table 12-9. Uncorrectable Error Address Register n (UERR_ADDR) Field Descriptions Bit 31-0 Field Description UERR_ADDR Register n corresponds to uncorrectable port n.
EPC Control Registers www.ti.com 12.4.10 CAM Index Registers (CAM_INDEX[0-7]) Figure 12-11. CAM Index Registers (CAM_INDEXn) (offset = 200h-21Ch) 31 28 27 24 23 20 19 16 Reserved index n × 4 + 3 Reserved index n × 4 + 2 R-0 R/WP-5h R-0 R/WP-5h 15 12 11 8 7 4 3 0 Reserved index n × 4 + 1 Reserved index n × 4 R-0 R/WP-5h R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after synchronous reset on system reset Table 12-11.
Chapter 13 SPNU562 – May 2014 CPU Compare Module for CortexTM-R5F (CCM-R5F) This chapter describes the CPU compare module for Cortex-R5F (CCM-R5F). This device implements two instances of the Cortex-R5F CPU which are running in lockstep to detect faults which may result in unsafe operating conditions. The CCM-R5F detects faults and signals them to an error signaling module (ESM).
Overview www.ti.com 13.1 Overview Safety-critical applications require run-time detection of faults in critical components in the device such as the Central Processing Unit (CPU) and the Vectored Interrupt Controller Module (VIM). For this purpose, the CPU Compare Module for Cortex-R5F (CCM-R5F) compares the core bus outputs of two Cortex-R5F CPUs running in a 1oo1D (one-out-of-one, with diagnostics) lockstep configuration.
Module Operation www.ti.com Figure 13-1. Block Diagram PDx Outputs CPU2 to the system Outputs from CPU1 to the system PDy cpu1clk CCM-R5F 2 cycle delay CPU Bus Compare PD Inactivity Monitor Checker CPU Inactivity Monitor Compare errors ESM VIM Bus Compare Lockstep mode VIM1 Safe values (values that will force the Z l Wh[ }µµ to inactive states) CPU1 (Main CPU) VIM2 CPU2 (Checker CPU) Lockstep mode 2 cycle delay cpu2clk Inputs to CPU1 Inputs to CPU2 13.
Module Operation www.ti.com 13.2.1 CPU/VIM Output Compare Diagnostic CPU / VIM Output Compare Diagnostic can run in one of the following four operating modes: 1. Active compare lockstep mode 2. Self-test 3. Error forcing 4. Self-test error forcing The operating mode can be selected by writing a dedicated key to the key register (MKEYx) of the corresponding diagnostic.
Module Operation www.ti.com 13.2.1.2 Self-Test Mode In self-test mode, the CCM-R5F checks itself for faults. During self-test, the compare error module output signal is deactivated. Any fault detected inside the CCM-R5F will be flagged by ESM error “CCM-R5F self-test”. In self-test mode, the CCM-R5F automatically generates test patterns to look for any hardware faults.
Module Operation www.ti.com 13.2.1.2.2 Compare Mismatch Test During the Compare Mismatch Test, the number of test patterns is equal to twice the number of CPU output signals to compare in lockstep mode. An all 1s vector is applied to the CCM-R5F’s CPU1 / VIM1 input port and the same pattern is also applied to the CCM-R5F’s CPU2 /VIM2 input port but with one bit flipped starting from signal position 0.
Module Operation www.ti.com 13.2.1.3 Error Forcing Mode In error forcing mode, a test pattern is applied to the CPU / VIM related inputs of the CCM-R5F compare logic to force an error in the compare error output signal of the compare unit. Depending if error forcing mode is applied to the CPU Output Compare Diagnostic or VIM Output Compare Diagnostic, the ESM error flag “CCM-R5F - CPU compare” or “CCM-R5F - VIM compare” is expected after the error forcing mode completes.
Module Operation www.ti.com 13.2.2 CPU Input Inversion Diagnostic There is another way to intentionally create a mismatch between the two CPUs' outputs as a diagnostic test to self-test the CCM-R5F's CPU Output Compare Diagnostic block. Before the CPU1's outputs are taken to the CCM-R5F, eight of the output signals are first exclusive-ORed bitwise with the 8-bit POLARITYINVERT register. After reset, the default value of the POLARITYINVERT register is all zeros.
Module Operation www.ti.com 13.2.3 Checker CPU Inactivity Monitor Similar to the CPU / VIM Output Compare Diagnostic, the Checker CPU Inactivity Monitor can also run in one of the following four operating modes: 1. Active compare 2. Self-test 3. Error forcing 4. Self-test error forcing The operating mode can be selected by writing a dedicated key to the key register (MKEY3). 13.2.3.1 Active Compare Mode This is the default mode on start-up.
Module Operation www.ti.com 13.2.3.2.1 Compare Match Test Since the comparison is done against the clamped values, and all compared signals are clamped to zero, only one test pattern is applied for the compare match test. A pattern of all-zeros are applied for the compare match test. The test will take one cycle. If the compare unit produces a compare mismatch then the self-test error flag is set, the self-test error signal is generated, and the Compare Match Test is terminated. 13.2.3.2.
Module Operation www.ti.com 13.2.4 Power Domain Inactivity Monitor The Power Domain Inactivity Monitor is very similar to the Checker CPU Inactivity Monitor in concept. When a power domain is turned off, its outputs are isolated from the rest of the system. The outputs are clamped to inactive safe values. Depending on the signals, the clamp value of a signal may be 0 or 1. Some bus masters may be residing in the turned off power domains.
Control Registers www.ti.com 13.3.1 CCM-R5F Status Register 1 (CCMSR1) The contents of this register should be interpreted in context of what test was selected. That is, what mode is CCM operating. Figure 13-3.
Control Registers www.ti.com 13.3.2 CCM-R5F Key Register 1 (CCMKEYR1) Figure 13-4. CCM-R5F Key Register 1 (CCMKEYR1) (Offset = 04h) 31 16 Reserved R-0 15 4 3 0 Reserved MKEY1 R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privileged mode only; -n = value after reset Table 13-9. CCM-R5F Key Register 1 (CCMKEYR1) Field Descriptions Bit Field 31-4 Reserved 3-0 MKEY1 Value 0 Description Reads return to zeros and writes have no effect.
Control Registers www.ti.com 13.3.3 CCM-R5F Status Register 2 (CCMSR2) Figure 13-5. CCM-R5F Status Register 2 (CCMSR2) (Offset = 08h) 31 17 15 16 Reserved CPME2 R-0 R/W1PC-0 9 8 7 2 1 0 Reserved STC2 Reserved STET2 STE2 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in Privileged mode only; -n = value after reset Table 13-10.
Control Registers www.ti.com 13.3.4 CCM-R5F Key Register 2 (CCMKEYR2) Figure 13-6. CCM-R5F Key Register 2 (CCMKEYR2) (Offset = 0Ch) 31 16 Reserved R-0 15 4 3 0 Reserved MKEY2 R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privileged mode only; -n = value after reset Table 13-11. CCM-R5F Key Register 2 (CCMKEYR2) Field Descriptions Bit Field 31-4 Reserved 3-0 MKEY2 Value 0 Description Reads return to zeros and writes have no effect.
Control Registers www.ti.com 13.3.5 CCM-R5F Status Register 3 (CCMSR3) Figure 13-7. CCM-R5F Status Register 3 (CCMSR3) (Offset = 10h) 31 17 15 16 Reserved CPME3 R-0 R/W1PC-0 9 8 7 2 1 0 Reserved STC3 Reserved STET3 STE3 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in Privileged mode only; -n = value after reset Table 13-12.
Control Registers www.ti.com 13.3.6 CCM-R5F Key Register 3 (CCMKEYR3) Figure 13-8. CCM-R5F Key Register 3 (CCMKEYR3) (Offset = 14h) 31 16 Reserved R-0 15 4 3 0 Reserved MKEY3 R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privileged mode only; -n = value after reset Table 13-13. CCM-R5F Key Register 2 (CCMKEYR2) Field Descriptions Bit Field Value 31-4 Reserved 3-0 MKEY3 0 Description Reads return to zeros and writes have no effect.
Control Registers www.ti.com 13.3.8 CCM-R5F Status Register 4 (CCMSR4) Figure 13-10. CCM-R5F Status Register 4 (CCMSR4) (Offset = 1Ch) 31 17 15 16 Reserved CPME4 R-0 R/W1PC-0 9 8 7 2 1 0 Reserved STC4 Reserved STET4 STE4 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in Privileged mode only; -n = value after reset Table 13-15.
Control Registers www.ti.com 13.3.9 CCM-R5F Key Register 4 (CCMKEYR4) Figure 13-11. CCM-R5F Key Register 4 (CCMKEYR4) (Offset = 20h) 31 16 Reserved R-0 15 4 3 0 Reserved MKEY4 R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privileged mode only; -n = value after reset Table 13-16. CCM-R5F Key Register 4 (CCMKEYR4) Field Descriptions Bit Field 31-4 Reserved 3-0 MKEY4 Value 0 Description Reads return to zeros and writes have no effect.
Control Registers www.ti.com 13.3.10 CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0) Figure 13-12. CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0) (Offset = 24h) 31 16 Reserved R-0 15 6 5 4 3 2 1 0 Reserved DMM_TRANS HTU2_TRANS Reserved R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 13-17.
Chapter 14 SPNU562 – May 2014 Oscillator and PLL This chapter describes the oscillator and PLL clock source paths for the device. Topic 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 498 ........................................................................................................................... Introduction ..................................................................................................... Quick Start..............................................................................
Introduction www.ti.com 14.1 Introduction The oscillator macro will pass a signal driven into the OSCIN pin to clock source 0 that is the device default clock source on reset. When a crystal or resonator with appropriate load circuitry is connected to OSCIN and OSCOUT, the oscillator macro drives the crystal/resonator to generate the input waveform. In addition to being directly usable as clock source 0, the oscillator clock is the input to the PLL.
Quick Start www.ti.com 14.2 Quick Start The purpose of this section is to provide an overview of how to configure the oscillator and PLL clock paths on power-up. More detailed descriptions are presented in later sections. Figure 14-1 shows the oscillator and PLL clock paths. While power-on reset is asserted (low), the oscillator and low power oscillator (LPO) are enabled and start-up by default.
Oscillator www.ti.com 14.3 Oscillator The clock generation path through the PLL begins with the oscillator. The oscillator consists of three separate pads -- OSCIN, OSCOUT, and Kelvin_GND (see Figure 14-2). The oscillator is responsible for two independent functions: 1. The oscillator is responsible for generating positive feedback in the external crystal/resonator with appropriate load and tank circuitry. At start-up, the oscillator amplifies random noise.
Oscillator www.ti.com 14.3.1 Oscillator Implementation The oscillator operates at 3.3V and uses a constant current source to drive current onto the OSCOUT node. An internal transistor shunts the current (and current from the external circuitry) to GND. This current steering drives the voltage waveform on OSCOUT. Figure 14-3. Oscillator Implementation R OSCOUT OSCIN 14.3.2 Oscillator Enable The oscillator is enabled asynchronously when nPORRST is low.
Low Power Oscillator and Clock Detect (LPOCLKDET) www.ti.com 14.4 Low Power Oscillator and Clock Detect (LPOCLKDET) The Low Power Oscillator (LPO) is comprised of two oscillators -- HF LPO and LF LPO -- in a single macro. The low power oscillator and clock detect (LPOCLKDET) uses a relaxation oscillator to generate an internal clock whose frequency is NOT tightly controlled. This frequency is used to monitor the oscillator input frequency and is also available as an independent clock source in the GCM.
Low Power Oscillator and Clock Detect (LPOCLKDET) www.ti.com The automatic switch-over from oscillator to HF LPO allows the application to execute at a reduced frequency and respond to a problem with the external crystal/resonator.
Low Power Oscillator and Clock Detect (LPOCLKDET) www.ti.com 14.4.5 LPOCLKDET Disable 14.4.5.1 Disable Clock Detect It is possible to disable the clock detect circuitry. For protection, this clock detect disable employs a 2-bit key: • RANGE DET ENA SSET (CLKTEST.24) must be set to 1 • RANGE DET CTRL (CLKTEST.25) must be cleared to 0 In this case, the LPO HF and LF clocks are still active but the clock detect circuitry is disabled.
PLL www.ti.com 14.5 PLL The following bit fields from PLLCTL1 and PLLCTL2 configure the PLL: • REFCLKDIV[5:0] • PLLMUL[15:0] • ODPLL[2:0] • PLLDIV[4:0] • SPR_AMOUNT[8:0] • SPREADINGRATE[8:0] • FMENA The PLL is responsible for synthesizing an output frequency from the input clock (from the oscillator); Figure 14-4 shows a simple block diagram of the PLL. The FM-PLL divides the reference input for a lower frequency input into the PLL (fINTCLK = fCLKIN/NR).
PLL www.ti.com Table 14-2. PLL Value Encoding PLL NR = REFCLKDIV [5...0] + 1 NR (4) Non-modulated: NF = ( PLLMUL [15...0] + 1 << 8) 256 (5) Modulated: NF = NF ( PLLMUL [15...0] + MULMOD [8...0] + 1 << 8) 256 NV = NV (6) ( S P R _ A M O U N T [ 8 ... 0 ] + 1) 2048 (7) NS NS = SPRRATE [8...0] + 1 (8) OD OD = ODPLL[2...
PLL www.ti.com 14.5.1 Modulation Optionally, the frequency can be modulated, that is, a controlled jitter is introduced onto the baseline frequency of the PLL. This modulation mechanism is not shown in Figure 14-4.
PLL www.ti.com 14.5.2 PLL Output Control The outputs from the PLL are the output clock, slip signals and VALID. • RFSLIP -- the RFSLIP signal indicates that the Output CLK is running too fast relative to INTCLK and sets a RFSLIP status flag in the Global Status Register (GLBSTAT), of the System and Peripheral Control Registers, if the slip signal is active during normal PLL operation; the RFSLIP flag is masked off while the PLL is not active and during the PLL’s lock period.
PLL www.ti.com 14.5.2.2 PLL Disable The clock sources (for example, OSC, PLL) are disabled by setting the appropriate bit in the Clock Source Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Set Register (CSDISSET) of the System and Peripheral Control Registers. These bit allow the clock to disable but do not force the behavior until the clock is no longer used as the source for a clock domain (for example, GCLK, VCLK, VCLK2, RTICLK).
PLL www.ti.com 14.5.2.4 Changing the PLL Operating Point While the PLL is Active Once the valid bit (CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT) of the System and Peripheral Control Registers) is set, software may change values to the PLL. If the change of values results in a small percentage change to the VCO frequency (∆fOutputCLK < 0.1 × fOutputCLK), then these changes can be done on-the-fly.
PLL www.ti.com 14.5.3 Behavior on PLL Fail The PLL allows flexible response to a PLL failure (slip). Like the oscillator, the PLL clock is configured by default to automatically switch-over to the oscillator in case of a PLL slip. (In this case, the oscillator sources GCM clock source 1 as well as GCM clock source 0. Also, if the oscillator fails, LPO HF is sourced to both GCM clock sources 0 and 1.) The PLL slip outputs indicate that the PLL is running either too fast or too slow.
PLL www.ti.com 14.5.4 Recovery from a PLL Failure If PLL1 fails, the PLL’s slip causes the valid flag to be locked and causes the clock source into GCM clock source 1 to shift from the PLL to the oscillator. The RFSLIP or FBSLIP status flags in the Global Status Register (GLBSTAT) of the System and Peripheral Control Registers are also set. PLL1 may be reenabled (though if the failure was caused by a hard-fault, the re-enable will fail) through the following procedure: 1.
PLL www.ti.com 14.5.5 PLL Modulation Depth Measurement The PLL contains a circuit for estimating the depth of the modulation. The circuit counts clock edges over a fixed window of the modulation waveform (SSW_CAPTURE_COUNT in SSWPLL2) and clock edges over the entire waveform (SSW_CLKOUT_COUNT in SSWPLL3). The capture ends after a predetermined number of clock edges in SSW_CLKOUT_COUNTER as set in TAP_COUNTER_DIS. There are 2 × NR windows per modulation waveform.
Control Registers www.ti.com 14.6 Control Registers The clock module has two registers (PLLCTL1 and PLLCTL2) located within the System and Peripheral Control Registers, plus it has four bits located in other System and Peripheral Control Registers. The FM-PLL is off at power-on.
Control Registers www.ti.com 14.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1) Figure 14-6 illustrates this register and Table 14-6 provides the bit descriptions. This register applies to PLL1, but does not apply to PLL2. Figure 14-6.
Control Registers www.ti.com Table 14-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions (continued) Bit Field 3-1 TAP_COUNTER_DIS 0 Value EXT_COUNTER_EN Description The value in this register is used to program a particular bit in CLKOUT counter. When that particular bit in CLKOUT counter becomes 1, then both the CLKOUT counter and the CAPTURE counter will stop counting when EXT_COUNTER_EN = 0. When EXT_COUNTER_EN = 1, this bit field is not used.
Control Registers www.ti.com 14.6.3 SSW PLL BIST Control Register 3 (SSWPLL3) This is observation register used to log counter value for CLKOUT counter inside PLL wrapper. The SSWPLL3 register is shown in Figure 14-8 and described in Table 14-8. This register applies to PLL1, but does not apply to PLL2. Figure 14-8. SSW PLL BIST Control Register 3 (SSWPLL3) [offset = 2Ch] 31 16 SSW_CLKOUT_COUNT R-0 15 0 SSW_CLKOUT_COUNT R-0 LEGEND: R = Read only; -n = value after reset Table 14-8.
Phase-Locked Loop Theory of Operation www.ti.com 14.7 Phase-Locked Loop Theory of Operation The PLL block consists of six logical sub-blocks: • Phase-Frequency Detector (PFD) • Charge Pump (CP) • Loop Filter (LF) • Voltage-Controlled Oscillator (VCO) • Frequency Modulation • Slip Detector Figure 14-9 illustrates the sub-blocks in a basic PLL circuit. The VCO adjusts its frequency until the two signals into the PFD have the same phase and frequency.
Phase-Locked Loop Theory of Operation www.ti.com The width of the up pulse and the down pulse depends on the difference in phase between the two inputs. For example, when the reference input leads the feedback input by 10 ns, then an up pulse of approximately 10 ns is generated (see Figure 14-10). On the other hand, when the reference input lags the feedback input by 10 ns, then a down pulse of approximately 10 ns is generated.
Phase-Locked Loop Theory of Operation www.ti.com 14.7.4 Frequency Modulation The output clock of the PLL changes frequency in a controlled way, centered around the unmodulated output frequency. The modulation block directly modulates the VCO frequency at the loop filter, and creates the triangular frequency modulation (see Figure 14-12). Figure 14-12. Frequency versus Time Modulation Period (1/fs) Depth f0 Modulation Frequency (MHz) f0+n% f0-n% Time (Ps) 14.
Programming Example www.ti.com 5. Compute the divider value NV: D ep th = 0 .5 NV NS N V 20 = ´ = ´ 100 NF 2 90 2 (20) NV = 0.045 6. If it is important to maintain the same average frequency in modulation as in non-modulation, either NF should be modified OR program the MULMOD bit field. The modulation fields create a multiplier offset equal to: DNF = NV ´ NS 2 (21) If using MULMOD[8:0], then: MULMOD [8 ...0 ] NV ´ NS 0 .045 ´ 20 = = 256 2 2 0 . 045 ´ 20 M U LM O D [8 ... 0 ] = ´ 256 = 115 .
Chapter 15 SPNU562 – May 2014 Dual-Clock Comparator (DCC) Module This chapter describes the dual-clock comparator (DCC) module. Topic 15.1 15.2 15.3 15.4 ........................................................................................................................... Introduction ..................................................................................................... Module Operation .............................................................................................
Introduction www.ti.com 15.1 Introduction The primary purpose of a DCC module is to measure the frequency of a clock signal using a second known clock signal as a reference. This capability can be used to ensure the correct frequency range for several different device clock sources, thereby enhancing the system safety metrics. 15.1.
Module Operation www.ti.com 15.2 Module Operation As shown in Figure 15-1, the DCC contains two counters – counter0 and counter1, which are driven by two signals – clock0 and clock1. The application programs the seed values for both these counters. The application also configures the tolerance window time by configuring the valid counter for clock0. Counter0 and counter1 both start counting simultaneously once the DCC is enabled.
Module Operation www.ti.com Figure 15-2. Counter Relationship (no error) Error Count0 Count0 Valid0 Valid0 Count1 Count1 Clock0 0 Clock1 0 time reload Clock1 must expire in this window, otherwise signal an error reload Figure 15-3.
Module Operation www.ti.com Figure 15-4. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting Error Count0 Clock0 Valid0 0 Count1 Clock1 0 time reload Counter1 reaches 0 before Counter0 reaches 0 Figure 15-5. Clock1 Not Present - Results in an Error and Stops Counting Error Count0 Clock0 Valid0 0 Count1 Count1 does not count down due to an inactive clock 1 Clock1 0 time reload An error signal is generated since Count1 does not reach 0 in the Valid0 window.
Module Operation www.ti.com Figure 15-6. Clock0 Not Present - Results in an Error and Stops Counting Error Count0 Count0 and Valid 0 do not count down due to an inactive clock 0 Clock0 Valid0 Count1 Clock1 reload time Counter1 reaches 0 at the right time, but since Clock0 is not running, Valid0 hasn’t started, thus an error is generated. 15.2.1 Single-Shot Measurement Mode The DCC module can be programmed to count down one time by enabling the single-shot mode.
Clock Source Selection for Counter0 and Counter1 www.ti.com • • The DCC error interrupt service routine can then check the value of counter1 when the error was generated. Suppose that the counter1 now reads 1044575. This means that counter1 has counted 1048575 - 1044575, or 4000 cycles within the 500µs measurement period. This means that the average frequency of the HF LPO over this 500µs period was 4000 cycles / 500µs, or 8MHz.
DCC Control Registers www.ti.com 15.4 DCC Control Registers This section describes the dual-clock comparator (DCC) module control and status registers. The registers support 8-bit, 16-bit or 32-bit writes and are aligned on a word (32-bit) boundary. Table 15-1 shows address offsets from the module base address. The base address for the control registers is FFFF EC00h for DCC1 and FFFF F400h for DCC2. Table 15-1.
DCC Control Registers www.ti.com 15.4.1 DCC Global Control Register (DCCGCTRL) Figure 15-7 and Table 15-2 describe the DCC Global Control register. Figure 15-7. DCC Control Register (DCCGCTRL) [offset = 00] 31 16 Reserved R-0 15 12 11 8 7 4 3 0 DONE INT ENA SINGLE SHOT ERR ENA DCC ENA R/WP-5h R/WP-5h R/WP-5h R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 15-2.
DCC Control Registers www.ti.com 15.4.2 DCC Revision Id Register (DCCREV) Figure 15-8 and Table 15-3 describe the DCC Revision Id register. Figure 15-8. DCC Revision Id Register (DCCREV) [offset = 4h] 31 30 29 28 27 16 SCHEME Reserved FUNC R-01 R-0 R-0 15 11 10 8 7 6 5 0 RTL MAJOR CUSTOM MINOR R-0 R-2h R-0 R-4h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15-3.
DCC Control Registers www.ti.com 15.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) Figure 15-10 and Table 15-5 describe the DCC Valid0 Seed register. Figure 15-10. DCC Valid0 Seed Register (DCCVALID0SEED) [offset = Ch] 31 16 Reserved R-0 15 0 VALID0 SEED R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 15-5.
DCC Control Registers www.ti.com 15.4.6 DCC Status Register (DCCSTAT) Figure 15-7 and Table 15-2 describe the DCC Status register. Figure 15-12. DCC Status Register (DCCSTAT) [offset = 14h] 31 16 Reserved R-0 15 1 0 Reserved 2 DONE ERR R-0 R/WPC-0 R/WPC-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in privileged mode only; -n = value after reset Table 15-7.
DCC Control Registers www.ti.com 15.4.7 DCC Counter0 Value Register (DCCCNT0) Figure 15-13 and Table 15-8 describe the DCC Counter0 Value register. Figure 15-13. DCC Counter0 Value Register (DCCCNT0) [offset = 18h] 31 20 19 16 Reserved COUNT0 R-0 R-0 15 0 COUNT0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15-8. DCC Counter0 Seed Register (DCCCNT0) Field Descriptions Bit Field 31-20 Reserved 19-0 COUNT0 Value 0 Description Read returns 0.
DCC Control Registers www.ti.com 15.4.8 DCC Valid0 Value Register (DCCVALID0) Figure 15-14 and Table 15-9 describe the DCC Valid0 Value register. Figure 15-14. DCC Valid0 Value Register (DCCVALID0) [offset = 1Ch] 31 16 Reserved R-0 15 0 VALID0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15-9. DCC Valid0 Value Register (DCCVALID0) Field Descriptions Bit Field 31-16 Reserved 15-0 VALID0 Value 0 Description Read returns 0. Writes have no effect.
DCC Control Registers www.ti.com 15.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) Figure 15-15 and Table 15-10 describe the DCC Counter1 Value register. Figure 15-16. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) [offset = 24h] 31 16 Reserved R-0 15 12 11 4 3 0 KEY Reserved CNT1 CLKSRC R/WP-5h R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 15-11.
Chapter 16 SPNU562 – May 2014 Error Signaling Module (ESM) This chapter provides the details of the error signaling module (ESM) which aggregates device errors and provides internal and external error response based on error severity. Topic 16.1 16.2 16.3 16.4 538 ........................................................................................................................... Overview .........................................................................................................
Overview www.ti.com 16.1 Overview The Error Signaling Module (ESM) collects and reports the various error conditions on the microcontroller. The error condition is categorized based on a severity level. Error response is then generated based on the category of the error. Possible error responses include a low priority interrupt, high priority interrupt, and an external pin action. 16.1.
Overview www.ti.com Table 16-1. ESM Interrupt and ERROR Pin Behavior Error Group Interrupt Generated Interrupt Priority ERROR Pin Response Generated 1 configurable interrupt configurable priority configurable output generation 2 interrupt generated high priority output generated 3 no interrupt NA output generated Figure 16-2 and Figure 16-3 show the interrupt response handling and ERROR pin response handling with register configuration.
Module Operation www.ti.com 16.2 Module Operation This device has 160 error channels, divided into 3 different error groups. Please refer to the device datasheet for ESM channel assignment details. The ESM module has error flags for each error channel. The error status registers ESMSR1, ESMSR4, ESMSR7, ESMSR2, ESMSR3 provide status information on a pending error of Group1 (Channel 0-31), Group1 (Channel 32-63), Group1 (Channel 64-95), Group2, and Group3, respectively.
Module Operation www.ti.com 16.2.2 ERROR Pin Timing The ERROR pin is an active low function. The state of the pin is also readable from ERROR Pin Status Register (ESMEPSR). A warm reset (RST) does not affect the state of the pin. The pin is in a highimpedance state during power-on reset. Once the ESM module drives the ERROR pin low, it remains in this state for the time specified by the Low-Time Counter Preload register (LTCPR).
Module Operation www.ti.com Example 4: ESM detects a failure and drives the ERROR pin low. Another failure occurs within the time the pin stays low. In this case, the low time counter will be reset when the other failure occurs. In other words, tERROR_low should be counted from whenever the most recent failure occurs. Figure 16-7.
Recommended Programming Procedure www.ti.com 16.3 Recommended Programming Procedure During the initialization stage, the application code should follow the recommendations in Figure 16-10 to initialize the ESM. Once an error occurs, it can trigger an interrupt, ERROR pin outputs low depending on the ESM settings. Once the ERROR pin outputs low, a power on reset or a write of 0x5 to ESMEKR is required to release the ESM back to normal state.
ESM Control Registers www.ti.com 16.4 ESM Control Registers Table 16-2 lists the ESM registers. Each register begins on a 32-bit word boundary. The registers support 8-, 16-, and 32-bit accesses. The base address for the control registers is FFFF F500h. Table 16-2. ESM Control Registers Offset Acronym Register Description 00h ESMEEPAPR1 ESM Enable ERROR Pin Action/Response Register 1 Section 16.4.1 Section 04h ESMDEPAPR1 ESM Disable ERROR Pin Action/Response Register 1 Section 16.4.
ESM Control Registers www.ti.com 16.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) This register is dedicated for Group1 Channel[31:0]. Figure 16-11. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) [offset = 00h] 31 16 IEPSET[31:16] R/WP-0 15 0 IEPSET[15:0] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-3.
ESM Control Registers www.ti.com 16.4.3 ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) This register is dedicated for Group1 Channel[31:0]. Figure 16-13. ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) [offset = 08h] 31 16 INTENSET[31:16] R/WP-0 15 0 INTENSET[15:0] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-5.
ESM Control Registers www.ti.com 16.4.5 ESM Interrupt Level Set/Status Register 1 (ESMILSR1) This register is dedicated for Group1 Channel[31:0]. Figure 16-15. ESM Interrupt Level Set/Status Register 1 (ESMILSR1) [offset = 10h] 31 16 INTLVLSET[31:16] R/WP-0 15 0 INTLVLSET[15:0] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-7.
ESM Control Registers www.ti.com 16.4.7 ESM Status Register 1 (ESMSR1) This register is dedicated for Group1 Channel[31:0]. Note that the ESMSR1 status register will get updated if an error condition occurs, regardless if the corresponding interrupt enable flag is set or not. Figure 16-17.
ESM Control Registers www.ti.com 16.4.9 ESM Status Register 3 (ESMSR3) This register is dedicated for Group3. Figure 16-19. ESM Status Register 3 (ESMSR3) [offset = 20h] 31 16 ESF3[31:0] R/WPC-X/0 15 0 ESF3[15:0] R/WPC-X/0 LEGEND: R/W = Read/Write; R = Read; C = Clear; WP = Write in privileged mode only; -n = value after reset/PORRST; X = Value unchanged Table 16-11. ESM Status Register 3 (ESMSR3) Field Descriptions Bit Field 31-0 ESF3 Value Description Error Status Flag.
ESM Control Registers www.ti.com 16.4.11 ESM Interrupt Offset High Register (ESMIOFFHR) Figure 16-21. ESM Interrupt Offset High Register (ESMIOFFHR) [offset = 28h] 31 16 Reserved R-0 15 8 7 0 Reserved INTOFFH R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 16-13. ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions Bit Field 31-8 Reserved 7-0 INTOFFH Value 0 Description Read returns 0. Writes have no effect. Offset High Level Interrupt.
ESM Control Registers www.ti.com 16.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR) Figure 16-22. ESM Interrupt Offset Low Register (ESMIOFFLR) [offset = 2Ch] 31 16 Reserved R-0 15 8 7 0 Reserved INTOFFL R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 16-14. ESM Interrupt Offset Low Register (ESMIOFFLR) Field Descriptions Bit Field 31-8 Reserved 7-0 INTOFFL Value 0 Description Read returns 0. Writes have no effect. Offset Low Level Interrupt.
ESM Control Registers www.ti.com 16.4.13 ESM Low-Time Counter Register (ESMLTCR) Figure 16-23. ESM Low-Time Counter Register (ESMLTCR) [offset = 30h] 31 16 Reserved R-0 15 0 LTC R-3FFFh LEGEND: R = Read; -n = value after reset Table 16-15. ESM Low-Time Counter Register (ESMLTCR) Field Descriptions Bit Field Value 31-16 Reserved 15-0 LTC 0 Description Read returns 0. Writes have no effect. ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin.
ESM Control Registers www.ti.com 16.4.15 ESM Error Key Register (ESMEKR) Figure 16-25. ESM Error Key Register (ESMEKR) [offset = 38h] 31 16 Reserved R-0 15 4 3 0 Reserved EKEY R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-17. ESM Error Key Register (ESMEKR) Field Descriptions Bit Field 31-4 Reserved 3-0 EKEY Value Description 0 Read returns 0. Writes have no effect. Error Key.
ESM Control Registers www.ti.com 16.4.17 ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) This register is dedicated for Group1 Channel[63:32]. Figure 16-27. ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) [offset = 40h] 31 16 IEPSET[63:48] R/WP-0 15 0 IEPSET[47:32] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-19.
ESM Control Registers www.ti.com 16.4.19 ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) This register is dedicated for Group1 Channel[63:32]. Figure 16-29. ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) [offset = 48h] 31 16 INTENSET[63:48] R/WP-0 15 0 INTENSET[47:32] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-21.
ESM Control Registers www.ti.com 16.4.21 ESM Interrupt Level Set/Status Register 4 (ESMILSR4) This register is dedicated for Group1 Channel[63:32]. Figure 16-31. ESM Interrupt Level Set/Status Register 4 (ESMILSR4) [offset = 50h] 31 16 INTLVLSET[63:48] R/WP-0 15 0 INTLVLSET[47:32] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-23.
ESM Control Registers www.ti.com 16.4.23 ESM Status Register 4 (ESMSR4) This register is dedicated for Group1 Channel[63:32]. Figure 16-33. ESM Status Register 4 (ESMSR4) [offset = 58h] 31 16 ESF[63:48] R/WPC-X/0 15 0 ESF[47:32] R/WPC-X/0 LEGEND: R/W = Read/Write; R = Read; C = Clear; WP = Write in privileged mode only; -n = value after reset/PORRST; X = Value unchanged Table 16-25. ESM Status Register 4 (ESMSR4) Field Descriptions Bit Field 63-32 ESF Value Description Error Status Flag.
ESM Control Registers www.ti.com 16.4.24 ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) This register is dedicated for Group1 Channel[95:64]. Figure 16-34. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) [offset = 80h] 31 16 IEPSET[95:80] R/WP-0 15 0 IEPSET[79:64] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-26.
ESM Control Registers www.ti.com 16.4.26 ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) This register is dedicated for Group1 Channel[95:64]. Figure 16-36. ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) [offset = 88h] 31 16 INTENSET[95:80] R/WP-0 15 0 INTENSET[79:64] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-28.
ESM Control Registers www.ti.com 16.4.28 ESM Interrupt Level Set/Status Register 7 (ESMILSR7) This register is dedicated for Group1 Channel[95:64]. Figure 16-38. ESM Interrupt Level Set/Status Register 7 (ESMILSR7) [offset = 90h] 31 16 INTLVLSET[95:80] R/WP-0 15 0 INTLVLSET[79:64] R/WP-0 LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset Table 16-30.
ESM Control Registers www.ti.com 16.4.30 ESM Status Register 7 (ESMSR7) This register is dedicated for Group1 Channel[95:64]. Figure 16-40. ESM Status Register 7 (ESMSR7) [offset = 98h] 31 16 ESF[95:80] R/WPC-X/0 15 0 ESF[79:64] R/WPC-X/0 LEGEND: R/W = Read/Write; R = Read; C = Clear; WP = Write in privileged mode only; -n = value after reset/PORRST; X = Value unchanged Table 16-32. ESM Status Register 7 (ESMSR7) Field Descriptions Bit Field 95-64 ESF Value Description Error Status Flag.
Chapter 17 SPNU562 – May 2014 Real-Time Interrupt (RTI) Module This chapter describes the functionality of the real-time interrupt (RTI) module. The RTI is designed as an operating system timer to support a real time operating system (RTOS). NOTE: This chapter describes a superset implementation of the RTI module that includes features and functionality related to DMA, and Timbase control. These features are dependent on the device-specific feature content.
Overview www.ti.com 17.1 Overview The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the timebases needed for scheduling in the operating system. The timers also allow you to benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the values. 17.1.
Module Operation www.ti.com 17.2 Module Operation Figure 17-1 illustrates the high level block diagram of the RTI module. The RTI module has two independent counter blocks for generating different timebases: counter block 0 and counter block 1. A compare unit compares the counters with programmable values and generates four independent interrupt or DMA requests on compare matches. Each of the compare registers can be programmed to be compared to either counter block 0 or counter block 1.
Module Operation www.ti.com Figure 17-2.
Module Operation www.ti.com 17.2.1.1 Counter and Capture Read Consistency Portions of the device internal databus is 32-bits wide. If the application wants to read the 64-bit counters or the 64-bit capture values, a certain order of 32-bit read operations needs to be followed. This is to prevent one counter incrementing in between the two separate read operations to both counters. Reading the Counters The free running counter (RTIFRCx) must be read first.
Module Operation www.ti.com Figure 17-3.
Module Operation www.ti.com Figure 17-4. Timebase Control RTIUC0 RTIFRC0 Control RTIGCTRL 31 Increment by 1 NTU0 NTU1 Control RTITBCTRL 0 Timebase Low Compare RTITBLCOMP NTU edge detect ≥ 31 0 Control Timebase High Compare RTITBCTRL RTITBHCOMP ≤ Control Timebase Interrupt TBINT RTITBCTRL 17.2.4.
Module Operation www.ti.com 17.2.4.2 Switching from Internal Source to External Source If the application switches from an internal source to an external source, the two signals must be synchronized (see Figure 17-6). The synchronization will occur when the TBEXT bit is set. RTIUC0 will be reset and the edge detection circuit will be active for one (RTICPUC0 + RTITBHCOMP) period or until an edge is detected.
Module Operation www.ti.com Figure 17-7. Missing NTUx Signal Example RTIUC0 RTICPUC0 UC0 reset by NTU edge time switch to internal timebase UC0 reset by CPUC0 compare match missing NTU pulse NTUx 17.2.5 Digital Watchdog (DWD) The digital watchdog (DWD) is an optional safety diagnostic which can detect a runaway CPU and generate either a reset or NMI (non-maskable interrupt) response.
Module Operation www.ti.com 17.2.5.1 Digital Watchdog (DWD) The DWD is disabled by default. If it should be used, it must be enabled by writing a 32-bit value, which is the inverted value of the hardwired code in the module, to the RTIDWDCTRL register. NOTE: Once the DWD is enabled, it cannot be disabled except by system reset or power on reset.
Module Operation www.ti.com service the watchdog by writing the correct sequence in the watchdog key register. This service will cause the watchdog counter to get reloaded from the preload value and start counting down. If the NMI handler does not service the watchdog in time, it could count down all the way to zero and wrap around. If the NMI Handler does not service the watchdog in time, the NMI gets generated continuously, each time the counter counts to '0'.
Module Operation www.ti.com 17.2.6 Low Power Modes Low power modes allow the trade off of the current used during low power versus functionality and fast wakeup response. All low power modes have the following characteristics: • CPU and system clocks are disabled. • Flash banks and pump are in sleep mode. • All peripheral modules are in low power modes and the clocks are disabled (exceptions to this may occur and would be documented in the specific device data sheet).
Control Registers www.ti.com 17.3 Control Registers Table 17-1 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The offset is relative to the associated peripheral select. See the following sections for detailed descriptions of the registers. The base address for the control registers is FFFF FC00h. The address locations not listed are reserved. Table 17-1.
Control Registers www.ti.com NOTE: Writes to Reserved registers may clear the pending RTI interrupt. 17.3.1 RTI Global Control Register (RTIGCTRL) The global control register starts/stops the counters and selects the signal compared with the timebase control circuit. This register is shown in Figure 17-12 and described in Table 17-2. Figure 17-12.
Control Registers www.ti.com 17.3.2 RTI Timebase Control Register (RTITBCTRL) The timebase control register selects if the free running counter 0 is incremented by RTICLK or NTU. This register is shown in Figure 17-13 and described in Table 17-3. Figure 17-13. RTI Timebase Control Register (RTITBCTRL) [offset = 04h] 31 8 Reserved R-0 7 1 0 Reserved 2 INC TBEXT R-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-3.
Control Registers www.ti.com 17.3.3 RTI Capture Control Register (RTICAPCTRL) The capture control register controls the capture source for the counters. This register is shown in Figure 17-14 and described in Table 17-4. Figure 17-14. RTI Capture Control Register (RTICAPCTRL) [offset = 08h] 31 8 Reserved R-0 7 1 0 Reserved 2 CAPCNTR1 CAPCNTR0 R-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-4.
Control Registers www.ti.com 17.3.4 RTI Compare Control Register (RTICOMPCTRL) The compare control register controls the source for the compare registers. This register is shown in Figure 17-15 and described in Table 17-5. Figure 17-15.
Control Registers www.ti.com 17.3.5 RTI Free Running Counter 0 Register (RTIFRC0) The free running counter 0 register holds the current value of free running counter 0. This register is shown in Figure 17-16 and described in Table 17-6. Figure 17-16. RTI Free Running Counter 0 Register (RTIFRC0) [offset = 10h] 31 16 FRC0 R/WP-0 15 0 FRC0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-6.
Control Registers www.ti.com 17.3.7 RTI Compare Up Counter 0 Register (RTICPUC0) The compare up counter 0 register holds the value to be compared with prescale counter 0 (RTIUC0). This register is shown in Figure 17-18 and described in Table 17-8. Figure 17-18. RTI Compare Up Counter 0 Register (RTICPUC0) [offset = 18h] 31 16 CPUC0 R/W-0 15 0 CPUC0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17-8.
Control Registers www.ti.com 17.3.9 RTI Capture Up Counter 0 Register (RTICAUC0) The capture up counter 0 register holds the current value of prescale counter 0 on external events. This register is shown in Figure 17-20 and described in Table 17-10. Figure 17-20. RTI Capture Up Counter 0 Register (RTICAUC0) [offset = 24h] 31 16 CAUC0 R-0 15 0 CAUC0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17-10.
Control Registers www.ti.com 17.3.11 RTI Up Counter 1 Register (RTIUC1) The up counter 1 register holds the current value of the prescale counter 1. This register is shown in Figure 17-22 and described in Table 17-12. Figure 17-22. RTI Up Counter 1 Register (RTIUC1) [offset = 34h] 31 16 UC1 R/WP-0 15 0 UC1 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-12.
Control Registers www.ti.com 17.3.12 RTI Compare Up Counter 1 Register (RTICPUC1) The compare up counter 1 register holds the value compared with prescale counter 1. This register is shown in Figure 17-23 and described in Table 17-13. Figure 17-23. RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h] 31 16 CPUC1 R/WP-0 15 0 CPUC1 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-13.
Control Registers www.ti.com 17.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1) The capture free running counter 1 register holds the current value of free running counter 1 on external events. This register is shown in Figure 17-24 and described in Table 17-14. Figure 17-24. RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h] 31 16 CAFRC1 R-0 15 0 CAFRC1 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17-14.
Control Registers www.ti.com 17.3.15 RTI Compare 0 Register (RTICOMP0) The compare 0 register holds the value to be compared with the counters. This register is shown in Figure 17-26 and described in Table 17-16. Figure 17-26. RTI Compare 0 Register (RTICOMP0) [offset = 50h] 31 16 COMP0 R/WP-0 15 0 COMP0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-16.
Control Registers www.ti.com 17.3.17 RTI Compare 1 Register (RTICOMP1) The compare 1 register holds the value to be compared to the counters. This register is shown in Figure 17-28 and described in Table 17-18. Figure 17-28. RTI Compare 1 Register (RTICOMP1) [offset = 58h] 31 16 COMP1 R/WP-0 15 0 COMP1 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-18.
Control Registers www.ti.com 17.3.19 RTI Compare 2 Register (RTICOMP2) The compare 2 register holds the value to be compared to the counters. This register is shown in Figure 17-30 and described in Table 17-20. Figure 17-30. RTI Compare 2 Register (RTICOMP2) [offset = 60h] 31 16 COMP2 R/WP-0 15 0 COMP2 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-20.
Control Registers www.ti.com 17.3.21 RTI Compare 3 Register (RTICOMP3) The compare 3 register holds the value to be compared to the counters. This register is shown in Figure 17-32 and described in Table 17-22. Figure 17-32. RTI Compare 3 Register (RTICOMP3) [offset = 68h] 31 16 COMP3 R/WP-0 15 0 COMP3 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-22.
Control Registers www.ti.com 17.3.23 RTI Timebase Low Compare Register (RTITBLCOMP) The timebase low compare register holds the value to activate the edge detection circuit. This register is shown in Figure 17-34 and described in Table 17-24. Figure 17-34. RTI Timebase Low Compare Register (RTITBLCOMP) [offset = 70h] 31 16 TBLCOMP R/WP-0 15 0 TBLCOMP R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-24.
Control Registers www.ti.com 17.3.25 RTI Set Interrupt Enable Register (RTISETINTENA) This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. This register is shown in Figure 17-36 and described in Table 17-26. Figure 17-36.
Control Registers www.ti.com Table 17-26. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions (continued) Bit 8 Field Value SETDMA0 Description Set compare DMA request 0. 0 Read: DMA request is disabled. Write: DMA request is unchanged. 7-4 Reserved 3 SETINT3 1 Read or Write: DMA request is enabled. 0 Reads return 0. Writes have no effect. Set compare interrupt 3. 0 Read: Interrupt is disabled. Write: Corresponding bit is unchanged.
Control Registers www.ti.com 17.3.26 RTI Clear Interrupt Enable Register (RTICLEARINTENA) This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. This register is shown in Figure 17-37 and described in Table 17-27. Figure 17-37.
Control Registers www.ti.com Table 17-27. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions (continued) Bit 9 Field Value CLEARDMA1 Description Clear compare DMA request 1. 0 Read: DMA request is disabled. Write: Corresponding bit is unchanged. 1 Read: DMA request is enabled. Write: DMA request is disabled. 8 CLEARDMA1 Clear compare DMA request 0. 0 Read: DMA request is disabled. Write: Corresponding bit is unchanged. 1 Read: DMA request is enabled.
Control Registers www.ti.com 17.3.27 RTI Interrupt Flag Register (RTIINTFLAG) The corresponding flags are set at every compare match of the RTIFRCx and RTICOMPx values, whether the interrupt is enabled or not. This register is shown in Figure 17-38 and described in Table 17-28. Figure 17-38.
Control Registers www.ti.com Table 17-28. RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions (continued) Bit Field 0 INT0 Value Description Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. 0 Read: No interrupt is pending. Write: Bit is unchanged. 1 Read: Interrupt is pending. Write: Bit is cleared to 0. 17.3.
Control Registers www.ti.com 17.3.29 Digital Watchdog Preload Register (RTIDWDPRLD) This register sets the expiration time of the DWD. This register is shown in Figure 17-38 and described in Table 17-28. Figure 17-40. Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h] 31 16 Reserved R-0 15 12 11 0 Reserved DWDPRLD R-0 R/WP-FFFh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-30.
Control Registers www.ti.com 17.3.30 Watchdog Status Register (RTIWDSTATUS) This register records the status of the DWD. The values of the following status bits will not be affected by a soft reset. These bits are cleared by a power up reset, or by a write of ‘1’. These bits can be used for debug purposes. This register is shown in Figure 17-38 and described in Table 17-28. Figure 17-41.
Control Registers www.ti.com 17.3.31 RTI Watchdog Key Register (RTIWDKEY) This register must be written with the correct written key values to serve the watchdog. This register is shown in Figure 17-42 and described in Table 17-32. NOTE: It has to be taken into account that the write to the RTIWDKEY register takes 3 VCLK cycles. Figure 17-42.
Control Registers www.ti.com 17.3.32 RTI Digital Watchdog Down Counter (RTIDWDCNTR) This register provides the current value of the DWD down counter. This register is shown in Figure 17-43 and described in Table 17-34. Figure 17-43. RTI Watchdog Down Counter Register (RTIDWDCNTR) [offset = A0h] 31 25 24 16 Reserved DWDCNTR R-0 R-1FFh 15 0 DWDCNTR R-FFFFh LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17-34.
Control Registers www.ti.com 17.3.34 Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) This register selects the DWWD window size. This register is shown in Figure 17-45 and described in Table 17-36. Figure 17-45. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h] 31 16 WWDSIZE R-0000 15 0 WWDSIZE R/WP-0005h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 17-36.
Control Registers www.ti.com 17.3.35 RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) When the RTI compare event is configured to generate a DMA request or triggers (all triggered by RTI compare interrupt request flag) to other peripherals, it is often desirable to clear the RTI compare flag automatically so that the requests can be generated repeatedly without any CPU intervention.
Control Registers www.ti.com 17.3.36 RTI Compare 0 Clear Register (RTICMP0CLR) This registers holds an initial value which is larger than the value in the RTI Compare 0 register Section 17.3.4. The user needs to choose the value such that the compare clear 0 event occurs before next compare 0 event. If the Free Running Counter matches the compare value, the compare 0 interrupt request flag is cleared and the value in the RTIUDCP0 register Section 17.3.16 is added to this register.
Control Registers www.ti.com 17.3.38 RTI Compare 2 Clear Register (RTICMP2CLR) This registers holds an initial value which is larger than the value in the RTI Compare 2 register Section 17.3.4. The user needs to choose the value such that the compare clear 2 event occurs before next compare 2 event. If the Free Running Counter matches the compare value, the compare 2 interrupt request flag is cleared and the value in the RTIUDCP2 register Section 17.3.20 is added to this register.
Chapter 18 SPNU562 – May 2014 Cyclic Redundancy Check (CRC) Controller Module This chapter describes the cyclic redundancy check (CRC) controller module. NOTE: This chapter describes a superset implementation of the CRC module that includes features and functionality that require DMA. Since not all devices have DMA capability, consult your device-specific datasheet to determine applicability of these features and functions to your device being used. Topic 18.1 18.2 18.3 18.4 ............................
Overview www.ti.com 18.1 Overview The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) to verify the integrity of memory system. A signature representing the contents of the memory is obtained when the contents of the memory are read into CRC controller. The responsibility of CRC controller is to calculate the signature for a set of data and then compare the calculated signature value against a pre-determined good signature value.
Overview www.ti.com Figure 18-1.
Module Operation www.ti.com 18.2 Module Operation 18.2.1 General Operation There are two channels in CRC controller and for each channel there is a memory mapped PSA (Parallel Signature Analysis) Signature Register and a memory mapped CRC (Cyclic Redundancy Check) Value register. A memory can be organized into multiple sectors with each sector consisting of multiple data patterns. A data pattern can be 8-, 16-, 32-, or 64-bit data.
Module Operation www.ti.com 18.2.3 PSA Signature Register The 64-bit PSA Signature Register is based on the primitive polynomial (as in the following equation) to produce the maximum length LFSR (Linear Feedback Shift Register), as shown in Figure 18-2. 64 4 3 f(x) = x + x + x + x + 1 (27) Figure 18-2.
Module Operation www.ti.com After system reset and when AUTO mode is enabled, CRC Controller automatically generates a DMA request to request the pre-determined CRC value corresponding to the first sector of memory to be checked. In AUTO mode, when one sector of data patterns is compressed, the signature stored at the PSA Signature Register is first copied to the PSA Sector Signature Register and PSA Signature Register is then cleared out to all zeros.
Module Operation www.ti.com 18.2.5 CRC Value Register Associated with each channel there is a CRC Value Register. The CRC Value Register stores the predetermined CRC value. After one sector of data patterns is compressed by PSA Signature Register, CRC Controller can automatically compare the resulting signature stored at the PSA Sector Signature Register with the pre-determined value stored at the CRC Value Register if AUTO mode is enabled.
Module Operation www.ti.com The total size of the memory system to be examined is also programmed in the respective transfer count register inside DMA module. The DMA transfer count register is divided into two parts. They are element count and frame count. Note that an HW DMA request can be programmed to trigger either one frame or one entire block transfer. In Figure 18-3, an HW DMA request from a timer is used as a trigger source to initiate DMA transfer.
Module Operation www.ti.com 18.2.7.3 Semi-CPU Mode Using Hardware Timer Trigger During semi-CPU mode, no DMA request is generated by CRC controller. Therefore, no DMA channel is allocated to update CRC Value Register. CPU should not read from CRC Value Register in semi-CPU mode as it contains stale value. Note that no signature verification is performed at all during this mode. Similar to AUTO mode, either by hardware or by software DMA request can be used as a trigger for data patterns transfer.
Module Operation www.ti.com The current sector register is frozen from being updated until both the current sector register is read and CRC fail status bit is cleared by CPU. If CPU does not respond to the CRC failure in a timely manner before another sector produces a signature verification failure, the current sector register is not updated with the new sector number. An overrun interrupt is generate instead.
Module Operation www.ti.com 18.2.10.4 Underrun Interrupt Underrun interrupt only occurs in AUTO mode. The interrupt is generated when the CRC Value Register is not updated with the corresponding signature when the data pattern counter finishes counting. During AUTO mode, CRC Controller generates DMA request to update CRC Value Register in synchronization to the corresponding sector of the memory. Signature verification is also performed if underrun condition is detected.
Module Operation www.ti.com Figure 18-7.
Module Operation www.ti.com 18.2.10.6 Interrupt Offset Register CRC Controller only generates one interrupt request to interrupt manager. A interrupt offset register is provided to indicate the source of the pending interrupt with highest priority. Table 18-3 shows the offset interrupt vector address of each interrupt condition in an ascending order of priority. Table 18-3. Interrupt Offset Mapping Offset Value 18.2.10.
Module Operation www.ti.com 18.2.13 Peripheral Bus Interface CRC is a Peripheral slave module. The register interface is similar to other peripheral modules. CRC supports following features: • Different sizes of burst operation. • Aligned and unaligned accesses. • Abort is generated for any illegal address accesses. 18.3 Example This section illustrates several of the ways in which the CRC Controller can be utilized to perform CRC. 18.3.
Example www.ti.com 18.3.1.3 • • • • CRC Setup Program the pattern count to 128. Program the sector count to 2048. For example, we want the entire 2Mbytes to be compressed within 5ms. We can program the block complete timeout pre-load (CRC_BCTOPLDx) value to 15625 (5 ms / (1 HCLK period × 64)) if CRC is operating at 200 MHz. Enable AUTO mode and all interrupts. After AUTO mode is selected, CRC Controller automatically generates a DMA request on channel 1.
Example www.ti.com 18.3.3 Example: Semi-CPU Mode If DMA controller is available in a system, the CRC module can also operate in semi-CPU mode. This means that CPU can still make use of the DMA to perform data patterns transfer to CRC controller in the background. The difference between semi-CPU mode and AUTO mode is that CRC controller does not automatically perform the signature verification.
CRC Control Registers www.ti.com 18.3.4.1 CRC Setup • All control registers can be left in their reset state. Only enable Full-CPU mode. CPU itself reads from the memory and write the data to the PSA Signature Register inside CRC Controller. When the first incoming data pattern arrives at the PSA Signature Register, the CRC Controller will compress it. After 2MBytes data patterns are compressed, CPU can read from the PSA Signature Register.
CRC Control Registers www.ti.com 18.4.1 CRC Global Control Register 0 (CRC_CTRL0) Figure 18-9. CRC Global Control Register 0 (CRC_CTRL0) [offset = 00h] 31 16 Reserved R-0 15 9 8 Reserved CH2_PSA_SWREST R-0 R/W-0 7 1 0 Reserved CH1_PSA_SWREST R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-5. CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions Bit 31-9 8 7-1 0 Field Value Reserved 0 CH2_PSA_SWREST Description Reads return 0.
CRC Control Registers www.ti.com 18.4.3 CRC Global Control Register 2 (CRC_CTRL2) Figure 18-11. CRC Global Control Register 2 (CRC_CTRL2) [offset = 10h] 31 16 Reserved R-0 15 10 7 9 8 Reserved CH2_MODE R-0 R/WP-0 5 4 Reserved 3 2 Reserved R-0 R-0 1 0 CH1_MODE R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 18-7.
CRC Control Registers www.ti.com 18.4.4 CRC Interrupt Enable Set Register (CRC_INTS) Figure 18-12.
CRC Control Registers www.ti.com Table 18-8. CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions (continued) Bit 8 Field Value CH2_CCITENS Description Channel 2 Compression Complete Interrupt Enable Bit. User and Privileged mode (read): 0 Compression Complete Interrupt is disabled 1 Compression Complete Interrupt is enabled Privileged mode (write): 7-5 4 Reserved 0 No effect 1 Compression Complete Interrupt enable 0 Reads return 0. Writes have no effect.
CRC Control Registers www.ti.com 18.4.5 CRC Interrupt Enable Reset Register (CRC_INTR) Figure 18-13.
CRC Control Registers www.ti.com Table 18-9. CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions (continued) Bit 8 Field Value CH2_CCITENR Description Channel 2 Compression Complete Interrupt Enable Reset Bit. User and Privileged mode (read): 0 Compression Complete Interrupt is disabled 1 Compression Complete Interrupt is enabled Privileged mode (write): 7-5 4 Reserved 0 No effect 1 Compression Complete Interrupt disable 0 Reads return 0. Writes have no effect.
CRC Control Registers www.ti.com 18.4.6 CRC Interrupt Status Register (CRC_STATUS) Figure 18-14.
CRC Control Registers www.ti.com Table 18-10. CRC Interrupt Status Register (CRC_STATUS) Field Descriptions (continued) Bit 8 Field Value CH2_CCIT Description Channel 2 CRC Pattern Compression Complete Interrupt Status Flag. This bit is only set in Semi-CPU mode. User and Privileged mode (read): 0 No Compression Complete Interrupt is active 1 Compression Complete Interrupt is active Privileged mode (write): 7-5 4 Reserved 0 No effect 1 Bit is cleared 0 Reads return 0.
CRC Control Registers www.ti.com 18.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG) Figure 18-15. CRC Interrupt Offset (CRC_INT_OFFSET_REG) [offset = 30h] 31 16 Reserved R-0 15 8 7 0 Reserved OFSTREG R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-11. CRC Interrupt Offset (CRC_INT_OFFSET_REG) Field Descriptions Bit Field 31-8 Reserved 7-0 OFSTREG Value 0 Reads return 0. Writes have no effect. CRC Interrupt Offset.
CRC Control Registers www.ti.com 18.4.8 CRC Busy Register (CRC_BUSY) Figure 18-16. CRC Busy Register (CRC_BUSY) [offset = 38h] 31 16 Reserved R-0 15 9 8 7 1 0 Reserved CH2_BUSY Reserved CH1_BUSY R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-12. CRC Busy Register (CRC_BUSY) Field Descriptions Bit 31-9 8 7-1 0 Field Value Reserved 0 CH2_BUSY Reserved CH1_BUSY Description Reads return 0. Writes have no effect. CH2_BUSY.
CRC Control Registers www.ti.com 18.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) Figure 18-18. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) [offset = 44h] 31 16 Reserved R-0 15 0 CRC_SEC_COUNT1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-14. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) Field Descriptions Bit Field Value 31-16 Reserved 15-0 CRC_SEC_COUNT1 0 Description Reads return 0. Writes have no effect.
CRC Control Registers www.ti.com 18.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) Figure 18-20. CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) [offset = 4Ch] 31 24 23 16 Reserved CRC_WDTOPLD1 R-0 R/W-0 15 0 CRC_WDTOPLD1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-16.
CRC Control Registers www.ti.com 18.4.14 Channel 1 PSA Signature Low Register (PSA_SIGREGL1) Figure 18-22. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) [offset = 60h] 31 0 PSASIG1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-18. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) Field Descriptions Bit 31-0 Field Description PSASIG1 Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register. 18.4.
CRC Control Registers www.ti.com 18.4.17 Channel 1 CRC Value High Register (CRC_REGH1) Figure 18-25. Channel 1 CRC Value High Register (CRC_REGH1) [offset = 6Ch] 31 0 CRC1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-21. Channel 1 CRC Value High Register (CRC_REGH1) Field Descriptions Bit Field Description 31-0 CRC1 Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[63:32] register. 18.4.
CRC Control Registers www.ti.com 18.4.20 Channel 1 Raw Data Low Register (RAW_DATAREGL1) Figure 18-28. Channel 1 Raw Data Low Register (RAW_DATAREGL1) [offset = 78h] 31 0 RAW_DATA1 R-0 LEGEND: R = Read only; -n = value after reset Table 18-24. Channel 1 Raw Data Low Register (RAW_DATAREGL1) Field Descriptions Bit 31-0 Field Description RAW_DATA1 Channel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. 18.4.
CRC Control Registers www.ti.com 18.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) Figure 18-31. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) [offset = 84h] 31 16 Reserved R-0 15 0 CRC_SEC_COUNT2 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-27. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) Field Descriptions Bit Field Value 31-16 Reserved 15-0 CRC_SEC_COUNT2 0 Description Reads return 0. Writes have no effect.
CRC Control Registers www.ti.com 18.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2) Figure 18-33. CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2) [offset = 8Ch] 31 24 23 16 Reserved CRC_WDTOPLD2 R-0 R/W-0 15 0 CRC_WDTOPLD2 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-29.
CRC Control Registers www.ti.com 18.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Figure 18-35. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) [offset = A0h] 31 0 PSASIG2 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-31. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Field Descriptions Bit 31-0 Field Description PSASIG2 Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register. 18.4.
CRC Control Registers www.ti.com 18.4.30 Channel 2 CRC Value High Register (CRC_REGH2) Figure 18-38. Channel 2 CRC Value High Register (CRC_REGH2) [offset = ACh] 31 0 CRC2 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18-34. Channel 2 CRC Value High Register (CRC_REGH2) Field Descriptions Bit Field Description 31-0 CRC2 Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register. 18.4.
CRC Control Registers www.ti.com 18.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2) Figure 18-41. Channel 2 Raw Data Low Register (RAW_DATAREGL2) [offset = B8h] 31 0 RAW_DATA2 R-0 LEGEND: R = Read only; -n = value after reset Table 18-37. Channel 2 Raw Data Low Register (RAW_DATAREGL2) Field Descriptions Bit 31-0 Field Description RAW_DATA2 Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. 18.4.
Chapter 19 SPNU562 – May 2014 Vectored Interrupt Manager (VIM) Module This chapter describes the behavior of the vectored interrupt manager (VIM) module of the device family. Topic 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 642 ........................................................................................................................... Overview ......................................................................................................... Dual VIM for Safety ...................
Overview www.ti.com 19.1 Overview The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on a device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the central processing unit (CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR).
Dual VIM for Safety www.ti.com 19.2 Dual VIM for Safety A block diagram of Dual VIM for safety support is shown in Figure 19-1. To reduce probability of common cause failure, the VIM module mimics the dual CPU scheme of two cycle delayed operation of the two cores. In this case, the MMR (Memory Mapped Register) interface to the second instance is delayed by two cycles. Similarly, the interrupt inputs are also delayed by two cycles to the second instance.
Device Level Interrupt Management www.ti.com 19.3 Device Level Interrupt Management A block diagram of device level interrupt handling is shown in Figure 19-2. When an event occurs within a peripheral, the peripheral makes an interrupt request to the VIM. Then, VIM prioritizes the requests from peripherals and provides the address of the highest interrupt service routine (ISR) to the CPU. Finally, CPU starts executing the ISR instructions from that address in the ISR. Section 19.3.1 through Section 19.3.
Device Level Interrupt Management www.ti.com 19.3.2 Interrupt Handling at the CPU The ARM CPU provides two vectors for interrupt requests—fast interrupt requests (FIQs) and normal interrupt requests (IRQs). FIQs are higher priority than IRQs, and FIQ interrupts may interrupt IRQ interrupts. NOTE: The FIQ implemented in Cortex-R4F/R5F is Non-Maskable Fast Interrupts (NMFI). Once FIQ is enabled (by clearing F bit in CPSR), it can NOT be disabled by setting F bit in CPSR.
Device Level Interrupt Management www.ti.com 19.3.3 Software Interrupt Handling Options The device supports three different possibilities for software to handle interrupts 1. Index interrupts mode (compatible with TMS470R1x legacy code) After the interrupt is received by the CPU, the CPU branches to 0x18 (IRQ) or 0x1C (FIQ) to execute the main ISR. The main ISR routine reads the offset register (IRQINDEX, FIQINDEX) to determine the source of the interrupt.
Interrupt Handling Inside VIM www.ti.com 19.4 Interrupt Handling Inside VIM A block diagram of the interrupt handling inside VIM is shown in Figure 19-3 Figure 19-3.
Interrupt Handling Inside VIM www.ti.com 19.4.1 VIM Interrupt Channel Mapping The VIM support 128 interrupt channels (including phantom interrupt). A block diagram of the VIM interrupt requests arrangement from peripheral modules to the interrupt channels is provided in Figure 194. Each interrupt channel (CHANx) has a corresponding mapping register bit field (CHANMAPx[6:0]). This mapping register determines which interrupt channel it maps each VIM interrupt request.
Interrupt Handling Inside VIM www.ti.com Figure 19-5.
Interrupt Handling Inside VIM www.ti.com 19.4.2 VIM Input Channel Management As shown in Figure 19-7, the VIM enables channels on a channel-by-channel basis (in the REQENASET and REQENACLR registers); unused channels may be masked to prevent spurious interrupts. NOTE: The interrupt ENABLE register does not affect the value of INTREQ. Figure 19-7. Interrupt Channel Management INT FLAG INTREQ.0 FIQ_CHAN[0] CHAN0 INT_CHAN0 INT FLAG INTREQ.1 FIQ_CHAN[1] CHAN1 INT_CHAN1 INT FLAG INTREQ.2 CHAN2 1 REQENA.
Interrupt Vector Table (VIM RAM) www.ti.com After the VIM has generated the vector corresponding to the highest active IRQ, it updates the FIQINDEX or the IRQINDEX register, depending on the class of interrupt. Then, it accesses the interrupt vector table using the vector value to fetch the address of the corresponding ISR. If the request is an FIQ class interrupt, the address read from the interrupt vector table, is written to the FIQVECREG register.
Interrupt Vector Table (VIM RAM) www.ti.com When a read occurs from the CPU or VIM, the VIM calculates the ECC bits from the data coming from the interrupt vector table and compares it to the known good ECC value stored in the table. If a single bit error is detected in the data, the SECDED block will automatically correct it. The read data will be a corrected one in this case. If double bit errors are detected, the read data will be the uncorrected one.
Interrupt Vector Table (VIM RAM) www.ti.com 19.5.3 Interrupt Vector Table Initialization After reset, the interrupt vector table content, including the ECC bits is not initialized. Therefore, the interrupt vector table has to be initialized first before enabling the corresponding interrupt channel. This can be done either using the hardware initialization mechanism (in Chapter Architecture Overview) or it can be done by writing known values into the interrupt vector table by software.
Interrupt Vector Table (VIM RAM) www.ti.com Following sequence should be used for injecting faults to data bits and testing the ECC check feature. 1. Write the data locations of VIM RAM with the required patterns while keeping ECCENA active. The ECC bits will be automatically initialized along with data bits. 2. Disable ECC by setting ECCENA=0 in ECCCTRL register. In this mode, writing to data bits does not automatically update ECC bits. 3.
VIM Wakeup Interrupt www.ti.com 19.6 VIM Wakeup Interrupt The wakeup interrupts are used to come out of low power mode (LPM). Any interrupt requests can be used to wake up the device. After reset, all interrupt requests are set to wake up from LPM. However, the VIM can mask unwanted interrupt lines for wake-up by using the WAKEENASET and WAKEENACLR register. The value in REQENASET / REQENACLR does NOT impact the wakeup interrupt.
Capture Event Sources www.ti.com 19.7 Capture Event Sources The VIM can select any of the 128 interrupt request to generate up to two capture events for the real-time interrupt (RTI) module (see Figure 19-11). The value in REQENASET / REQENACLR does NOT impact the capture event. Two registers (Section 19.9.17) are available, one for each capture event source. Figure 19-11.
Examples www.ti.com Example 19-2. Enable/Disable IRQ/FIQ through CPSR FIQENABLE .equ 0x40 IRQENABLE .equ 0x80 ...... _Enable_Fiq MRS R1, CPSR BIC R1, R1, #FIQENABLE MSR CPSR, R1 MOV PC, LR ...... _Disable_Irq MRS R1, CPSR ORR R1, R1, #IRQENABLE MSR CPSR, R1 MOV PC, LR ...... _Enable_Irq MRS R1, CPSR BIC R1, R1, #IRQENABLE MSR CPSR, R1 MOV PC, LR 19.8.
Examples www.ti.com Example 19-4 shows a fast response to the FIQ interrupt in Index Interrupt and can be applied to a system that has more than one channel assigned as a FIQ. It is built in Index Interrupt compatible with TMS470R1x legacy code. Example 19-4. How to Respond to FIQ With Short Latency 00000000h 00000004h 00000008h 0000000Ch 00000010h 00000014h 00000018h .sect ".
VIM Control Registers www.ti.com 19.9 VIM Control Registers Table 19-5 lists the VIM module registers. Each register begins on a word boundary. All registers are 32bit, 16-bit, and 8-bit accessible for read and write. Write is only possible in privilege mode. The base address of the VIM module is FFFF FE00h. The base address of the ECC-related VIM registers is FFFF FD00h. The address locations not listed are reserved. Table 19-5.
VIM Control Registers www.ti.com 19.9.1 Interrupt Vector Table ECC Status Register (ECCSTAT) Figure 19-12 and Table 19-6 describe this register. Figure 19-12. Interrupt Vector Table ECC Status Register (ECCSTAT) [offset = ECh] 31 16 Reserved R-0 15 9 8 7 1 0 Reserved SBERR Reserved UERR R-0 R/W1CP-0 R-0 R/W1CP-0 LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset Table 19-6.
VIM Control Registers www.ti.com 19.9.2 Interrupt Vector Table ECC Control Register (ECCCTL) Figure 19-13. Interrupt Vector Table ECC Control Register (ECCCTL) [offset = F0h] 31 28 27 Reserved 24 R-0 15 23 SBE_EVT_EN R/WP-5h 12 11 Reserved 19 TEST_DIAG_EN R/WP-Ah 7 16 EDAC_MODE R-0 8 R-0 20 Reserved R/WP-Ah 4 3 Reserved 0 ECCENA R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 19-7.
VIM Control Registers www.ti.com 19.9.3 Uncorrectable Error Address Register (UERRADDR) The uncorrectable error address register gives the address of the first uncorrectable error location. NOTE: No computation is needed when reading the complete register to retrieve the address in the Interrupt Vector Table. This register will never be reset by a power-on reset nor any other reset source. Figure 19-14.
VIM Control Registers www.ti.com 19.9.5 Single Bit Error Address Register (SBERRADDR) This register gives the address of the first single bit ECC error detected by the ECC logic.Figure 19-16 and Table 19-10 describe this register. NOTE: This register will never be reset by a power-on reset nor any other reset source. Figure 19-16.
VIM Control Registers www.ti.com 19.9.7 IRQ Index Offset Vector Register (IRQINDEX) The IRQ offset register provides the user with the numerical index value that represents the pending IRQ interrupt with the highest priority. Figure 19-17 and Table 19-12 describe this register. Figure 19-17. IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h] 31 16 Reserved R-0 15 8 7 0 Reserved IRQINDEX R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 19-12.
VIM Control Registers www.ti.com 19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3]) The FIQ/IRQ program control registers determine whether a given interrupt request will be either FIQ or IRQ. Figure 19-19, Figure 19-20, Figure 19-21, Figure 19-22 and Table 19-14 describe these registers. NOTE: Channel 0 and 1 are FIQ only, not impacted by this register. Figure 19-19.
VIM Control Registers www.ti.com 19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3]) The pending interrupt register gives the pending interrupt requests. The register is updated every vbus clock cycle. Figure 19-23, Figure 19-24, Figure 19-25, Figure 19-26 and Table 19-15 describe this register. Figure 19-23.
VIM Control Registers www.ti.com 19.9.11 Interrupt Enable Set Registers (REQENASET[0:3]) The interrupt register enable selectively enables individual request channels. Figure 19-27, Figure 19-28, Figure 19-29, Figure 19-30 and Table 19-16 describe these registers. NOTE: Channel 0 and 1 are always enabled, not impacted by this register. Figure 19-27.
VIM Control Registers www.ti.com 19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3]) The interrupt register enable selectively disables individual request channels. Figure 19-31, Figure 19-32, Figure 19-33, Figure 19-34 and Table 19-17 describe these registers. NOTE: Channel 0 and 1 are always enabled, not impacted by this register. Figure 19-31.
VIM Control Registers www.ti.com 19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3]) The wake-up enable registers selectively enables individual wake-up interrupt request lines. Figure 19-35, Figure 19-36, Figure 19-37, Figure 19-38 and Table 19-18 describe these registers. Figure 19-35. Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h] 31 0 WAKEENASET[31:0] R/WP-FFFF FFFFh LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Figure 19-36.
VIM Control Registers www.ti.com 19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3]) The wake-up enable register selectively disables individual wake-up interrupt request lines. Figure 19-39, Figure 19-40, Figure 19-41, Figure 19-42 and Table 19-19 describe these registers. Figure 19-39. Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h] 31 0 WAKEENACLR[31:0] R/WP-FFFF FFFFh LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Figure 19-40.
VIM Control Registers www.ti.com 19.9.15 IRQ Interrupt Vector Register (IRQVECREG) The interrupt vector register gives the address of the enabled and active IRQ interrupt. Figure 19-43 and Table 19-20 describe these registers. Figure 19-43. IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h] 31 0 IRQVECREG R-0 LEGEND: R = Read only; -n = value after reset Table 19-20. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions Bit 31-0 Field IRQVECREG Value From Section 19.
VIM Control Registers www.ti.com 19.9.17 Capture Event Register (CAPEVT) Figure 19-45 and Table 19-22 describe this register. Figure 19-45. Capture Event Register (CAPEVT) [offset = 78h] 31 23 22 16 Reserved CAPEVTSRC1 R-U R/WP-0 15 7 6 0 Reserved CAPEVTSRC0 R-U R/WP-0 LEGEND: R = Read only; WP = Write in privilege mode only; U = Undefined; -n = value after reset Table 19-22.
VIM Control Registers www.ti.com 19.9.18 VIM Interrupt Control Registers (CHANCTRL[0:31]) Thirty-two interrupt control registers control the 128 interrupt channels of the VIM. Each register controls four interrupt channels: each of them is indexed from 0 to 127. Table 19-23 shows the organization of all the registers and the reset value of each. Each four fields of the register has been named with a generic index that refers to the detailed register organization.
VIM Control Registers www.ti.com Table 19-24. Interrupt Control Registers (CHANCTRL[0:31]) Field Descriptions (continued) Bit 22-16 Field CHANMAPx Value Description CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. These bits determine which interrupt request the priority channel CHANx 1 maps to: 1 0 Read: Interrupt request 0 maps to channel priority CHANx 1. Write: The default value of this bit after reset is given in Table 19-23. The channel priority CHANx 1 is set with the interrupt request.
Chapter 20 SPNU562 – May 2014 Direct Memory Access Controller (DMA) Module This chapter describes the direct memory access (DMA) controller. Topic 20.1 20.2 20.3 676 ........................................................................................................................... Page Overview ......................................................................................................... 677 Module Operation ...........................................................................
Overview www.ti.com 20.1 Overview The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations.
Overview www.ti.com Figure 20-1. DMA Block Diagram Errors (Single, Double Bit Errors) Event manager (prioritization, arbitration) Hardware Events DMA req sync and polarity FIFO A channel processing FIFO B channel processing Control Packet Access Arbiter CPU I/F Control Regs Interrupt Manager BTC, FTC, BER, LFS, HBC, MPV interrupts Port Arbiter Control Packet RAM Port A Port B 20.1.
Module Operation www.ti.com respective channels in the PARx registers. 20.2 Module Operation The DMA acts as an independent master in the platform architecture. DMA will attempt to execute up to two channels at the same time to maximize system throughput. Each channel can be configured to utilize either Port A or B or both for the read and write accesses while storing the data in one of the FIFOs.
Module Operation www.ti.com 20.2.1 Memory Space The DMA controller makes no distinction between program memory and data memory. The DMA controller can transfer to and from any space within the 4 Gbyte physical address map, by programming the absolute address for the source and destination in the control packet. Control packets store the transfer information such as source address, destination address, transfer count and control attributes for each channel. 20.2.
Module Operation www.ti.com 20.2.3 Addressing Modes There are three addressing modes supported by the DMA controller that can be setup independent for the source and the destination address: • Constant -- source and/or destination addresses do not change. • Post incremented -- source and/or destination address are post-incremented by the element size. • Indexed -- source and/or destination address is post-incremented as defined in the Element Index Offset Register (Section 20.3.2.
Module Operation www.ti.com Figure 20-4. DMA Request Mapping and Control Packet Organization CH0ASI[5:0] DMAREQ(0) DMAREQ(1) Ch 0 DMAREQ(2) Y... DMAREQ(63) CH1ASI[5:0] DMAREQ(0) Control Packet 0 Ch 1 DMAREQ(1) Control Packet 1 YY. DMAREQ(2) Y... Control Packet 31 DMAREQ(63) Y... CH31ASI[5:0] DMAREQ(0) Ch 31 DMAREQ(1) DMAREQ(2) Y... DMAREQ(63) Figure 20-5.
Module Operation www.ti.com 20.2.4.1 Initial Source Address This field stores the absolute 32-bit source address of the DMA transfer. 20.2.4.2 Initial Destination Address This field stores the absolute 32-bit destination address of the DMA transfer. 20.2.4.3 Initial Transfer Count The transfer count field is composed of two parts. The frame transfer count value and the element transfer count value. Each count value is 13 bits wide.
Module Operation www.ti.com 20.2.4.7 Current Destination Address The current destination address field contains the current working destination address during a DMA transaction. The current destination address is incremented during post-increment addressing mode or indexing mode. 20.2.4.8 Current Transfer Count The current transfer count stores the remaining number of elements to be transferred in a block. It is decremented by one for each element read from the source location.
Module Operation www.ti.com Figure 20-8. DMA Indexing Example 2 0x0 E1 E4 E7 E10 E13 E16 E19 E22 E2 E5 E8 E11 E14 E17 E20 E23 E3 E6 E9 E12 E15 E18 E21 E23 0x20 0x40 0x60 0x80 Element Index = 64 Frame Index = 4 This example can be applied to either source or destination indexing and assumes the following setup. Element Size = 32 bit Element Count = 3 Frame Count = 8 20.2.
Module Operation www.ti.com Table 20-1. Arbitration According to Priority Queues and Priority Schemes Queue Priority Scheme Remark Channels are serviced in an ascending order according to the channel number. The lower the channel number, the higher the priority. A channel will be arbitrated out whenever there is a higher pending channel. Otherwise a channel is completely serviced until its transfer count reaches zero before the next highest pending channel is serviced.
Module Operation www.ti.com Figure 20-11.
Module Operation www.ti.com Figure 20-12.
Module Operation www.ti.com Figure 20-13.
Module Operation www.ti.com 20.2.7 DMA Request There are three ways to start a DMA transfer: • Software request: The transfer will be triggered by writing to SW Channel Enable Set and Status Register (Section 20.3.1.7). The software request can trigger either a block or a frame transfer depending on what the trigger type (TTYPE) bit is set to in the Channel Control Register (Section 20.3.2.4). • Hardware request: The DMA controller can handle up to 32 DMA Request lines.
Module Operation www.ti.com 20.2.9 Interrupts Each channel can be configured to generate interrupts on several transfer conditions: • Frame transfer complete (FTC) interrupt: an interrupt is issued after the last element of a frame has been transferred. • Last frame transfer started (LFS) interrupt: an interrupt is issued before the first element of the last frame of a block transfer has started.
Module Operation www.ti.com Figure 20-15. Detailed Interrupt Structure (Frame Transfer Complete Path) Frame Transfer Complete Ch0 ••• ••• ••• FTC0AB FTCB Frame Transfer Complete Ch31 FTC31AB This figure is applicable for the HBC, LFS, BTC, and BER interrupt.
Module Operation www.ti.com 20.2.10 Debugging The DMA supports four different behaviors in suspend mode. These behaviors can be configured by the user as per the application requirement. • Immediate stop at a DMA channel arbitration boundary. Please refer to Table 20-2 and Table 20-3 for arbitration boundary definition. • Finish current frame transfer and continue after suspend ends. • Finish current block transfer and continue after suspend ends. • Ignore the suspend.
Module Operation www.ti.com 20.2.12 FIFO Buffer DMA FIFO is 4 levels deep and 64-bit wide (can hold up to 4 × 64-bits of data). They are used for Data packing and unpacking. The DMA FIFO has two states: • EMPTY: The FIFO contains no data. • FULL: The FIFO is filled or the element count has reached zero; the read operation has to be stopped. DMA channels can only be switched when the FIFO is empty. This also implies that arbitration between channels is done when the FIFO is empty.
Module Operation www.ti.com 20.2.13 Channel Chaining Channel chaining is used to trigger a single or multiple channels with out an external DMA request. This is possible by chaining one control packet to other. Chain[5:0] field of the Channel Control Register (Section 20.3.2.4) is used to program the chaining control packet. Chained control packets follow arbitration rules within the pending register. For example if CH1, CH2, CH4, CH5 are triggered together and CH3 is chained with CH1.
Module Operation www.ti.com 20.2.15 Memory Protection The DMA controller is capable of access to the full address range of the device. The protection mechanism allows the protection of multiple memory regions to restrict accesses to those address ranges. This will allow the application to protect critical application data from unintentionally being accessed by the DMA controller. 20.2.15.
Module Operation www.ti.com Figure 20-17. Example of Protection Mechanism 0xFFFFFFFF Region3 System + peripherals Region2 0xFFF78000 No access restrictions Access restrictions 0x08003FFF Region1 RAM 0x08000000 Region0 0x00000000 20.2.16 ECC Checking The Control packet RAM is protected using a Single Error Correction Double Error Detection (SECDED) scheme. This scheme is implemented using a total of 9 ECC check bits for every 128 bits of data stored in the DMA Control Packet RAM.
Module Operation www.ti.com 20.2.17 ECC Testing The ECC RAM is accessible to allow manually inserting faults so that the ECC checking feature can be tested. Test mode is entered by asserting the TEST bit in the ECC Control Register (Section 20.3.1.65). Once the bit is set, the ECC bits are mapped to the control packet RAM starting address A00h. The sequence to test the ECC is: 1. Write the data location of the Control Packet RAM while keeping ECC_ENA active.
Module Operation www.ti.com 20.2.19 Transaction Errors DMA generates parity for all transactions and checks parity for responses to the transactions. Note that this feature is distinct from the ECC checking for the Control Packet RAM. If a parity error is detected in these transactions and TER_EN bit in TERECTRL register is enabled, DMA will stop processing the current channel at the arbitration boundary and will update TER_ERR flag.
Control Registers and Control Packets www.ti.com 20.3 Control Registers and Control Packets The DMA control registers are summarized in Table 20-5. The base address for the control registers is FFFF F000h. The control packets are summarized in Table 20-6. The base address for the control packets is FFF8 0000h. Each register begins on a word boundary. All registers and control packets are accessible in 8, 16, and 32 bit.
Control Registers and Control Packets www.ti.com Table 20-5. DMA Control Registers (continued) Offset Acronym Register Description 11Ch GINTFLAG Global Interrupt Flag Register Section 20.3.1.38 Section 124h FTCFLAG FTC Interrupt Flag Register Section 20.3.1.39 12Ch LFSFLAG LFS Interrupt Flag Register Section 20.3.1.40 134h HBCFLAG HBC Interrupt Flag Register Section 20.3.1.41 13Ch BTCFLAG BTC Interrupt Flag Register Section 20.3.1.
Control Registers and Control Packets www.ti.com Table 20-5. DMA Control Registers (continued) Offset Acronym Register Description 1F8h DMAMPR7S DMA Memory Protection Region 7 Start Address Register Section 20.3.1.85 Section 1FCh DMAMPR7E DMA Memory Protection Region 7 End Address Register Section 20.3.1.86 228h DMASECCCTRL DMA Single bit ECC Control Register Section 20.3.1.87 230h DMAECCSBE DMA ECC Single bit Error Address Register Section 20.3.1.
Control Registers and Control Packets www.ti.com 20.3.1 Global Configuration Registers These registers control the overall behavior of the DMA controller. 20.3.1.1 Global Control Register (GCTRL) Figure 20-19.
Control Registers and Control Packets www.ti.com 20.3.1.2 Channel Pending Register (PEND) Figure 20-20. Channel Pending Register (PEND) [offset = 04h] 31 0 PEND[31:0] R-0 LEGEND: R = Read only; -n = value after reset Table 20-8. Channel Pending Register (PEND) Field Descriptions Bit 31-0 Field Value PEND[n] Description Channel pending register. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Control Registers and Control Packets www.ti.com 20.3.1.4 DMA Revision ID Register (DMAREVID) Figure 20-22. DMA Revision ID Register (DMAREVID) [offset = 10h] 31 30 29 28 27 16 SCHEME Reserved FUNC R-1 R-0 R-A0Dh 15 11 10 8 7 6 5 0 Reserved MAJOR Reserved MINOR R-0 R-0 R-0 R-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20-10.
Control Registers and Control Packets www.ti.com 20.3.1.5 HW Channel Enable Set and Status Register (HWCHENAS) Figure 20-23. HW Channel Enable Set and Status Register (HWCHENAS) [offset = 14h] 31 0 HWCHENA[31:0] R-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-11. HW Channel Enable Set and Status Register (HWCHENAS) Field Descriptions Bit 31-0 Field Value HWCHENA[n] Description Hardware channel enable bit.
Control Registers and Control Packets www.ti.com 20.3.1.7 SW Channel Enable Set and Status Register (SWCHENAS) Figure 20-25. SW Channel Enable Set and Status Register (SWCHENAS) [offset = 24h] 31 0 SWCHENA[31:0] R-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-13. SW Channel Enable Set and Status Register (SWCHENAS) Field Descriptions Bit 31-0 Field Value SWCHENA[n] Description SW channel enable bit.
Control Registers and Control Packets www.ti.com 20.3.1.9 Channel Priority Set Register (CHPRIOS) Figure 20-27. Channel Priority Set Register (CHPRIOS) [offset = 34h] 31 0 CPS[31:0] R-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-15. Channel Priority Set Register (CHPRIOS) Field Descriptions Bit 31-0 Field Value CPS[n] Description Channel priority set bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Control Registers and Control Packets www.ti.com 20.3.1.11 Global Channel Interrupt Enable Set Register (GCHIENAS) Figure 20-29. Global Channel Interrupt Enable Set Register (GCHIENAS) [offset = 44h] 31 0 GCHIE[31:0] R-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-17. Global Channel Interrupt Enable Set Register (GCHIENAS) Field Descriptions Bit 31-0 Field Value GCHIE[n] Description Global channel interrupt enable bit.
Control Registers and Control Packets www.ti.com 20.3.1.13 DMA Request Assignment Register 0 (DREQASI0) Figure 20-31. DMA Request Assignment Register 0 (DREQASI0) [offset = 54h] 31 30 29 24 23 22 21 16 Reserved CH0ASI Reserved CH1ASI R-0 R/WP-0 R-0 R/WP-1h 15 14 13 8 7 6 5 0 Reserved CH2ASI Reserved CH3ASI R-0 R/WP-2h R-0 R/WP-3h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-19.
Control Registers and Control Packets www.ti.com 20.3.1.14 DMA Request Assignment Register 1 (DREQASI1) Figure 20-32. DMA Request Assignment Register 1 (DREQASI1) [offset = 58h] 31 30 29 24 23 22 21 16 Reserved CH4ASI Reserved CH5ASI R-0 R/WP-4h R-0 R/WP-5h 15 14 13 8 7 6 5 0 Reserved CH6ASI Reserved CH7ASI R-0 R/WP-6h R-0 R/WP-7h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-20.
Control Registers and Control Packets www.ti.com 20.3.1.15 DMA Request Assignment Register 2 (DREQASI2) Figure 20-33. DMA Request Assignment Register 2 (DREQASI2) [offset = 5Ch] 31 30 29 24 23 22 21 16 Reserved CH8ASI Reserved CH9ASI R-0 R/WP-8h R-0 R/WP-9h 15 14 13 8 7 6 5 0 Reserved CH10ASI Reserved CH11ASI R-0 R/WP-Ah R-0 R/WP-Bh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-21.
Control Registers and Control Packets www.ti.com 20.3.1.16 DMA Request Assignment Register 3 (DREQASI3) Figure 20-34. DMA Request Assignment Register 3 (DREQASI3) [offset = 60h] 31 30 29 24 23 22 21 16 Reserved CH12ASI Reserved CH13ASI R-0 R/WP-Ch R-0 R/WP-Dh 15 14 13 8 7 6 5 0 Reserved CH14ASI Reserved CH15ASI R-0 R/WP-Eh R-0 R/WP-Fh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-22.
Control Registers and Control Packets www.ti.com 20.3.1.17 DMA Request Assignment Register 4 (DREQASI4) Figure 20-35. DMA Request Assignment Register 4 (DREQASI4) [offset = 64h] 31 30 29 24 23 22 21 16 Reserved CH16ASI Reserved CH17ASI R-0 R/WP-10h R-0 R/WP-11h 15 14 13 8 7 6 5 0 Reserved CH18ASI Reserved CH19ASI R-0 R/WP-12h R-0 R/WP-13h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-23.
Control Registers and Control Packets www.ti.com 20.3.1.18 DMA Request Assignment Register 5 (DREQASI5) Figure 20-36. DMA Request Assignment Register 5 (DREQASI5) [offset = 68h] 31 30 29 24 23 22 21 16 Reserved CH20ASI Reserved CH21ASI R-0 R/WP-14h R-0 R/WP-15h 15 14 13 8 7 6 5 0 Reserved CH22ASI Reserved CH23ASI R-0 R/WP-16h R-0 R/WP-17h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-24.
Control Registers and Control Packets www.ti.com 20.3.1.19 DMA Request Assignment Register 6 (DREQASI6) Figure 20-37. DMA Request Assignment Register 6 (DREQASI6) [offset = 6Ch] 31 30 29 24 23 22 21 16 Reserved CH24ASI Reserved CH25ASI R-0 R/WP-18h R-0 R/WP-19h 15 14 13 8 7 6 5 0 Reserved CH26ASI Reserved CH27ASI R-0 R/WP-1Ah R-0 R/WP-1Bh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-25.
Control Registers and Control Packets www.ti.com 20.3.1.20 DMA Request Assignment Register 7 (DREQASI7) Figure 20-38. DMA Request Assignment Register 7 (DREQASI7) [offset = 70h] 31 30 29 24 23 22 21 16 Reserved CH28ASI Reserved CH29ASI R-0 R/WP-1Ch R-0 R/WP-1Dh 15 14 13 8 7 6 5 0 Reserved CH30ASI Reserved CH31ASI R-0 R/WP-1Eh R-0 R/WP-1Fh LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-26.
Control Registers and Control Packets www.ti.com 20.3.1.21 Port Assignment Register 0 (PAR0) Figure 20-39.
Control Registers and Control Packets www.ti.com 20.3.1.22 Port Assignment Register 1 (PAR1) Figure 20-40.
Control Registers and Control Packets www.ti.com 20.3.1.23 Port Assignment Register 2 (PAR2) Figure 20-41.
Control Registers and Control Packets www.ti.com 20.3.1.24 Port Assignment Register 3 (PAR3) Figure 20-42.
Control Registers and Control Packets www.ti.com 20.3.1.25 FTC Interrupt Mapping Register (FTCMAP) Figure 20-43. FTC Interrupt Mapping Register (FTCMAP) [offset = B4h] 31 0 FTCAB[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-31. FTC Interrupt Mapping Register (FTCMAP) Field Descriptions Bit 31-0 Field Value FTCAB[n] Description Frame transfer complete (FTC) interrupt to Group A or Group B.
Control Registers and Control Packets www.ti.com 20.3.1.28 BTC Interrupt Mapping Register (BTCMAP) Figure 20-46. BTC Interrupt Mapping Register (BTCMAP) [offset = CCh] 31 0 BTCAB[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-34. BTC Interrupt Mapping Register (BTCMAP) Field Descriptions Bit 31-0 Field Value BTCAB[n] Description Block transfer complete (BTC) interrupt to Group A or Group B.
Control Registers and Control Packets www.ti.com 20.3.1.30 FTC Interrupt Enable Set Register (FTCINTENAS) Figure 20-48. FTC Interrupt Enable Set Register (FTCINTENAS) [offset = DCh] 31 0 FTCINTENA[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-36. FTC Interrupt Enable Set Register (FTCINTENAS) Field Descriptions Bit 31-0 Field Value FTCINTENA[n] Description Frame transfer complete (FTC) interrupt enable.
Control Registers and Control Packets www.ti.com 20.3.1.32 LFS Interrupt Enable Set Register (LFSINTENAS) Figure 20-50. LFS Interrupt Enable Set Register (LFSINTENAS) [offset = ECh] 31 0 LFSINTENA[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-38. LFS Interrupt Enable Set Register (LFSINTENAS) Field Descriptions Bit 31-0 Field Value LFSINTENA[n] Description Last frame started (LFS) interrupt enable.
Control Registers and Control Packets www.ti.com 20.3.1.34 HBC Interrupt Enable Set Register (HBCINTENAS) Figure 20-52. HBC Interrupt Enable Set Register (HBCINTENAS) [offset = FCh] 31 0 HBCINTENA[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-40. HBC Interrupt Enable Set Register (HBCINTENAS) Field Descriptions Bit 31-0 Field Value HBCINTENA[n] Description Half block complete (HBC) interrupt enable.
Control Registers and Control Packets www.ti.com 20.3.1.36 BTC Interrupt Enable Set Register (BTCINTENAS) Figure 20-54. BTC Interrupt Enable Set Register (BTCINTENAS) [offset = 10Ch] 31 0 BTCINTENA[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-42. BTC Interrupt Enable Reset Register (BTCINTENAS) Field Descriptions Bit 31-0 Field Value BTCINTENA[n] Description Block transfer complete (BTC) interrupt enable.
Control Registers and Control Packets www.ti.com 20.3.1.38 Global Interrupt Flag Register (GINTFLAG) Figure 20-56. Global Interrupt Flag Register (GINTFLAG) [offset = 11Ch] 31 0 GINT[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-44. Global Interrupt Flag Register (GINTFLAG) Field Descriptions Bit 31-0 Field Value GINT[n] Description Global interrupt flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Control Registers and Control Packets www.ti.com 20.3.1.40 LFS Interrupt Flag Register (LFSFLAG) Figure 20-58. LFS Interrupt Flag Register (LFSFLAG) [offset = 12Ch] 31 0 LFSI[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-46. LFS Interrupt Flag Register (LFSFLAG) Field Descriptions Bit 31-0 Field Value LFSI[n] Description Last frame started (LFS) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Control Registers and Control Packets www.ti.com 20.3.1.42 BTC Interrupt Flag Register (BTCFLAG) Figure 20-60. BTC Interrupt Flag Register (BTCFLAG) [offset = 13Ch] 31 0 BTCI[31:0] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-48. BTC Interrupt Flag Register (BTCFLAG) Field Descriptions Bit 31-0 Field Value BTCI[n] Description Block transfer complete (BTC) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Control Registers and Control Packets www.ti.com 20.3.1.44 FTCA Interrupt Channel Offset Register (FTCAOFFSET) Figure 20-62. FTCA Interrupt Channel Offset Register (FTCAOFFSET) [offset = 14Ch] 31 16 Reserved R-0 15 8 7 6 5 0 Reserved sbz sbz FTCA R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 20-50. FTCA Interrupt Channel Offset Register (FTCAOFFSET) Field Descriptions Bit 31-16 Field Value Description Reserved 0 Read returns 0. Writes have no effect.
Control Registers and Control Packets www.ti.com 20.3.1.46 HBCA Interrupt Channel Offset Register (HBCAOFFSET) Figure 20-64. HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h] 31 16 Reserved R-0 15 8 7 6 5 0 Reserved sbz sbz HBCA R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 20-52. HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions Bit 31-16 Field Value Description Reserved 0 Read returns 0. Writes have no effect.
Control Registers and Control Packets www.ti.com 20.3.1.48 BERA Interrupt Channel Offset Register (BERAOFFSET) Figure 20-66. BERA Interrupt Channel Offset Register (BERAOFFSET) [offset = 15Ch] 31 16 Reserved R-0 15 8 7 6 5 0 Reserved sbz sbz BERA R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 20-54. BERA Interrupt Channel Offset Register (BERAOFFSET) Field Descriptions Bit 31-16 Field Value Description Reserved 0 Read returns 0. Writes have no effect.
Control Registers and Control Packets www.ti.com 20.3.1.50 LFSB Interrupt Channel Offset Register (LFSBOFFSET) Figure 20-68. LFSB Interrupt Channel Offset Register (LFSBOFFSET) [offset = 164h] 31 16 Reserved R-0 15 8 7 6 5 0 Reserved sbz sbz LFSB R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 20-56. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions Bit 31-16 Field Value Description Reserved 0 Read returns 0. Writes have no effect.
Control Registers and Control Packets www.ti.com 20.3.1.52 BTCB Interrupt Channel Offset Register (BTCBOFFSET) Figure 20-70. BTCB Interrupt Channel Offset Register (BTCBOFFSET) [offset = 16Ch] 31 16 Reserved R-0 15 8 7 6 5 0 Reserved sbz sbz BTCB R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 20-58. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions Bit 31-16 Field Value Description Reserved 0 Read returns 0. Writes have no effect.
Control Registers and Control Packets www.ti.com 20.3.1.54 Port Control Register (PTCRL) Figure 20-72. Port Control Register (PTCRL) [offset = 178h] 31 25 PENDB R-0 R-0 23 19 15 9 18 17 Reserved BYB R-0 R/WP-0 8 24 Reserved 7 3 16 Reserved R-0 2 1 0 Reserved PENDA Reserved BYA PSFRHQ PSFRLQ R-0 R-0 R-0 R/WP-0 R/WP-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-60.
Control Registers and Control Packets www.ti.com 20.3.1.55 RAM Test Control Register (RTCTRL) Figure 20-73. RAM Test Control Register (RTCTRL) [offset = 17Ch] 31 16 Reserved R-0 15 1 0 Reserved RTC R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-61. RAM Test Control Register (RTCTRL) Field Descriptions Bit 31-1 0 Field Reserved Value 0 RTC Description Read returns 0. Writes have no effect. RAM Test Control.
Control Registers and Control Packets www.ti.com 20.3.1.56 Debug Control Register (DCTRL) Figure 20-74. Debug Control Register (DCTRL) [offset = 180h] 31 29 28 24 23 17 16 Reserved CHNUM Reserved DMADBGS R-0 R-0 R-0 R/WC-0 15 1 0 Reserved DBGEN R-0 R/WC-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset Table 20-62.
Control Registers and Control Packets www.ti.com 20.3.1.57 Watch Point Register (WPR) Figure 20-75. Watch Point Register (WPR) [offset = 184h] 31 0 WP R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 20-63. Watch Point Register (WPR) Field Descriptions Bit 31-0 Field Description WP Watch point. Note: These bits can only be set when using a debugger. This register is only reset by a test reset (nTRST). A 32-bit address can be programmed into this register as a watch point.
Control Registers and Control Packets www.ti.com 20.3.1.59 FIFO A Active Channel Source Address Register (FAACSADDR) Figure 20-77. FIFO A Active Channel Source Address Register (FAACSADDR) [offset = 18ch] 31 0 FAACSA R-0 LEGEND: R = Read only; -n = value after reset Table 20-65. FIFO A Active Channel Source Address Register (FAACSADDR) Field Descriptions Bit 31-0 Field Description FAACSA FIFO B Active Channel Source Address.
Control Registers and Control Packets www.ti.com 20.3.1.62 FIFO B Active Channel Source Address Register (FBACSADDR) Figure 20-80. FIFO B Active Channel Source Address Register (FBACSADDR) [offset = 198h] 31 0 FBACSA R-0 LEGEND: R = Read only; -n = value after reset Table 20-68. FIFO B Active Channel Source Address Register (FBACSADDR) Field Descriptions Bit 31-0 Field Description FBACSA FIFO B Active Channel Source Address.
Control Registers and Control Packets www.ti.com 20.3.1.65 ECC Control Register (DMAPECR) Figure 20-83. ECC Control Register (DMAPECR) [offset = 1A8h] 31 15 15 9 16 Reserved ERRA R-0 R/WP-0 8 7 4 3 0 Reserved TEST Reserved ECC_ENA R-0 R/WP-0 R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 20-71.
Control Registers and Control Packets www.ti.com 20.3.1.66 DMA ECC Error Address Register (DMAPAR) Figure 20-84. DMA ECC Error Address Register (DMAPAR) [offset = 1ACh] 31 25 24 23 16 Reserved EDFLAG Reserved R-0 R-0 R-0 15 12 11 0 Reserved ERRORADDRESS R-0 R-X LEGEND: R/W = Read/Write; R = Read only; X= Undefined; -n = value after reset . Table 20-72.
Control Registers and Control Packets www.ti.com 20.3.1.67 DMA Memory Protection Control Register 1 (DMAMPCTRL1) Figure 20-85.
Control Registers and Control Packets www.ti.com Table 20-73. DMA Memory Protection Control Register 1 (DMAMPCTRL1) Field Descriptions (continued) Bit 15-13 12 11 10-9 8 7-5 4 3 2-1 0 Field Reserved Value 0 INT1AB Reads return 0. Writes have no effect. Interrupt assignment of region 1 to Group A or Group B. 0 The interrupt is routed to the VIM (Group A). 1 The interrupt is routed to the second CPU (Group B). INT1ENA Interrupt enable of region 1. 0 The interrupt is disabled.
Control Registers and Control Packets www.ti.com 20.3.1.68 DMA Memory Protection Status Register 1 (DMAMPST1) Figure 20-86. DMA Memory Protection Status Register 1 (DMAMPST1) [offset = 1B4h] 31 25 24 23 17 16 Reserved REG3FT Reserved REG2FT R-0 R/WC-0 R-0 R/WC-0 15 9 8 7 1 0 Reserved REG1FT Reserved REG0FT R-0 R/WC-0 R-0 R/WC-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20-74.
Control Registers and Control Packets www.ti.com 20.3.1.69 DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) Figure 20-87. DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) [offset = 1B8h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-75.
Control Registers and Control Packets www.ti.com 20.3.1.71 DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) Figure 20-89. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) [offset = 1C0h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-77.
Control Registers and Control Packets www.ti.com 20.3.1.73 DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) Figure 20-91. DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) [offset = 1C8h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-79.
Control Registers and Control Packets www.ti.com 20.3.1.75 DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) Figure 20-93. DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) [offset = 1D0h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-81.
Control Registers and Control Packets www.ti.com 20.3.1.77 DMA Memory Protection Control Register 2 (DMAMPCTRL2) Figure 20-95.
Control Registers and Control Packets www.ti.com Table 20-83. DMA Memory Protection Control Register 2 (DMAMPCTRL2) Field Descriptions (continued) Bit 15-13 12 11 10-9 8 7-5 4 3 2-1 0 752 Field Reserved Value 0 INT5AB Reads return 0. Writes have no effect. Interrupt assignment of region 5 to Group A or Group B. 0 The interrupt is routed to the VIM (Group A). 1 The interrupt is routed to the second CPU (Group B). INT5ENA Interrupt enable of region 5. 0 The interrupt is disabled.
Control Registers and Control Packets www.ti.com 20.3.1.78 DMA Memory Protection Status Register 2 (DMAMPST2) Figure 20-96. DMA Memory Protection Status Register 2 (DMAMPST2) [offset = 1DCh] 31 25 24 23 17 16 Reserved REG7FT Reserved REG6FT R-0 R/WC-0 R-0 R/WC-0 15 9 8 7 1 0 Reserved REG5FT Reserved REG4FT R-0 R/WC-0 R-0 R/WC-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20-84.
Control Registers and Control Packets www.ti.com 20.3.1.79 DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) Figure 20-97. DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) [offset = 1E0h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-85.
Control Registers and Control Packets www.ti.com 20.3.1.81 DMA Memory Protection Region 5 Start Address Register (DMAMPR5S) Figure 20-99. DMA Memory Protection Region 5 Start Address Register (DMAMPR5S) [offset = 1E8h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-87.
Control Registers and Control Packets www.ti.com 20.3.1.83 DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) Figure 20-101. DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) [offset = 1F0h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-89.
Control Registers and Control Packets www.ti.com 20.3.1.85 DMA Memory Protection Region 7 Start Address Register (DMAMPR7S) Figure 20-103. DMA Memory Protection Region 7 Start Address Register (DMAMPR7S) [offset = 1F8h] 31 0 STARTADDRESS R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-91.
Control Registers and Control Packets www.ti.com 20.3.1.87 DMA Single Bit ECC Control Register (DMASECCCTRL) Figure 20-105. DMA Single Bit ECC Control Register (DMASECCCTRL) [offset = 228h] 31 17 15 12 16 Reserved SBERR R-0 R/WCP-0 11 8 7 4 3 0 Reserved SBE_EVT_EN Reserved EDACMODE R-0 R/WP-5h R-0 R/WP-Ah LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20-93.
Control Registers and Control Packets www.ti.com 20.3.1.88 DMA ECC Single Bit Error Address Register (DMAECCSBE) Figure 20-106. DMA ECC Single Bit Error Address Register (DMAECCSBE) [offset = 230h] 31 16 Reserved R-0 15 12 11 0 Reserved ERRORADDRESS R-0 R-X LEGEND: R/W = Read/Write; R = Read only; X= Undefined; -n = value after reset . Table 20-94.
Control Registers and Control Packets www.ti.com 20.3.1.89 FIFO A Status Register (FIFOASTAT) Figure 20-107. FIFO A Status Register (FIFOASTAT) [offset = 240h] 31 0 FFACH[31:0] R-0 LEGEND: R = Read only; -n = value after reset Table 20-95. FIFO A Status Register (FIFOASTAT) Field Descriptions Bit 31-0 Field Value FFACH[n] Description Status of DMA channel running using FIFO A. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Control Registers and Control Packets www.ti.com 20.3.1.91 DMA Request Polarity Select Register 1 (DMAREQPS1) Figure 20-109. DMA Request Polarity Select Register (DMAREQPS1) [offset = 330h] 31 0 DMAREQPS[63:32] R/WP-0 LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset Table 20-97.
Control Registers and Control Packets www.ti.com 20.3.1.93 Transaction Parity Error Event Control Register (TERECTRL) Figure 20-111. Transaction Parity Error Event Control Register (TERECTRL) [offset = 340h] 31 17 16 Reserved TER_ERR R-0 R/WC-0 15 4 3 0 Reserved TER_EN R-0 R/WP-Ah LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20-99.
Control Registers and Control Packets www.ti.com 20.3.1.95 TER Event Channel Offset Register (TERROFFSET) Figure 20-113. TER Event Channel Offset Register (TERROFFSET) [offset = 348h] 31 16 Reserved R-0 15 8 7 6 5 0 Reserved sbz sbz TER_OFF R-0 R-0 R-0 R-x LEGEND: R = Read only; -n = value after reset Table 20-101. TER Event Channel Offset Register (TERROFFSET) Field Descriptions Bit Field Value Description 31-8 Reserved 0 Read returns 0. Writes have no effect.
Control Registers and Control Packets www.ti.com 20.3.2 Channel Configuration The channel configuration is defined by the channel control packet: channel control, transfer count, index pointers, source/destination address. • It is stored in local RAM, which is protected by parity. • Each control packet contains a total of nine fields. • The first six fields are programmable, while the last three fields are read only. • The RAM is accessible by queue A and queue B state machines as well as CPU.
Control Registers and Control Packets www.ti.com 20.3.2.3 Initial Transfer Count Register (ITCOUNT) Figure 20-116. Initial Transfer Count Register (ITCOUNT) [offset = 08h] 31 29 28 16 Reserved IFTCOUNT R-X R/WP-X 15 13 12 0 Reserved IETCOUNT R-X R/WP-X LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown Table 20-104.
Control Registers and Control Packets www.ti.com Table 20-105. Channel Control Register (CHCTRL) Field Descriptions Bit Field 31-22 Reserved 21-16 CHAIN Value 0 Description Reads are undefined. Writes have no effect. Next channel to be triggered. At the end of the programmed number of frames, the specified channel will be triggered. Note: The programmer must program the CHAIN bits before initiating a DMA transfer. 0 No channel is selected. 1h Channel 0 is selected.
Control Registers and Control Packets www.ti.com 20.3.2.5 Element Index Offset Register (EIOFF) Figure 20-118. Element Index Offset Register (EIOFF) [offset = 14h] 31 29 28 16 Reserved EIDXD R-X R/WP-X 15 13 12 0 Reserved EIDXS R-X R/WP-X LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown Table 20-106.
Control Registers and Control Packets www.ti.com 20.3.2.7 Current Source Address Register (CSADDR) Figure 20-120. Current Source Address Register (CSADDR) [offset = 800h] 31 0 CSADDR R-X LEGEND: R = Read only; -n = value after reset; X = Unknown Table 20-108. Current Source Address Register (CSADDR) Field Descriptions Bit 31-0 Field Description CSADDR Current source address. These bits contain the current working absolute 32-bit source address (physical).
Chapter 21 SPNU562 – May 2014 External Memory Interface (EMIF) This chapter describes the external memory Interface (EMIF). Topic 21.1 21.2 21.3 21.4 ........................................................................................................................... Introduction ..................................................................................................... EMIF Module Architecture ................................................................................. Registers ...
Introduction www.ti.com 21.1 Introduction 21.1.1 Purpose of the Peripheral This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 16-bit data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external devices including: • Single data rate (SDR) SDRAM • Asynchronous devices including NOR Flash and SRAM The most common use for the EMIF is to interface with both a flash device and an SDRAM device simultaneously.
Introduction www.ti.com 21.1.3 Functional Block Diagram Figure 21-1 illustrates the connections between the EMIF and its internal requesters, along with the external EMIF pins. Section 21.2.2 contains a description of the entities internal to the SoC that can send requests to the EMIF, along with their prioritization. Section 21.2.3 describes the EMIF external pins and summarizes their purpose when interfacing with SDRAM and asynchronous devices. Figure 21-1.
EMIF Module Architecture www.ti.com 21.2 EMIF Module Architecture This section provides details about the architecture and operation of the EMIF. Both, SDRAM and asynchronous Interface are covered, along with other system-related issues such as clock control. 21.2.1 EMIF Clock Control The EMIF clock is output on the EMIF_CLK pin and should be used when interfacing to external SDRAM devices. The EMIF module gets the VCLK3 clock domain as the input.
EMIF Module Architecture www.ti.com Table 21-1. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories (continued) Pins(s) I/O Description EMIF_nWE O Active-low write enable. When interfacing to SDRAM, this pin is connected to the nWE pin of the SDRAM and is used to send commands to the device. When interfacing to an asynchronous device, this pin provides a signal which is active-low during the strobe period of an asynchronous write access cycle. Table 21-2.
EMIF Module Architecture www.ti.com 21.2.5 SDRAM Controller and Interface The EMIF can gluelessly interface to most standard SDR SDRAM devices and supports such features as self refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
EMIF Module Architecture www.ti.com Figure 21-2. Timing Waveform of SDRAM PRE Command PRE EMIF_CLK EMIF_nCS[0] EMIF_nDQM Bank EMIF_BA EMIF_A[10]=0 EMIF_A EMIF_nRAS EMIF_nCAS EMIF_nWE 21.2.5.2 Interfacing to SDRAM The EMIF supports a glueless interface to SDRAM devices with the following characteristics: • Pre-charge bit is A[10] • The number of column address bits is 8, 9, 10, or 11. • The number of row address bits is 13, 14, 15, or 16. • The number of internal banks is 1, 2, or 4.
EMIF Module Architecture www.ti.com Figure 21-4. EMIF to 512K × 16 × 2 bank SDRAM Interface EMIF EMIF_nCS[0] EMIF_nCAS EMIF_nRAS EMIF_nWE EMIF_CLK EMIF_CKE EMIF_BA[0] nCE nCAS nRAS nWE CLK CKE BA[0] EMIF_A[10:0] EMIF_nDQM[0] EMIF_nDQM[1] EMIF_D[15:0] SDRAM 512 x 16 x 2 bank A[10:0] LDQM UDQM DQ[15:0] Table 21-6.
EMIF Module Architecture www.ti.com 21.2.5.3 SDRAM Configuration Registers The operation of the EMIF's SDRAM interface is controlled by programming the appropriate configuration registers. This section describes the purpose and function of each configuration register, but Section 21.3 should be referred for a more detailed description of each register, including the default registers values and bit-field positions.
EMIF Module Architecture www.ti.com Table 21-9. Description of the SDRAM Timing Register (SDTIMR) Parameter Description T_RFC SDRAM Timing Parameters. These fields configure the EMIF to comply with the AC timing requirements of the attached SDRAM devices. This allows the EMIF to avoid violating SDRAM timing constraints and to more efficiently schedule its operations. More details about each of these parameters can be found in the register description in Section 21.3.6.
EMIF Module Architecture www.ti.com Table 21-11. SDRAM LOAD MODE REGISTER Command EMIF_A[9:7] EMIF_A[6:4] EMIF_A[3] EMIF_A[2:0] 0 (Write bursts are of the programmed burst length in EMIF_A[2:0]) These bits control the CAS latency of the SDRAM and are set according to CL field in the SDRAM configuration register (SDCR) as follows: • If CL = 2, EMIF_A[6:4] = 2h (CAS latency = 2) • If CL = 3, EMIF_A[6:4] = 3h (CAS latency = 3) 0 (Sequential Burst Type.
EMIF Module Architecture www.ti.com 4. Program SDCR to match the characteristics of the attached SDRAM device. This will cause the autoinitialization sequence in Section 21.2.5.4 to be re-run with the new value of RR. 5. Perform a read from the SDRAM to assure that step 5 of this procedure will occur after the initialization process has completed. Alternatively, wait for 200 μs instead of performing a read. 6. Finally, program the RR field to match that of the attached device's refresh interval.
EMIF Module Architecture www.ti.com 21.2.5.6.1 Determining the Appropriate Value for the RR Field The value that should be programmed into the RR field of SDRCR can be calculated by using the frequency of the EMIF_CLK signal (fEMIF_CLK) and the required refresh rate of the SDRAM (fRefresh). The following formula can be used: RR = fEMIF_CLK / fRefresh The SDRAM datasheet often communicates the required SDRAM Refresh Rate in terms of the number of REFR commands required in a given time interval.
EMIF Module Architecture www.ti.com 21.2.5.8 Power Down Mode To support low-power modes, the EMIF can be requested to issue a POWER DOWN command to the SDRAM by setting the PD bit in the SDRAM configuration register (SDCR). When this bit is set, the EMIF will continue normal operation until all outstanding memory access requests have been serviced and the SDRAM refresh backlog (if there is one) has been cleared. At this point the EMIF will enter the powerdown state.
EMIF Module Architecture www.ti.com 21.2.5.9 SDRAM Read Operation When the EMIF receives a read request to SDRAM from one of the requesters listed in Section 21.2.2, it performs one or more read access cycles. A read access cycle begins with the issuing of the ACTV command to select the desired bank and row of the SDRAM device. After the row has been opened, the EMIF proceeds to issue a READ command while specifying the desired bank and column address.
EMIF Module Architecture www.ti.com 21.2.5.10 SDRAM Write Operations When the EMIF receives a write request to SDRAM from one of the requesters listed in Section 21.2.2, it performs one or more write-access cycles. A write-access cycle begins with the issuing of the ACTV command to select the desired bank and row of the SDRAM device. After the row has been opened, the EMIF proceeds to issue a WRT command while specifying the desired bank and column address.
EMIF Module Architecture www.ti.com 21.2.5.11 Mapping from Logical Address to EMIF Pins When the EMIF receives an SDRAM access request, it must convert the address of the access into the appropriate signals to send to the SDRAM device. The details of this address mapping are shown in Table 21-13 for 16-bit operation.
EMIF Module Architecture www.ti.com 21.2.6 Asynchronous Controller and Interface The EMIF easily interfaces to a variety of asynchronous devices including NOR Flash, NAND Flash, and SRAM. It can be operated in two major modes (see Table 21-14): • Normal Mode • Select Strobe Mode Table 21-14. Normal Mode vs.
EMIF Module Architecture www.ti.com Of special note is the connection between the EMIF and the external device's address bus. The EMIF address pin EMIF_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when interfacing to a 16-bit or 8-bit asynchronous device, the EMIF_BA[1] and EMIF_BA[0] pins provide the least-significant bits of the halfword or byte address, respectively.
EMIF Module Architecture www.ti.com 21.2.6.2 Accessing Larger Asynchronous Memories The device has 22 dedicated EMIF address lines. If a device such as a large asynchronous flash needs to be attached to the EMIF, then GPIO pins may be used to control the flash device’s upper address lines. 21.2.6.3 Configuring the EMIF for Asynchronous Accesses The operation of the EMIF's asynchronous interface can be configured by programming the appropriate register fields.
EMIF Module Architecture www.ti.com Table 21-15. Description of the Asynchronous m Configuration Register (CEnCFG) (continued) Parameter Description ASIZE Asynchronous Device Bus Width. This field determines the data bus width of the asynchronous interface in the following way: • ASIZE = 0 selects an 8-bit bus • ASIZE = 1 selects a 16-bit bus The configuration of ASIZE determines the function of the EMIF_A and EMIF_BA pins as described in Section 21.2.6.1.
EMIF Module Architecture www.ti.com Table 21-18. Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR) (continued) Parameter Description AT_MASK_CLR Asynchronous Timeout Mask Clear. Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout occurs. 21.2.6.4 Read and Write Operations in Normal Mode Normal Mode is the asynchronous interface's default mode of operation.
EMIF Module Architecture www.ti.com Table 21-19. Asynchronous Read Operation in Normal Mode (continued) Time Interval Pin Activity in Normal Mode End of the hold At the end of the hold period: period • The address pins EMIF_A and EMIF_BA become invalid • EMIF_nCS[4:2] rises (if no more operations are required to complete the current request) EMIF may be required to issue additional read operations to a device with a small data bus width in order to complete an entire word access.
EMIF Module Architecture www.ti.com 21.2.6.4.2 Asynchronous Write Operations (Normal Mode) NOTE: During an entire asynchronous write operation, the EMIF_nOE pin is driven high. An asynchronous write is performed when any of the requesters mentioned in Section 21.2.2 request a write to memory in the asynchronous bank of the EMIF. After the request is received, a write operation is initiated once it becomes the EMIF's highest priority task, according to the priority scheme detailed in Section 21.2.13.
EMIF Module Architecture www.ti.com Figure 21-11.
EMIF Module Architecture www.ti.com 21.2.6.5 Read and Write Operation in Select Strobe Mode Select Strobe Mode is the EMIF's second mode of operation. It is selected when the SS bit of the asynchronous n configuration register (CEnCFG) is set to 1. In this mode, the EMIF_nDQM pins operate as byte enables and the EMIF_nCS[n] (n = 2, 3, or 4) pin is only active during the strobe period of an access cycle. Section 21.2.6.4.1 and Section 21.2.6.4.
EMIF Module Architecture www.ti.com Figure 21-12.
EMIF Module Architecture www.ti.com 21.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode) NOTE: During the entirety of an asynchronous write operation, the EMIF_nOE pin is driven high. An asynchronous write is performed when any of the requesters mentioned in Section 21.2.2 request a write to memory in the asynchronous bank of the EMIF.
EMIF Module Architecture www.ti.com Figure 21-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode Setup 2 Strobe 3 Hold 2 EMIF_CLK EMIF_nCS[n] EMIF_nDQM Byte enables EMIF_A/EMIF_BA Address Data EMIF_D EMIF_nOE EMIF_nWE 21.2.6.6 Extended Wait Mode and the EMIF_nWAIT Pin The EMIF supports the Extend Wait Mode. This is a mode in which the external asynchronous device may assert control over the length of the strobe period.
EMIF Module Architecture www.ti.com 21.2.6.7 NOR Flash Page Mode EMIF supports Page mode reads for NOR Flash on its asynchronous memory chip selects. This mode can be enabled by writing a 1 to the CSn_PG_MD_EN (n = 2, 3, or 4) field in the Page Mode Control register for the chip select in consideration. Whenever Page Mode for reads is enabled for a particular chip select, the page size for the device connected must also be programmed in the CSn_PG_SIZE field of the Page Mode Control register.
EMIF Module Architecture www.ti.com 21.2.8 Reset and Initialization Considerations The EMIF memory controller has two active-low reset signals, CHIP_RST_n and MOD_G_RST_n. Both these reset signals are driven by the device system reset signal. This device does not offer the flexibility to reset just the EMIF state machine without also resetting the EMIF controller's memory-mapped registers.
EMIF Module Architecture www.ti.com Table 21-23. Interrupt Monitor and Control Bit Fields Register Name Bit Name Description EMIF interrupt raw register (INTRAW) WR This bit is set when an rising edge on the EMIF_nWAIT signal occurs. Writing a 1 clears the WR bit as well as the WR_MASKED bit in INTMSK. AT This bit is set when an asynchronous timeout occurs. Writing a 1 clears the AT bit as well as the AT_MASKED bit in INTMSK. LT This bit is set when an unsupported addressing mode is used.
EMIF Module Architecture www.ti.com 21.2.13 Priority and Arbitration Section 21.2.2 describes the external prioritization and arbitration among requests from different sources within the microcontroller. The result of this external arbitration is that only one request is presented to the EMIF at a time. Once the EMIF completes a request, the external arbiter then provides the EMIF with the next pending request.
EMIF Module Architecture www.ti.com 21.2.14 System Considerations This section describes various system considerations to keep in mind when operating the EMIF. 21.2.14.1 Asynchronous Request Times In a system that interfaces to both SDRAM and asynchronous memory, the asynchronous requests must not take longer than the smaller of the following two values: • tRAS (typically 120 μs) - to avoid violating the maximum time allowed between issuing an ACTV and PRE command to the SDRAM.
EMIF Module Architecture www.ti.com 21.2.15 Power Management Power dissipation from the EMIF memory controller may be managed by following methods: • Self-refresh mode • Power-down mode • Gating input clocks to the module off Gating input clocks off to the EMIF memory controller achieves higher power savings when compared to the power savings of self-refresh or power down mode. The input clock VCLK3 can be turned off through the use of the Global Clock Module (GCM).
Registers www.ti.com 21.3 Registers The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers (MMRs). Table 21-24 lists the memory-mapped registers for the EMIF. NOTE: All EMIF MMRs, except SDCR, support only word (32-bit) accesses. Performing a byte (8bit) or halfword (16-bit) write to these registers results in undefined behavior. The SDCR is byte writable to allow the setting of the SR, PD and PDWR bits without triggering the SDRAM initialization sequence.
Registers www.ti.com 21.3.2 Asynchronous Wait Cycle Configuration Register (AWCC) The asynchronous wait cycle configuration register (AWCC) is used to configure the parameters for extended wait cycles. Both the polarity of the EMIF_nWAIT pin(s) and the maximum allowable number of extended wait cycles can be configured. The AWCC is shown in Figure 21-16 and described in Table 2126.
Registers www.ti.com 21.3.3 SDRAM Configuration Register (SDCR) The SDRAM configuration register (SDCR) is used to configure various parameters of the SDRAM controller such as the number of internal banks, the internal page size, and the CAS latency to match those of the attached SDRAM device. In addition, this register is used to put the attached SDRAM device into Self-Refresh mode. The SDCR is shown in Figure 21-17 and described in Table 21-27.
Registers www.ti.com Table 21-27. SDRAM Configuration Register (SDCR) Field Descriptions (continued) Bit 11-9 Field Value CL CAS Latency. This field defines the CAS latency to be used when accessing connected SDRAM devices. A 1 must be simultaneously written to the BIT11_9LOCK bit field of this register in order to write to the CL bit field. Writing to this field triggers the SDRAM initialization sequence.
Registers www.ti.com 21.3.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) The asynchronous n configuration registers (CE2CFG, CE3CFG, CE4CFG, and CE5CFG) are used to configure the shaping of the address and control signals during an access to asynchronous memory connected to CS2, CS3, CS4, and CS5, respectively. CS5 is not available on this device. It is also used to program the width of asynchronous interface and to select from various modes of operation.
Registers www.ti.com 21.3.6 SDRAM Timing Register (SDTIMR) The SDRAM timing register (SDTIMR) is used to program many of the SDRAM timing parameters. Consult the SDRAM datasheet for information on the appropriate values to program into each field. The SDTIMR is shown in Figure 21-20 and described in Table 21-30. Figure 21-20.
Registers www.ti.com 21.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) The SDRAM self refresh exit timing register (SDSRETR) is used to program the amount of time between when the SDRAM exits Self-Refresh mode and when the EMIF issues another command. The SDSRETR is shown in Figure 21-21 and described in Table 21-31. Figure 21-21.
Registers www.ti.com 21.3.8 EMIF Interrupt Raw Register (INTRAW) The EMIF interrupt raw register (INTRAW) is used to monitor and clear the EMIF’s hardware-generated Asynchronous Timeout Interrupt. The AT bit in this register will be set when an Asynchronous Timeout occurs regardless of the status of the EMIF interrupt mask set register (INTMSKSET) and EMIF interrupt mask clear register (INTMSKCLR). Writing a 1 to this bit will clear it.
Registers www.ti.com 21.3.9 EMIF Interrupt Masked Register (INTMSK) Like the EMIF interrupt raw register (INTRAW), the EMIF interrupt masked register (INTMSK) is used to monitor and clear the status of the EMIF’s hardware-generated Asynchronous Timeout Interrupt. The main difference between the two registers is that when the AT_MASKED bit in this register is set, an active-high pulse will be sent to the CPU interrupt controller.
Registers www.ti.com 21.3.10 EMIF Interrupt Mask Set Register (INTMSKSET) The EMIF interrupt mask set register (INTMSKSET) is used to enable the Asynchronous Timeout Interrupt. If read as 1, the AT_MASKED bit in the EMIF interrupt masked register (INTMSK) will be set and an interrupt will be generated when an Asynchronous Timeout occurs. If read as 0, the AT_MASKED bit will always read 0 and no interrupt will be generated when an Asynchronous Timeout occurs.
Registers www.ti.com 21.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR) The EMIF interrupt mask clear register (INTMSKCLR) is used to disable the Asynchronous Timeout Interrupt. If read as 1, the AT_MASKED bit in the EMIF interrupt masked register (INTMSK) will be set and an interrupt will be generated when an Asynchronous Timeout occurs. If read as 0, the AT_MASKED bit will always read 0 and no interrupt will be generated when an Asynchronous Timeout occurs.
Registers www.ti.com 21.3.12 Page Mode Control Register (PMCR) The page mode control register (PMCR) is shown in Figure 21-26 and described in Table 21-36. This register is configured when using NOR Flash page mode. Figure 21-26.
Example Configuration www.ti.com 21.4 Example Configuration This section presents an example of interfacing the EMIF to both an SDR SDRAM device and an asynchronous flash device. 21.4.1 Hardware Interface Figure 21-27 shows the hardware interface between the EMIF, a Samsung K4S641632H-TC(L)70 64Mb SDRAM device, and two SHARP LH28F800BJE-PTTL90 8Mb Flash memory. The connection between the EMIF and the SDRAM is straightforward, but the connection between the EMIF and the flash deserves a detailed look.
Example Configuration www.ti.com Figure 21-27.
Example Configuration www.ti.com 21.4.2.1.2 SDRAM Timing Register (SDTIMR) Settings for the EMIF to K4S641632H-TC(L)70 Interface The fields of the SDRAM timing register (SDTIMR) should be programmed first as described in Table 2138 to satisfy the required timing parameters for the K4S641632H-TC(L)70. Based on these calculations, a value of 6111 4610h should be written to SDTIMR. Figure 21-28 shows a graphical description of how SDTIMR should be programmed. Table 21-38.
Example Configuration www.ti.com 21.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDSRETR) Settings for the EMIF to K4S641632HTC(L)70 Interface The SDRAM self refresh exit timing register (SDSRETR) should be programmed second to satisfy the tXSR timing requirement from the K4S641632H-TC(L)70 datasheet. Table 21-39 shows the calculation of the proper value to program into the T_XS field of this register. Based on this calculation, a value of 6h should be written to SDSRETR.
Example Configuration www.ti.com 21.4.2.1.5 SDRAM Configuration Register (SDCR) Settings for the EMIF to K4S641632H-TC(L)70 Interface Finally, the fields of the SDRAM configuration register (SDCR) should be programmed as described in Table 21-37 to properly interface with the K4S641632H-TC(L)70 device. Based on these settings, a value of 4720h should be written to SDCR. Figure 21-31 shows how SDCR should be programmed. The EMIF is now ready to perform read and write accesses to the SDRAM. Table 21-41.
Example Configuration www.ti.com 21.4.2.2 Configuring the Flash Interface This section describes how to configure the EMIF to interface with the two of SHARP LH28F800BJEPTTL90 8Mb Flash memory with a clock frequency of fEMIF_CLK = 100 MHz. The example assumes that one flash is connected to EMIF_nCS2 and the other to EMIF_nCS3. 21.4.2.2.
Example Configuration www.ti.
Example Configuration www.ti.com LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms Hold Setup Strobe tAVAV EMIF_CLK tELEH EMIF_nCS[n] EMIF_A/ EMIF_BA Address EMIF_D Data EMIF_nWE The R_STROBE field should be set to meet the following equation: R_STROBE >= (tD + tELQV + tSU) × fEMIF_CLK - 1 R_STROBE >= (7 ns + 90 ns + 6.5 ns) × 100 MHz - 1 R_STROBE >= 9.
Example Configuration www.ti.
Chapter 22 SPNU562 – May 2014 Analog To Digital Converter (ADC) Module This chapter describes the analog to digital converter (ADC) interface module. Topic 22.1 22.2 22.3 ........................................................................................................................... Page Overview ........................................................................................................ 826 Basic Operation..........................................................................
Overview www.ti.com 22.1 Overview This microcontrollers implements up to two instances of the ADC module.
Overview www.ti.com 22.1.1 Introduction This section presents a brief functional description of the analog-to-digital converter (ADC) module. Figure 22-2 shows the components of the ADC module. Figure 22-2.
Overview www.ti.com 22.1.1.1 Input Multiplexor The input multiplexor (MUX) connects the selected input channel to the AIN input of the ADC core. The ADC1 module supports up to 32 inputs as shown in Figure 22-2. The ADC2 module supports up to 25 inputs. The sequencer selects the channel to be converted. Enabling the enhanced channel selection mode also allows one or more of the analog input channels to be connected to the output of an external analog switch or multiplexor. 22.1.1.
Basic Operation www.ti.com 22.1.1.4 Sequencer The sequencer coordinates the operations of the ADC, including the input multiplexor, the ADC core, and the result memory. In addition, the logic of the sequencer sets the status register flags when the conversion is ongoing, stopped, or finished. All the features of the sequencer are discussed in detail in the following sections of this document. 22.1.1.
Basic Operation www.ti.com 22.2.1.3 How to Set Up the Input Channel Acquisition Time The signal acquisition time for each group is separately configurable using the ADG1SAMP[11:0], ADG2SAMP[11:0], and ADEVSAMP[11:0] registers. The acquisition time is specified in terms of ADCLK cycles and ranges from a minimum of 2 ADCLK cycles to a maximum of 4098 ADCLK cycles. For example, Group1 acquisition time, tACQG1 = G1SAMP[11:0] + 2, in ADCLK cycles.
Basic Operation www.ti.com An Event Group conversion starts when at least one channel is selected for conversion in this group, and when the defined event trigger occurs. If any conversion group is configured to be in a continuous conversion mode, then it needs to only be triggered once. All the channels selected for conversion in that group will be converted repeatedly. 22.2.1.
Basic Operation www.ti.com 22.2.1.9.1 Reading Conversion Results from a FIFO The conversion results for each group can be accessed via a range of addresses provided to facilitate the use of the ARM Cortex-R4 CPU’s Load-Multiple (LDM) instruction. A single read performed using the LDR instruction can also be used to read out a single conversion result. The results are read out from the group’s memory region as a FIFO queue by reading from any location inside this address range.
Basic Operation www.ti.com 22.2.1.9.2 Reading Conversion Results Directly from the Conversion Results’ Memory The conversion result memory is part of the device’s memory map. The base address for the ADC1 result memory is FF3E 0000h and for the ADC2 result memory is FF3A 0000h. Figure 22-6.
Basic Operation www.ti.com 22.2.1.9.3 Example Suppose that channels 0, 1, and 2 are selected for conversion in the Event Group, channels 4, 7, and 8 are selected for conversion in group 1, and channels 3, 5, and 6 are selected for conversion in group 2. The conversion results will get stored in the three memory regions as shown in Figure 22-9. Suppose that the CPU wants to read out the results for the Event Group from a FIFO queue.
Basic Operation www.ti.com 22.2.1.10 How to Stop a Conversion A group’s conversion can be stopped by clearing the group’s channel select register. 22.2.1.11 Example Sequence for Basic Configuration of ADC Module The following sequence is necessary to configure the ADC to convert channels 0, 2, 4, and 8 in singleconversion mode using Group1: 1. Write 0 to the Reset Control Register (ADRSTCR) to release the module from the reset state 2.
Basic Operation www.ti.com 22.2.2 Advanced Conversion Group Configuration Options Figure 22-10 shows the operating mode control registers and the status registers for each of the three conversion groups. The register addresses shown are offsets from the base address. The ADC1 register frame base address is FFF7 C000h and the ADC2 register frame base address is FFF7 C200h. Figure 22-10.
Basic Operation www.ti.com 22.2.2.1 Group Trigger Options The Group1 and Group2 operating mode control registers have an extra control bit: HW_TRIG. This bit configures the group to be hardware event-triggered instead of software-triggered, which is the default. When a group is configured to be event-triggered, the group conversion starts when at least one channel is selected for conversion in this group, and when the defined event trigger occurs.
Basic Operation • www.ti.com Maximum Number of Conversions A MAX_COUNT register for each conversion group stores the maximum number of conversions to be performed before the index into a group's LUT is reset to zero. This register can be programmed to a value between 0 and 31.
Basic Operation www.ti.com 22.2.2.2.2.2 Example ADC Conversion Sequence Using Enhanced Channel Selection Mode Consider the example conversion Group1 configuration shown in Figure 22-12. Only bits 0 and 31 of ADG1SEL are set. Assume that all other bits in this register are zeros. In case of the default sequential channel selection mode, the write to the ADG1SEL register would cause the Group1 conversions to start with channel 0 followed by channel 31.
Basic Operation www.ti.com Now suppose that the application has enabled the enhanced channel selection mode for Group1 with the G1_MAX_COUNT register configured to be 3. Also suppose that the application has programmed the Group1 LUT as shown in Figure 22-12. Now suppose that the application triggers Group1 conversions by writing 0x80000001 to ADG1SEL, that is, bits 0 and 31 are set and all others are zeros.
Basic Operation www.ti.com 22.2.2.3 Single or Continuous Conversion Modes The EV_MODE, G1_MODE, and G2_MODE bits are used to select between either single or continuous conversion mode for each of the three groups. 22.2.2.3.1 Single Conversion Mode A conversion group configured to be in single-conversion mode gets serviced only once by the ADC for each group trigger.
Basic Operation www.ti.com Examples of conversion group priority: • If an Event Group conversion is ongoing in single conversion sequence mode and Group2 and Group1 conversions are requested, then the ADC will finish conversion of channels selected in Event Group, then switch over to converting channels selected in Group1, and then convert channels selected in Group2.
Basic Operation www.ti.com 22.2.2.7 Conversion Result Size on Reading: 8-bit, 10-bit, or 12-bit Some applications do not need the full 12-bit resolution of the ADC modules on the device and can work with 8-bit or 10-bit conversion results. 22.2.2.7.1 ADC Configured in 12-bit Resolution The mode control register for each conversion group contains a field called DATA_FMT, which defines the format of the conversion result read out of the result RAM, when accessed as a FIFO.
Basic Operation www.ti.com 22.2.3 ADC Module Basic Interrupts This section describes the basic interrupts generated by the ADC module. 22.2.3.1 Group Conversion End Interrupt The ADC module sets the group’s conversion end flag (EV_END, G1_END, or G2_END) in that group’s interrupt flag register (ADEVINTFLG, ADG1INTFLG, ADG2INTFLG) when all the channels selected for conversion in that group are converted.
Basic Operation www.ti.com 22.2.4 ADC Module DMA Requests This section describes the capabilities of the ADC module to take advantage of the Platform DMA controller module. The ADC module can generate a DMA request under two conditions: 22.2.4.1 DMA Request for Each Conversion Result Written to the Results’ Memory In this mode, the ADC module will generate the first DMA request as soon as a conversion result gets written to the group’s results’ memory.
Basic Operation www.ti.com 22.2.5 ADC Magnitude Threshold Interrupts The ADC allows up to three magnitude threshold interrupts to be generated. The comparison parameters are programmed via the Magnitude Threshold Control Register (ADMAGINTxCR). 22.2.5.1 Magnitude Threshold Interrupt Configuration The following fields are configurable for each of the three available magnitude threshold interrupts: 1.
Basic Operation www.ti.com 22.2.6 ADC Special Modes The ADC module supports some special modes for diagnostics and power saving purposes. 22.2.6.1 ADC Error Calibration Mode The application program can activate a calibration sequence any time self-test mode is disabled (SELF_TEST = 0). This calibration sequence includes the conversion of an embedded calibration reference voltage followed by the calculation of an offset error correction value.
Basic Operation www.ti.com Table 22-2. Calibration Reference Voltages (1) CAL_EN BRIDGE_EN HILO S1 S2 S3 S4 S5 Reference Voltage 1 0 0 1 0 1 0 0 (ADREFHI × R1 + ADREFLO × R2) / (R1 + R2) 1 0 1 0 1 0 1 0 (ADREFLO × R1 + ADREFHI × R2) / (R1 + R2) 1 1 0 0 1 1 0 0 ADREFLO 1 1 1 1 0 0 1 0 ADREFHI 0 X X 0 0 0 0 1 Vin (1) The state of the switches in this table assumes that self-test mode is not enabled. When CAL_ST (ADCALCR.
Basic Operation www.ti.com At this point, the ADC can be configured for normal operation, and it corrects each digital result with the error correction value loaded in ADCALR. NOTE: Prevent ADC Calibration Data From Being Overwritten In calibration mode, the conversion result is written to ADCALR that overwrites any previous calibration data; therefore, the ADCALR register must be read before a new conversion is started. For no correction, a value of 0x0000 must be written to ADCALR.
Basic Operation www.ti.com Figure 22-14. Mid-point Value Calculation Digital Code (hex) FS 3FF * The Real function shown is a straight line between the ends points of the real staircase characteristic. 10-bit ADC’s Theoretical Transfer Function The Theoretical transfer function is for reference only.
Basic Operation www.ti.com Figure 22-15. Self-Test and Calibration Logic ADREFHI ADREFLO Self-test and calibration R1 ~ 5K R2 ~ 7K S3 S4 S1 S2 R1 R2 ADIN0 MUX Vin ADC Core S5 ADIN31 CALR ADCALR.9:0 ADDRx.16,9:0 In self-test mode, a test voltage defined by the HILO bit (ADCALCR.8) is provided to the ADC core input through a resistor (see Table 22-3). To change the test source, this bit can be toggled before any single conversion mode request.
Basic Operation www.ti.com Figure 22-16. Timing for Self-Test Mode Sample time doubled in self-test mode Sample time in normal operation mode Tsamp1 ADREFLO + ADINx Tsamp2 ADREFLO + ADINx Conversion of last value sampled Start ADREFHI Ext. Input AD_Core _In discharge of ext. cap charging of ext. cap ADREFLO time 22.2.6.2.
Basic Operation www.ti.com 22.2.6.3.2 Enhanced Power-Down Mode A bit in the ADC operating mode control register, IDLE_PWRDN (ADOPMODECR.4) enables the enhanced power-down mode of the ADC. Once this bit is set, the ADC module will power down the ADC core whenever there are no more ongoing or pending ADC conversions. The ADC core will be powered down regardless of the state of the POWERDOWN bit (ADOPMODECR.3).
Basic Operation www.ti.com 22.2.7 ADC Results’ RAM Special Features The following section describes some of the special features supported by the ADC module to enhance the results’ RAM testability and integrity. 22.2.7.1 ADC Results’ RAM Auto-Initialization The ADC module allows the application to auto-initialize the ADC results’ RAM to all zeros. The application must ensure that the ADC module is not in any of the conversion modes before triggering off the auto-initialization process.
Basic Operation www.ti.com Figure 22-18. ADC Memory Map in Parity Test Mode ADC1 BASE ADDRESS ADC2 0xFF3E0000 0xFF3A0000 Conversion word 0 0xFF3E0004 0xFF3A0004 Conversion word 1 0xFF3E0008 0xFF3A0008 Conversion word 2 0xFF3E01F8 0xFF3A01F8 Conversion word 62 0xFF3E00FC 0xFF3A00FC Conversion word 63 Reserved 0xFF3E1000 0xFF3A1000 Parity Bits 22.2.8 ADEVT Pin General Purpose I/O Functionality The AD1EVT pin for ADC1 and AD2EVT pin for ADC2 can be configured as general-purpose I/O signals.
Basic Operation www.ti.com Once the device power-on reset is released, the ADC module controls the state of the ADxEVT pin. • Pull control: The pull control can either be enabled or disabled by default (while system reset is active and after it is released). The actual default state of the pull control is specified in the device datasheet. The application can enable pull control by clearing the PDIS (pull control disable) bit in the ADEVTPDIS register.
ADC Registers www.ti.com 22.3 ADC Registers All registers in the ADC module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are allowed. The application must ensure that the reserved bits are always written as 0 to ensure software compatibility to future revisions of the module. Table 22-6 shows register address offsets from the base address of the ADC modules. The base address of ADC1 registers is FFF7 C000h and the base address of ADC2 registers is FFF7 C200h. Table 22-6.
ADC Registers www.ti.com Table 22-6. ADC Registers (continued) Offset 858 Acronym Register Description F8h ADG2EMUBUFFER ADC Group2 Results Emulation FIFO Register Section 22.3.42 Section FCh ADEVTDIR ADC ADEVT Pin Direction Control Register Section 22.3.43 100h ADEVTOUT ADC ADEVT Pin Output Value Control Register Section 22.3.44 104h ADEVTIN ADC ADEVT Pin Input Value Register Section 22.3.45 108h ADEVTSET ADC ADEVT Pin Set Register Section 22.3.
ADC Registers www.ti.com 22.3.1 ADC Reset Control Register (ADRSTCR) Figure 22-20 and Table 22-7 describe the ADRSTCR register. Figure 22-20. ADC Reset Control Register (ADRSTCR) [offset = 00] 31 1 0 Reserved RESET R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 22-7. ADC Reset Control Register (ADRSTCR) Field Descriptions Bit Field 31-1 Value Reserved 0 0 RESET Description Reads return zeros, writes have no effect.
ADC Registers www.ti.com Table 22-8. ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions (continued) Bit Field 24 COS Value Description This bit affects emulation operation only. It defines whether the ADC core clock (ADCLK) is immediately halted when the emulation system enters suspend mode or if it should continue operating normally.
ADC Registers www.ti.com 22.3.3 ADC Clock Control Register (ADCLOCKCR) Figure 22-22 and Table 22-9 describe the ADCLOCKCR register. Figure 22-22. ADC Clock Control Register (ADCLOCKCR) [offset = 08h] 31 5 4 0 Reserved PS R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-9. ADC Clock Control Register (ADCLOCKCR) Field Descriptions Bit Field 31-5 Reserved 4-0 PS Value 0 0-1Fh Description Reads return zeros, writes have no effect. ADC Clock Prescaler.
ADC Registers www.ti.com Table 22-10. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions Bit Field 31-25 24 Reserved Value 0 SELF_TEST Description Read returns 0. Writes have no effect. ADC Self Test Enable. When this bit is Set, either ADREFHI or ADREFLO is connected through a resistor to the selected input channel. The desired conversion mode is configured in the group mode control registers. For more details on the ADC Self Test Mode, refer to Section 22.2.6.2.
ADC Registers www.ti.com 22.3.5 ADC Event Group Operating Mode Control Register (ADEVMODECR) ADC Event Group Operating Mode Control Register (ADEVMODECR) is shown in Figure 22-24 and Figure 22-25, and described in Table 22-11. As shown, the format of the ADEVMODECR is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. Figure 22-24.
ADC Registers www.ti.com Table 22-11. ADC Event Group Operating Mode Control Register (ADEVMODECR) Field Descriptions Field Value Reserved 0 No Reset on ChnSel Description Reads return zeros, writes have no effect. No Event Group Results Memory Reset on New Channel Select. This bit determines whether the event group results’ RAM is reset whenever a non-zero value is written to the event group channel select register.
ADC Registers www.ti.com Table 22-11. ADC Event Group Operating Mode Control Register (ADEVMODECR) Field Descriptions (continued) Field Value EV_MODE Description Event Group Conversion Mode. This bit defines whether the input channels selected for conversion in the Event Group are converted only once per trigger, or are continuously converted.
ADC Registers www.ti.com 22.3.6 ADC Group1 Operating Mode Control Register (ADG1MODECR) ADC Group1 Operating Mode Control Register (ADG1MODECR) is shown in Figure 22-26 and Figure 2227, and described in Table 22-12. As shown, the format of the ADG1MODECR is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. Figure 22-26.
ADC Registers www.ti.com Table 22-12. ADC Group1 Operating Mode Control Register (ADG1MODECR) Field Descriptions Field Reserved Value 0 No Reset on ChnSel Description Reads return zeros, writes have no effect. No Group1 Results Memory Reset on New Channel Select. This bit determines whether the group1 results’ RAM is reset whenever a non-zero value is written to the group1 channel select register.
ADC Registers www.ti.com Table 22-12. ADC Group1 Operating Mode Control Register (ADG1MODECR) Field Descriptions (continued) Field Value G1_8BIT Description Group1 8-bit result mode. This field is only applicable when the ADC module is configured to be in the 10-bit ADC module. This field is reserved when the module is configured as a 12-bit ADC module. This bit allows the Group1 conversion results to be read out in an 8-bit format. This bit only applies to the “read from FIFO” mode.
ADC Registers www.ti.com 22.3.7 ADC Group2 Operating Mode Control Register (ADG2MODECR) ADC Group2 Operating Mode Control Register (ADG2MODECR) is shown in Figure 22-28 and Figure 2229, described in Table 22-13. As shown, the format of the ADG2MODECR is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. Figure 22-28.
ADC Registers www.ti.com Table 22-13. ADC Group 2 Operating Mode Control Register (ADG2MODECR) Field Descriptions Field Value Reserved 0 No Reset on ChnSel Description Reads return zeros, writes have no effect. No Group2 Results Memory Reset on New Channel Select. This bit determines whether the group2 results’ RAM is reset whenever a non-zero value is written to the group2 channel select register.
ADC Registers www.ti.com Table 22-13. ADC Group 2 Operating Mode Control Register (ADG2MODECR) Field Descriptions (continued) Field Value G2_8BIT Description Group2 8-bit result mode. This field is only applicable when the ADC module is configured to be in the 10-bit ADC module. This field is reserved when the module is configured as a 12-bit ADC module. This bit allows the Group2 conversion results to be read out in an 8-bit format. This bit only applies to the “read from FIFO” mode.
ADC Registers www.ti.com 22.3.8 ADC Event Group Trigger Source Select Register (ADEVSRC) ADC Event Group Trigger Source Select Register (ADEVSRC) is shown in Figure 22-30 and described in Table 22-14. Figure 22-30. ADC Event Group Trigger Source Select Register (ADEVSRC) [offset = 1Ch] 31 8 Reserved R-0 7 4 3 Reserved 5 EV_EDG_BOTH EV_EDG_SEL 2 EV_SRC 0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-14.
ADC Registers www.ti.com 22.3.9 ADC Group1 Trigger Source Select Register (ADG1SRC) ADC Group1 Trigger Source Select Register (ADG1SRC) is shown in Figure 22-31 and described in Table 22-15. Figure 22-31. ADC Group1 Trigger Source Select Register (ADG1SRC) [offset = 20h] 31 8 Reserved R-0 7 4 3 Reserved 5 G1_EDG_BOTH G1_EDG_SEL 2 G1_SRC 0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-15.
ADC Registers www.ti.com 22.3.10 ADC Group2 Trigger Source Select Register (ADG2SRC) ADC Group2 Trigger Source Select Register (ADG2SRC) is shown in Figure 22-32 and described in Table 22-16. Figure 22-32. ADC Group2 Trigger Source Select Register (ADG2SRC) [offset = 24h] 31 8 Reserved R-0 7 4 3 Reserved 5 G2_EDG_BOTH G2_EDG_SEL 2 G2_SRC 0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-16.
ADC Registers www.ti.com 22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA) ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in Figure 22-33 and described in Table 22-17. Figure 22-33.
ADC Registers www.ti.com 22.3.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA) ADC Group1 Interrupt Enable Control Register (ADG1INTENA) is shown in Figure 22-34 and described in Table 22-18. Figure 22-34. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) [offset = 2Ch] 31 8 Reserved R-0 7 3 2 1 0 Reserved 4 G1_END_ INT_EN Reserved G1_OVR_ INT_EN G1_THR_ INT_EN R-0 R/W-0 R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-18.
ADC Registers www.ti.com 22.3.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA) ADC Group2 Interrupt Enable Control Register (ADG2INTENA) is shown in Figure 22-35 and described in Table 22-19. Figure 22-35. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) [offset = 30h] 31 8 Reserved R-0 7 3 2 1 0 Reserved 4 G2_END_ INT_EN Reserved G2_OVR_ INT_EN G2_THR_ INT_EN R-0 R/W-0 R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-19.
ADC Registers www.ti.com 22.3.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG) ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in Figure 22-36 and described in Table 22-20. Figure 22-36.
ADC Registers www.ti.com 22.3.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG) ADC Group1 Interrupt Flag Register (ADG1INTFLG) is shown in Figure 22-37 and described in Table 2221. Figure 22-37. ADC Group1 Interrupt Flag Register (ADG1INTFLG) [offset = 38h] 31 8 Reserved R-0 7 3 2 1 0 Reserved 4 G1_END G1_MEM_ EMPTY G1_MEM_ OVERRUN G1_THR_ INT_FLG R-0 R/W1C-0 R-1 R-0 R/W1C-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset Table 22-21.
ADC Registers www.ti.com 22.3.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG) ADC Group2 Interrupt Flag Register (ADG2INTFLG) is shown in Figure 22-38 and described in Table 2222. Figure 22-38. ADC Group2 Interrupt Flag Register (ADG2INTFLG) [offset = 3Ch] 31 8 Reserved R-0 7 3 2 1 0 Reserved 4 G2_END G2_MEM_ EMPTY G2_MEM_ OVERRUN G2_THR_ INT_FLG R-0 R/W1C-0 R-1 R-0 R/W1C-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset Table 22-22.
ADC Registers www.ti.com 22.3.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) is shown in Figure 22-39 and described in Table 22-23. Figure 22-39. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) [offset = 40h] 31 16 15 9 8 0 Reserved Sign Extension EV_THR R-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-23.
ADC Registers www.ti.com 22.3.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) The ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) is shown in Figure 22-41 and described in Table 22-25. Figure 22-41. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) [offset = 48h] 31 16 15 9 8 0 Reserved Sign Extension G2_THR R-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-25.
ADC Registers www.ti.com 22.3.20 ADC Event Group DMA Control Register (ADEVDMACR) ADC Event Group DMA Control Register (ADEVDMACR) is shown in Figure 22-42 and described in Table 22-26. Figure 22-42.
ADC Registers www.ti.com Table 22-26. ADC Event Group DMA Control Register (ADEVDMACR) Field Descriptions (continued) Bit 0 Field Value EV_DMA_EN Description Event Group DMA Transfer Enable. Any operation mode read: 884 0 ADC module does not generate a DMA request when it writes the conversion result to the Event Group memory. 1 ADC module generates a DMA transfer when the ADC has written to the Event Group memory. The EV_BLK_XFER bit must be cleared to 0 for this DMA request to be generated.
ADC Registers www.ti.com 22.3.21 ADC Group1 DMA Control Register (ADG1DMACR) ADC Group1 DMA Control Register (ADG1DMACR) is shown in Figure 22-43 and described in Table 2227. Figure 22-43. ADC Group1 DMA Control Register (ADG1DMACR) [offset = 50h] 31 25 24 16 Reserved G1_BLOCKS R-0 R/W-0 15 8 Reserved R-0 7 4 Reserved 3 2 DMA_G1_END G1_BLK_XFER R-0 R/W-0 R/W-0 1 0 Reserved G1_DMA_EN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-27.
ADC Registers www.ti.com Table 22-27. ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions (continued) Bit 0 Field Value G1_DMA_EN Description Group1 DMA Transfer Enable. Any operation mode read: 886 0 ADC module does not generate a DMA request when it writes the conversion result to the Group1 memory. 1 ADC module generates a DMA transfer when the ADC has written to the Group1 memory. The G1_BLK_XFER bit must be cleared to 0 for this DMA request to be generated.
ADC Registers www.ti.com 22.3.22 ADC Group2 DMA Control Register (ADG2DMACR) ADC Group2 DMA Control Register (ADG2DMACR) is shown in Figure 22-44 and described in Table 2228. Figure 22-44. ADC Group2 DMA Control Register (ADG2DMACR) [offset = 54h] 31 25 24 16 Reserved G2_BLOCKS R-0 R/W-0 15 8 Reserved R-0 7 4 Reserved 3 2 DMA_G2_END G2_BLK_XFER R-0 R/W-0 R/W-0 1 0 Reserved G2_DMA_EN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-28.
ADC Registers www.ti.com Table 22-28. ADC Group2 DMA Control Register (ADG2DMACR) Field Descriptions (continued) Bit 0 Field Value G2_DMA_EN Description Group2 DMA Transfer Enable. Any operation mode read: 888 0 ADC module does not generate a DMA request when it writes the conversion result to the Group2 memory. 1 ADC module generates a DMA transfer when the ADC has written to the Group2 memory. The G2_BLK_XFER bit must be cleared to 0 for this DMA request to be generated.
ADC Registers www.ti.com 22.3.23 ADC Results Memory Configuration Register (ADBNDCR) ADC Results Memory Configuration Register (ADBNDCR) [offset = 0x58] is shown in Figure 22-45 and described in Table 22-29. Refer to Section 22.2.7 for further details on how the conversion results are stored in the ADC results’ RAM. Figure 22-45.
ADC Registers www.ti.com 22.3.24 ADC Results Memory Size Configuration Register (ADBNDEND) ADC Results Memory Size Configuration Register (ADBNDEND) is shown in Figure 22-46 and described in Table 22-30. Figure 22-46. ADC Results Memory Size Configuration Register (ADBNDEND) [offset = 5Ch] 31 17 16 Reserved BUF_INIT_ACTIVE R-0 R-0 15 3 2 0 Reserved BNDEND R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-30.
ADC Registers www.ti.com 22.3.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP) ADC Event Group Sampling Time Configuration Register (ADEVSAMP) is shown in Figure 22-47 and described in Table 22-31. Figure 22-47. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) [offset = 60h] 31 12 11 0 Reserved EV_ACQ R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-31.
ADC Registers www.ti.com 22.3.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP) ADC Group2 Sampling Time Configuration Register (ADG2SAMP) is shown in Figure 22-49 and described in Table 22-33. Figure 22-49. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) [offset = 68h] 31 12 11 0 Reserved G2_ACQ R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-33.
ADC Registers www.ti.com 22.3.28 ADC Event Group Status Register (ADEVSR) ADC Event Group Status Register (ADEVSR) is shown in Figure 22-50 and described in Table 22-34. Figure 22-50. ADC Event Group Status Register (ADEVSR) [offset = 6Ch] 31 8 Reserved R-0 7 3 2 1 0 Reserved 4 EV_MEM_ EMPTY EV_BUSY EV_STOP EV_END R-0 R-1 R-0 R-0 R/W1C-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-34.
ADC Registers www.ti.com 22.3.29 ADC Group1 Status Register (ADG1SR) ADC Group1 Status Register (ADG1SR) is shown in Figure 22-51 and described in Table 22-35. Figure 22-51. ADC Group1 Status Register (ADG1SR) [offset = 70h] 31 8 Reserved R-0 7 3 2 1 0 Reserved 4 G1_MEM_ EMPTY G1_BUSY G1_STOP G1_END R-0 R-1 R-0 R-0 R/W1C-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-35.
ADC Registers www.ti.com 22.3.30 ADC Group2 Status Register (ADG2SR) ADC Group2 Status Register (ADG2SR) is shown in Figure 22-52 and described in Table 22-36. Figure 22-52. ADC Group2 Status Register (ADG2SR) [offset = 74h] 31 8 Reserved R-0 7 3 2 1 0 Reserved 4 G2_MEM_ EMPTY G2_BUSY G2_STOP G2_END R-0 R-1 R-0 R-0 R/W1C-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-36.
ADC Registers www.ti.com 22.3.31 ADC Event Group Channel Select Register (ADEVSEL) ADC Event Group Channel Select Register (ADEVSEL) is shown in Figure 22-53 and described in Table 22-37. NOTE: Clearing ADEVSEL During a Conversion Writing 0x0000 to ADEVSEL stops the Event Group conversions. This does not cause the ADC Event Group Results Memory pointer or the Event Group Threshold Register to be reset.
ADC Registers www.ti.com 22.3.32 ADC Group1 Channel Select Register (ADG1SEL) ADC Group1 Channel Select Register (ADG1SEL) is shown in Figure 22-54 and described in Table 22-38. NOTE: Clearing ADG1SEL During a Conversion Writing 0x0000 to ADG1SEL stops the Group1 conversions. This does not cause the ADC Group1 Results Memory pointer or the Group1 Threshold Register to be reset.
ADC Registers www.ti.com 22.3.33 ADC Group2 Channel Select Register (ADG2SEL) ADC Group2 Channel Select Register (ADG2SEL) is shown in Figure 22-55 and described in Table 22-39. NOTE: Clearing ADG2SEL During a Conversion Writing 0x0000 to ADG2SEL stops the Group2 conversions. This does not cause the ADC Group2 Results Memory pointer or the Group2 Threshold Register to be reset.
ADC Registers www.ti.com 22.3.34 ADC Calibration and Error Offset Correction Register (ADCALR) ADC Calibration and Error Offset Correction Register (ADCALR) is shown in Figure 22-56 and Figure 2257, and described in Table 22-40. As shown, the format of the ADCALR is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. Figure 22-56.
ADC Registers www.ti.com 22.3.36 ADC Channel Last Conversion Value Register (ADLASTCONV) ADC Channel Last Conversion Value Register (ADLASTCONV) is shown in Figure 22-59 and described in Table 22-42. Figure 22-59. ADC Channel Last Conversion Value Register (ADLASTCONV) [offset = 8Ch] 31 24 23 0 Reserved LAST_CONV R-0 R-U LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown Table 22-42.
ADC Registers www.ti.com 22.3.37 ADC Event Group Results' FIFO Register (ADEVBUFFER) ADC Event Group Results' FIFO Register (ADEVBUFFER) is shown in Figure 22-60 and Figure 22-61, and described in Table 22-43. As shown, the format of the data read from the ADEVBUFFER locations is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. Figure 22-60.
ADC Registers www.ti.com 22.3.38 ADC Group1 Results FIFO Register (ADG1BUFFER) ADC Group1 Results FIFO Register (ADG1BUFFER) is shown in Figure 22-62 and Figure 22-63, described in Table 22-44. As shown, the format of the data read from the ADG1BUFFER locations is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. Figure 22-62.
ADC Registers www.ti.com 22.3.39 ADC Group2 Results FIFO Register (ADG2BUFFER) ADC Group2 Results FIFO Register (ADG2BUFFER) is shown in Figure 22-64 and Figure 22-65, described in Table 22-45. As shown, the format of the data read from the ADG2BUFFER locations is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. Figure 22-64.
ADC Registers www.ti.com 22.3.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) is shown in Figure 22-66 and Figure 22-67, and described in Table 22-46. As shown, the format of the data read from the ADEVEMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
ADC Registers www.ti.com 22.3.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) is shown in Figure 22-68 and Figure 22-69, described in Table 22-47. As shown, the format of the data read from the ADG1EMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
ADC Registers www.ti.com 22.3.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) is shown in Figure 22-70 and Figure 22-71, described in Table 22-48. As shown, the format of the data read from the ADG2EMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
ADC Registers www.ti.com 22.3.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR) ADC ADEVT Pin Direction Control Register (ADEVTDIR) is shown in Figure 22-72 and described in Table 22-49. Figure 22-72. ADC ADEVT Pin Direction Control Register (ADEVTDIR) [offset = FCh] 31 1 0 Reserved ADEVT_DIR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-49.
ADC Registers www.ti.com 22.3.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT) ADC ADEVT Pin Output Value Control Register (ADEVTOUT) is shown in Figure 22-73 and described in Table 22-50. Figure 22-73. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) [offset = 100h] 31 1 0 Reserved ADEVT_OUT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-50.
ADC Registers www.ti.com 22.3.46 ADC ADEVT Pin Set Register (ADEVTSET) ADC ADEVT Pin Set Register (ADEVTSET) is shown in Figure 22-75 and described in Table 22-52. Figure 22-75. ADC ADEVT Pin Set Register (ADEVTSET) [offset = 108h] 31 1 0 Reserved ADEVT_SET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-52.
ADC Registers www.ti.com 22.3.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) is shown in Figure 22-77 and described in Table 22-54. Figure 22-77. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) [offset = 110h] 31 1 0 Reserved ADEVT_PDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-54.
ADC Registers www.ti.com 22.3.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) is shown in Figure 22-79 and described in Table 22-56. Figure 22-79. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) [offset = 118h] 31 1 0 Reserved ADEVT_PSEL R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-56.
ADC Registers www.ti.com 22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) is shown in Figure 22-81 and described in Table 22-58. Figure 22-81. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) [offset = 120h] 31 16 Reserved R-0 15 8 7 1 0 G1_SAMP_DIS_CYC Reserved G1_SAMP_ DIS_EN R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-58.
ADC Registers www.ti.com 22.3.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) is shown in Figure 22-82 and described in Table 22-59. Figure 22-82. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) [offset = 124h] 31 16 Reserved R-0 15 8 7 1 0 G2_SAMP_DIS_CYC Reserved G2_SAMP_ DIS_EN R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-59.
ADC Registers www.ti.com 22.3.54 ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) are shown in Figure 22-83 and Figure 22-84, and described in Table 22-60. As shown, the format of the ADMAGINTxCR is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. The ADC module supports up to three magnitude compare interrupts. These registers are at offset addresses 128h, 130h, and 138h.
ADC Registers www.ti.com Table 22-60. ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) Field Descriptions Field Reserved Value 0 Description Reads return zeros, writes have no effect. MAG_CHIDx These bits specify the channel number from 0 to 31 for which the conversion result needs to be monitored by the ADC. MAG_THRx These bits specify the 12-bit or 10-bit compare value that the ADC will use for the comparison with the MAG_CHIDx channel's conversion result.
ADC Registers www.ti.com 22.3.55 ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK) ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK) is shown in Figure 22-85and Figure 22-86, and described in Table 22-61. As shown, the format of the ADMAGINTxMASK is different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. There are three mask registers for the three magnitude compare interrupts. These registers are at offset addresses 12Ch, 134h, and 13Ch.
ADC Registers www.ti.com 22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) is shown in Figure 22-87 and described in Table 22-62. Figure 22-87. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) [offset = 158h] 31 3 2 0 Reserved MAG_INT_ENA_SET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-62.
ADC Registers www.ti.com 22.3.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) is shown in Figure 22-89 and described in Table 22-64. Figure 22-89. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) [offset = 160h] 31 3 2 0 Reserved MAG_INT_FLG R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-64.
ADC Registers www.ti.com 22.3.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) is shown in Figure 22-91 and described in Table 22-66. Figure 22-91. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) [offset = 168h] 31 1 0 Reserved EV_FIFO_RESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-66.
ADC Registers www.ti.com 22.3.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) is shown in Figure 22-93 and described in Table 22-68. Figure 22-93. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) [offset = 170h] 31 1 0 Reserved G2_FIFO_RESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-68.
ADC Registers www.ti.com 22.3.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) is shown in Figure 22-95 and described in Table 22-70. Figure 22-95. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) [offset = 178h] 31 9 8 0 Reserved G1_RAM_ADDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-70.
ADC Registers www.ti.com 22.3.66 ADC Parity Control Register (ADPARCR) ADC Parity Control Register (ADPARCR) is shown in Figure 22-97 and described in Table 22-72. Figure 22-97. ADC Parity Control Register (ADPARCR) [offset = 180h] 31 16 Reserved R-0 15 9 8 7 4 3 0 Reserved TEST Reserved PARITY_ENA R-0 R/WP-0 R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 22-72.
ADC Registers www.ti.com 22.3.67 ADC Parity Error Address Register (ADPARADDR) ADC Parity Error Address Register (ADPARADDR) is shown inFigure 22-98 and described in Table 22-73. Figure 22-98. ADC Parity Error Address Register (ADPARADDR) [offset = 184h] 31 16 Reserved R-0 15 12 11 2 1 0 Reserved ERROR_ADDRESS Reserved R-0 R-U R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown Table 22-73.
ADC Registers www.ti.com 22.3.69 ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) Figure 22-100 and Table 22-75 describe the ADEVCHNSELMODECTRL register. Figure 22-100. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) (offset = 190h) 31 4 3 0 Reserved EV_ENH_CHNSEL_MODE_ENABLE R-0 R/W-5h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-75.
ADC Registers www.ti.com 22.3.71 ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) Figure 22-102 and Table 22-77 describe the ADG2CHNSELMODECTRL register. Figure 22-102. ADC Group2 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 198h) 31 4 3 0 Reserved G2_ENH_CHNSEL_MODE_ENABLE R-0 R//W-5h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-77.
ADC Registers www.ti.com 22.3.72 ADC Event Group Current Count Register (ADEVCURRCOUNT) Figure 22-103 and Table 22-78 describe the ADEVCURRCOUNT register. Figure 22-103. ADC Event Group Current Count Register (ADEVCURRCOUNT) (offset = 19Ch) 31 5 4 0 Reserved EV_CURRENT_COUNT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-78.
ADC Registers www.ti.com 22.3.74 ADC Group1 Current Count Register (ADG1CURRCOUNT) Figure 22-105 and Table 22-80 describe the ADG1CURRCOUNT register. Figure 22-105. ADC Group1 Current Count Register (ADG1CURRCOUNT) (offset = 1A4h) 31 5 4 0 Reserved G1_CURRENT_COUNT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-80.
ADC Registers www.ti.com 22.3.76 ADC Group2 Current Count Register (ADG2CURRCOUNT) Figure 22-107 and Table 22-82 describe the ADG2CURRCOUNT register. Figure 22-107. ADC Group2 Current Count Register (ADG2CURRCOUNT) (offset = 1ACh) 31 5 4 0 Reserved G2_CURRENT_COUNT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22-82.
Chapter 23 SPNU562 – May 2014 High-End Timer (N2HET) Module This chapter provides a general description of the High-End Timer (N2HET). The N2HET is a softwarecontrolled timer with a dedicated specialized timer micromachine and a set of 30 instructions. The N2HET micromachine is connected to a port of up to 32 input/output (I/O) pins. NOTE: This chapter describes a superset implementation of the N2HET module that includes features and functionality that require DMA.
Features www.ti.com 23.1 Features • • • • • • • • • • • Programmable timer for input and output timing functions Reduced instruction set (30 instructions) for dedicated time and angle functions Up to maximum of 128 96-bit words of instruction RAM protected by parity. Check your datasheet for the actual number of words implemented.
Features www.ti.com 23.1.1.2 Timer Module Structure and Execution The timer consists of a specialized micromachine that operates a reduced instruction set. Two 25-bit registers and three 32-bit registers are available to manipulate information such as time, event counts, and angle values.
Features www.ti.com Other instructions (MOV64, RADM64) can modify both the control and data fields of other instructions. This allows the N2HET to implement toggle functionality. For example, an ECMP instruction can be followed by a pair of MOV64 instructions. The MOV64 instruction updates the data field of the ECMP instruction to implement the double buffering behavior.
Features www.ti.com 23.1.1.
Features www.ti.com Figure 23-1. N2HET Block Diagram Peripheral bus High Resolution prescaler HETPFR.5:0 Shadow Registers Shadow Registers HR clock (to IO PIN CONTROL) Loop resolution prescaler HETPFR.10:8 Address Decode HOST INTERFACE Slave Master HETGCR.16 internal multiN2HET sync Control RAM Program RAM Data RAM NHET RAM CURRENT INSTRUCTION PROGRAM FIELD Ignore Suspend CONTROL FIELD DATA FIELD OFF Stop ON HETGCR.17 Register A HETGCR.
N2HET Functional Description www.ti.com 23.2 N2HET Functional Description The N2HET contains RAM into which N2HET code is loaded. The N2HET code is run by the specialized timer micromachine. The host interface and I/O control provide an interface to the CPU and external pins respectively. 23.2.1 Specialized Timer Micromachine The N2HET has its own instruction set, detailed in Section 23.5.1. The timer micromachine reads each instruction from the N2HET RAM.
N2HET Functional Description www.ti.com 23.2.1.1 Time Slots and Resolution Loop Each instruction requires a specific number of cycles or time slots to execute. The resolution specified in the prescaler bitfields determines the timer accuracy. All input captures, event counts, and output compares are executed once in each resolution loop. HR captures and compares are possible (up to N2HET clock accuracy) on the HR I/O pins. For more information about the HR I/O structure, see Section 23.2.5. 23.2.1.
N2HET Functional Description www.ti.com As Figure 23-4 illustrates, when a program overflow occurs, the currently executing N2HET program sequence is interrupted and restarted at N2HETaddress 0 for the beginning of the next loop resolution clock period. Also, HETEXC2.PRGMOVRFLFLAG is set. If the instruction that caused the overflow (instruction at address 0xC in Figure 23-4) has any pin actions selected, these pin actions will not be performed.
N2HET Functional Description www.ti.com Figure 23-5. Multi-Resolution Operation Flow Example Instructions with full resolution (2 Ps) Branch on conditional address 0 Instructions with lower resolution (6 Ps) Change conditional address 1 2 Instructions with lower resolution (6 Ps) Change conditional address Instructions with lower resolution (6 Ps) Change conditional address 23.2.1.7 Debug Capability The N2HET supports breakpoints to allow you to more easily debug your N2HET program.
N2HET Functional Description www.ti.com The N2HET internal working registers (A,B,R,S,T) are not directly visible through the JTAG emulator interface. If the content of these registers needs to be inspected, it is best to add an instruction like MOV32 which copies the register value to the N2HET RAM. This RAM location can be inspected when the N2HET halts. To 1. 2. 3. restart execution of both the CPU and the N2HET from the halted state: Clear NHETEXC2.DEBUGSTATUSFLAG.
N2HET Functional Description www.ti.com 23.2.2.1 N2HET RAM Banking Because the CPU must make updates to the N2HET RAM while the N2HET is executing, for example to update the duty cycle value of a PWM, it is important to understand how the N2HET RAM organization facilitates simultaneous accesses by both the HOST CPU and the N2HET. The N2HET RAM is implemented as 4 banks of 96-bit wide two port RAM. This means that there a total of 8 ports available; four read and four write.
N2HET Functional Description www.ti.com Even or odd parity selection for N2HET parity detection can be configured in the system module. Parity calculation and checking can be enabled/disabled by a 4-bit key in HETPCR. During a read access to the N2HET RAM, the parity is calculated based on the data read from the RAM and compared with the good parity value stored in the parity bits.
N2HET Functional Description www.ti.com Table 23-4. N2HET Parity Bit Mapping (continued) Bits Address N2HET1 Address N2HET2 [31:1] 0xFF46_200C 0xFF44_200C Reads 0, Writes have no effect Read 0 0xFF46_2010 0xFF44_2010 Reads 0, Writes have no effect Instruction 1 Program Field Parity Bit .... .... ... ... [0] Each 32-bit N2HET field has its own parity bit in the N2HET Parity RAM as shown in Table 23-4.
N2HET Functional Description www.ti.com 5. LRP = loop resolution clock period LRP = lr · HRP (ns) The loop resolution period (LRP) must be selected to be larger than the number of Time slots (VCLK2 cycles) required to complete the worst-case execution path through the N2HET program. Otherwise a program overflow condition may occur (see Section 23.2.1.4).
N2HET Functional Description www.ti.com There are lr high resolution clock periods (HRP) within the N2HET loop resolution clock period (LRP). If lr = 128 then the HR delay can range from 0 to127 HRP clocks within LRP and all 7 bits of the HR data field are needed. Instead of being limited to measuring and triggering events based on the loop resolution clock period (LRP) the HR extension allows measurements and events to be described in terms fractions of an LRP (down to 1/128 of an LRP).
N2HET Functional Description www.ti.com 23.2.4.2 64-bit Read Access The consecutive read of a control field CF(n) and a data field DF(n) of the same instruction (n) performed by the same master (for example, CPU, DMA, or any other master) is always done as a simultaneous 64bit read access. This means that at the same time CF(n) is read, DF(n) is loaded in a shadow register. So the second access will read DF(n) from the shadow register instead of the N2HET RAM.
N2HET Functional Description www.ti.com These 32 I/Os have an identical structure connected to pins HET[31] to HET[0]. See Figure 23-8 for an illustration of the I/O control. In addition all 32 I/Os have a special HR structure based on the HR clock. This structure allows any N2HET instruction to use any of these I/Os with an accuracy of either loop resolution or high resolution accuracy. Figure 23-8.
N2HET Functional Description www.ti.com Figure 23-9. N2HET Loop Resolution Structure for Each Bit HETDIN Timer data in Loop Resolution Clock HET[x] HETDSET Timer data out HETDOUT HETDCLR HETDIR The example in Figure 23-10 shows a simple PWM generation with loop resolution accuracy.
N2HET Functional Description www.ti.com 23.2.5.3 High Resolution Structure All 32 I/Os provide the HR structure based on the HR clock. The HR clock frequency is programmed through the Prescale Factor Register (HETPFR). In addition to the standard I/O structure, all pins have HR hardware so that these pins can be used as HR input captures (using the HR instructions PCNT or WCAP) or HR output compares (using the HR instructions ECMP, MCMP or PWCNT).
N2HET Functional Description www.ti.com 23.2.5.5 HR Structures Sharing (Input) The HR Share Control Register (HETHRSH) allows two HR structures to share the same pin for input capture only. If these bits are set, the HR structures N and N+1 are connected to pin N. In this structure, pin N+1 remains available for general purpose input/output. See Figure 23-12. Figure 23-12.
N2HET Functional Description www.ti.com The following N2HET program gives an example for one channel of the symmetrical PWM. The generated timing is given in Figure 23-14. MAXC .equ 22 A_ .equ 0 ; HR structure HR0 B_ .
N2HET Functional Description www.ti.com As an alternative, HR structures may be shared using a logical AND function to combine the effects of the pin structures. The HETAND allows sharing two consecutive HR structures N (even) and N+1 (odd). See Figure 23-15. In this structure, pin N+1 remains available for general purpose input/output. NOTE: Setting both the HETAND bit and HETXOR bits at the same time for a given pair of N2HET pins is not supported, must be avoided by the application program.
N2HET Functional Description www.ti.com Figure 23-16.
N2HET Functional Description www.ti.com 23.2.5.8 Edge Detection Input Timing There are several timing requirements for input signals in order to be captured correctly by N2HET. Figure 23-18 illustrates these requirements, with min and max values described in Table 23-7 (Loop Resolution) and Table 23-8 (High Resolution). Figure 23-18. N2HET Input Edge Detection 1 N2HETx 3 4 2 Table 23-7.
N2HET Functional Description www.ti.com When the 25-bit (loop resolution) compare matches, the HR compare value will be loaded from the 7 lower bits of the instruction data field to the HR counter. At the next loop resolution clock, the HR counter will count down at the HR clock frequency and perform the pin action when it reaches zero. In the example illustrated by Figure 23-19, the 25-bit compare value is 1 and the 7-bit HR compare value is 2. According to Section 23.2.3.
N2HET Functional Description www.ti.com 23.2.5.10 PWM Generation Example 2 (in HR Mode) The MCMP instruction can also be used in HR mode. In this case operation is exactly the same as for the ECMP instruction except that the 25-bit low resolution is now the result of a magnitude compare (greater or equal) rather than an equality compare. When the 25-bit (loop resolution) magnitude compare matches, the HR compare value will be loaded from the 7 lower bits of the instruction data field to the HR counter.
N2HET Functional Description www.ti.com Figure 23-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow) HR clock Loop res clock PCNT CF X HR counter 0 0 1 2 3 0 1 1 2 3 2 0 0 HR capt. reg X 1 PCNT DF X 2 Input pin Input pin sync’d 1 2 3 Figure 23-22 shows what happens when the capture edge arrives before the HR counter overflows. This causes the non-incremented value to be captured by the PCNT instruction. Figure 23-22.
N2HET Functional Description www.ti.com Figure 23-23. WCAP Instruction Timing LRP HR clock HRP Loop res clock Instruction CNT WCAP A register CNT WCAP 0 HR counter 0 CNT WCAP 1 1 2 CNT WCAP 2 3 0 1 2 CNT WCAP 3 3 0 1 2 CNT WCAP 4 3 0 1 5 2 3 0 1 2 6 3 0 1 2 3 Input pin HET[0] sync’d to VCLK2 Input pin HET[0] sampled by LRP HR capt.
N2HET Functional Description www.ti.com The following apply if the device is under reset: • Pull control: The reset pull control on the pins is enabled and a pulldown is configured. • Input buffer: The input buffer is enabled. • Output buffer: The output buffer is disabled. The following apply if the device is out of reset: • Pull control: The pull control is enabled by clearing the corresponding bit in the N2HET Pull Disable Register (HETPULDIS).
N2HET Functional Description www.ti.com 23.2.5.16 N2HET Pin Disable Feature This feature is provided for the safe operation of systems such as power converters and motor drives. It can be used to inform the monitoring software of motor drive abnormalities such as over-voltage, overcurrent, and excessive temperature rise. Figure 23-25.
N2HET Functional Description www.ti.com 23.2.6 Suppression Filters Each N2HET pin is equipped with a suppression filter. If the pin is configured as an input it enables to filter out pulses shorter than a programmable duration. Each filter consists of a 10-bit down counter, which starts counting at a programmable preloaded value and is decremented using the VCLK2 clock. • The counter starts counting when the filter input signal has the opposite state of the filter output signal.
N2HET Functional Description www.ti.com Table 23-12. Interrupt Sources and Corresponding Offset Values in Registers HETOFFx Source No. Offset Value no interrupt 0 Instruction 0, 32, 64... 1 Instruction 1, 33, 65... 2 : : Instruction 31, 63, 95... 32 Program Overflow 33 APCNT underflow: 34 APCNT overflow 35 The instructions capable of generating interrupts are listed in Table 23-51. Figure 23-27.
N2HET Functional Description www.ti.com Figure 23-28.
N2HET Functional Description www.ti.com 23.2.9 N2HET Requests to DMA and HTU As described in Section 23.5.3 the majority of the N2HET instructions are able to generate a transfer request to the High End Timer Transfer Unit (HTU) and/or to the DMA module when an instruction-specific condition is true. One N2HET instruction can select one of 8 request lines by programming the “reqnum” parameter (see Section 23.5.3).
Angle Functions www.ti.com 23.3 Angle Functions Engine management systems require an angle-referenced time base to synchronize signals to the engine toothed wheel. The N2HET has a method to provide such a time base for low-end engine systems. The reference is created by the N2HET using three dedicated instructions with fractional angle steps equal to /8, /16, /32, /64. 23.3.
Angle Functions www.ti.com Figure 23-31. SCNT Count Operation Final Count = N0+nK Target=P(n-1) Final Count = N1+mK E SCNT step counter N0+3K N1+2K N0+2K N1+K N0+K N1=N0+nK-P(n-1) N0 N2=N1+mK-P(n-1) E ACNT detects period variations of the external signal measured by APCNT and compensates related counting errors. A period increase is flagged in the deceleration flag. A period decrease is flagged in the acceleration flag.
Angle Functions www.ti.com Figure 23-33 and Figure 23-34 illustrate the behavior of the angle generator during a gap after a deceleration or acceleration of the N2HET. Figure 23-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration) Singularity HET[2] ext. ref. signal APCNT period counter DCF Decel flag ACNT angle generator GPF Gap flag Gap End Gap Start Figure 23-34. N2HET Timings Associated with the Gap Flag (ACNT Acceleration) Singularity HET[2] ext. ref.
Angle Functions www.ti.com 23.3.1.2 APCNT Underflow The fastest valid external signal APCNT can accept must satisfy the following condition: Step Width K < Period Min. Resolution (LRP) This condition fixes the maximum possible step width once the minimum period and the resolution of an application are specified.
N2HET Control Registers 23.4 www.ti.com N2HET Control Registers Table 23-13 summarizes all the N2HET registers. The base address for the control registers is FFF7 B800h for N2HET1 and FFF7 B900h for N2HET2. Table 23-13. N2HET Registers 968 Offset Acronym Register Description 00h HETGCR Global Configuration Register Section 23.4.1 Section 04h HETPFR Prescale Factor Register Section 23.4.2 08h HETADDR NHET Current Address Register Section 23.4.
N2HET Control Registers www.ti.com 23.4.1 Global Configuration Register (HETGCR) N2HET1: offset = FFF7 B800h; N2HET2: offset = FFF7 B900h Figure 23-35. Global Configuration Register (HETGCR) 31 25 Reserved 24 23 HET PIN ENA R-0 R/W-1 22 Rsvd. R-0 21 MP 20 19 Reserved R/W-0 R-0 18 PPF 17 16 IS R/W-0 R/W-0 15 CMS R/W-0 1 0 Reserved TO R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-14.
N2HET Control Registers www.ti.com Table 23-14. Global Configuration Register (HETGCR) Field Descriptions (continued) Bit 0 Field Value TO Description Turn On/Off When TO = 0, the timer program stops executing. Turn-off is automatically delayed until the current timer program loop is completed. Turn-off does not affect the content of the timer RAM, ALU registers, or control registers. Turn-off resets all flags. TO does not affect the state of the pins.
N2HET Control Registers www.ti.com 23.4.3 N2HET Current Address Register (HETADDR) N2HET1: offset = FFF7 B808h; N2HET2: offset = FFF7 B908h Figure 23-37. N2HET Current Address (HETADDR) 31 16 Reserved R-0 15 9 8 0 Reserved HETADDR R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-16. N2HET Current Address (HETADDR) Field Descriptions Bit Field Value 31-9 Reserved 0 8-0 HETADDR Description Read returns 0. Writes have no effect.
N2HET Control Registers www.ti.com Table 23-18. Interrupt Offset Encoding Format Source No. Offset Value No interrupt 0 Instruction 0, 32, 64... 1 Instruction 1, 33, 65... 2 : : Instruction 31, 63, 95... 32 Program Overflow 33 APCNT Underflow 34 APCNT Overflow 35 23.4.5 Offset Index Priority Level 2 Register (HETOFF2) N2HET1: offset = FFF7 B810h; N2HET2: offset = FFF7 B910h Figure 23-39.
N2HET Control Registers www.ti.com 23.4.6 Interrupt Enable Set Register (HETINTENAS) N2HET1: offset = FFF7 B814h; N2HET2: offset = FFF7 B914h Figure 23-40. Interrupt Enable Set Register (HETINTENAS) 31 16 HETINTENAS R/W-0 15 0 HETINTENAS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-20. Interrupt Enable Set Register (HETINTENAS) Field Descriptions Bit 31-0 Field Value HETINTENAS Description Interrupt Enable Set bits.
N2HET Control Registers www.ti.com 23.4.8 Exception Control Register 1 (HETEXC1) N2HET1: offset = FFF7 B81Ch; N2HET2: offset = FFF7 B91Ch Figure 23-42.
N2HET Control Registers www.ti.com 23.4.9 Exception Control Register 2 (HETEXC2) N2HET1: offset = FFF7 B820h; N2HET2: offset = FFF7 B920h Figure 23-43. Exception Control Register 2 (HETEXC2) 31 16 Reserved R-0 15 9 Reserved 8 DEBUG STATUS FLAG R-0 7 R/WC-0 3 Reserved R-0 2 1 0 APCNT OVRFL FLAG APCNT UNRFL FLAG PRGM OVRFL FLAG R/WC-0 R/WC-0 R/WC-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset Table 23-23.
N2HET Control Registers www.ti.com 23.4.10 Interrupt Priority Register (HETPRY) N2HET1: offset = FFF7 B824h; N2HET2: offset = FFF7 B924h Figure 23-44. Interrupt Priority Register (HETPRY) 31 16 HETPRY R/WP-0 15 0 HETPRY R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 23-24.
N2HET Control Registers www.ti.com 23.4.12 AND Share Control Register (HETAND) N2HET1: offset = FFF7 B82Ch; N2HET2: offset = FFF7 B92Ch Figure 23-46.
N2HET Control Registers www.ti.com 23.4.13 HR Share Control Register (HETHRSH) N2HET1: offset = FFF7 B834h; N2HET2: offset = FFF7 B934h Figure 23-47.
N2HET Control Registers www.ti.com 23.4.14 XOR Share Control Register (HETXOR) N2HET1: offset = FFF7 B838h; N2HET2: offset = FFF7 B938h Figure 23-48.
N2HET Control Registers www.ti.com 23.4.15 Request Enable Set Register (HETREQENS) N2HET1: offset = FFF7 B83Ch; N2HET2: offset = FFF7 B93Ch Figure 23-49. Request Enable Set Register (HETREQENS) 31 8 Reserved R-0 7 6 5 4 3 2 1 0 REQ ENA 7 REQ ENA 6 REQ ENA 5 REQ ENA 4 REQ ENA 3 REQ ENA 2 REQ ENA 1 REQ ENA 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-29.
N2HET Control Registers www.ti.com 23.4.17 Request Destination Select Register (HETREQDS) N2HET1: offset = FFF7 B844h; N2HET2: offset = FFF7 B944h Figure 23-51.
N2HET Control Registers www.ti.com 23.4.18 NHET Direction Register (HETDIR) N2HET1: offset = FFF7 B84Ch; N2HET2: offset = FFF7 B94Ch Figure 23-52. N2HET Direction Register (HETDIR) 31 16 HETDIR R/W-0 15 0 HETDIR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-32.
N2HET Control Registers www.ti.com 23.4.19 N2HET Data Input Register (HETDIN) N2HET1: offset = FFF7 B850h; N2HET2: offset = FFF7 B950h Figure 23-53. N2HET Data Input Register (HETDIN) 31 16 HETDIN R-x 15 0 HETDIN R-x LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; Table 23-33. N2HET Data Input Register (HETDIN) Field Descriptions Bit 31-0 Field Value HETDIN n Description Data input. This bit displays the logic state of the pin.
N2HET Control Registers www.ti.com 23.4.21 NHET Data Set Register (HETDSET) N2HET1: offset = FFF7 B858h; N2HET2: offset = FFF7 B958h Figure 23-55. N2HET Data Set Register (HETDSET) 31 16 HETDSET R/WS-0 15 0 HETDSET R/WS-0 LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset Table 23-35.
N2HET Control Registers www.ti.com 23.4.23 N2HET Open Drain Register (HETPDR) Values in this register enable or disable the open drain capability of the data pins. N2HET1: offset = FFF7 B860h; N2HET2: offset = FFF7 B960h Figure 23-57. N2HET Open Drain Register (HETPDR) 31 16 HETPDR R/W-0 15 0 HETPDR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-37.
N2HET Control Registers www.ti.com 23.4.25 N2HET Pull Select Register (HETPSL) Values in this register select the pull-up or pull-down functionality of the pins. N2HET1: offset = FFF7 B868h; N2HET2: offset = FFF7 B968h Figure 23-59. N2HET Pull Select Register (HETPSL) 31 16 HETPSL R/W-0 15 0 HETPSL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-39.
N2HET Control Registers www.ti.com 23.4.26 Parity Control Register (HETPCR) N2HET1: offset = FFF7 B874h; N2HET2: offset = FFF7 B974h Figure 23-60. Parity Control Register (HETPCR) 31 16 Reserved R-0 15 9 8 7 4 3 0 Reserved TEST Reserved PARITY_ENA R-0 R/WP-0 R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 23-40.
N2HET Control Registers www.ti.com 23.4.27 Parity Address Register (HETPAR) N2HET1: offset = FFF7 B878h; N2HET2: offset = FFF7 B978h Figure 23-61. Parity Address Register (HETPAR) 31 16 Reserved R-0 15 13 12 2 1 0 Reserved PAOFF Reserved R-0 R-X R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; X = Value unchanged after reset Table 23-41. Parity Address Register (HETPAR) Field Descriptions Bit Field 31-13 Reserved 12-2 PAOFF Value 0 Description Read returns 0.
N2HET Control Registers www.ti.com 23.4.28 Parity Pin Register (HETPPR) N2HET1: offset = FFF7 B87Ch; N2HET2: offset = FFF7 B97Ch Figure 23-62. Parity Pin Register (HETPPR) 31 16 HETPPR R/W-0 15 0 HETPPR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-42.
N2HET Control Registers www.ti.com 23.4.29 Suppression Filter Preload Register (HETSFPRLD) N2HET1: offset = FFF7 B880h; N2HET2: offset = FFF7 B980h Figure 23-63. Suppression Filter Preload Register (HETSFPRLD) 31 18 15 10 17 16 Reserved CCDIV R-0 R/W-0 9 0 Reserved CPRLD R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-44.
N2HET Control Registers www.ti.com 23.4.31 Loop Back Pair Select Register (HETLBPSEL) Refer to Section 23.2.5.7 for a description of loopback test functions. N2HET1: offset = FFF7 B88Ch; N2HET2: offset = FFF7 B98Ch Figure 23-65.
N2HET Control Registers www.ti.com 23.4.32 Loop Back Pair Direction Register (HETLBPDIR) Refer to Section 23.2.5.7 for a description of loopback test functions. N2HET1: offset = FFF7 B890h; N2HET2: offset = FFF7 B990h Figure 23-66.
N2HET Control Registers www.ti.com 23.4.33 N2HET Pin Disable Register (HETPINDIS) N2HET1: offset = FFF7 B894h; N2HET2: offset = FFF7 B994h Figure 23-67. N2HET Pin Disable Register (HETPINDIS) 31 16 HETPINDIS R/W-0 15 0 HETPINDIS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23-48.
Instruction Set www.ti.com 23.5 Instruction Set 23.5.1 Instruction Summary Table 23-49 presents a list of the instructions in the N2HET instruction set. The pages following describe each instruction in detail. Table 23-49.
Instruction Set www.ti.com Table 23-50.
Instruction Set www.ti.com 23.5.2 Abbreviations, Encoding Formats and Bits Abbreviations marked with a star (*) are available only on specific instructions. U Reading a bit marked with U will return an indeterminate value. BRK Defines the software breakpoint for the device software debugger. Default: OFF Location: Program field [22] next Defines the program address of the next instruction in the program flow. This value may be a label or an 9-bit unsigned integer.
Instruction Set www.ti.com The format CC{pin number} is also supported. MSB 0 0 0 0 LSB Description 0 0 0 Select HET[0] 0 0 1 Select HET[1] (Each pin may be selected by writing its number in binary) 1 1 1 1 0 Select HET[30] 1 1 1 1 1 Select HET[31] Reg* Register select: Selects the register for data comparison and storage Default: No register (None) Location: Control field [2:1] except for CNT instruction.
Instruction Set www.ti.com hr_lr* 998 Specifies HIGH/LOW data resolution. If the hr_lr field is HIGH, the instruction uses the hr_data field. If the hr_lr field is LOW, the hr_data field is ignored. Default: HIGH Location: Program Field [8] hr_lr Prog. field [8] LOW 1 HIGH 0 prv* Specifies the initial value defining the previous bit (see Section 23.2.5.8). A value of ON sets the previous pin-level bit to 1. A value of OFF sets the initial value of the previous (prv) bit to 0.
Instruction Set www.ti.com 23.5.3 Instruction Description The following sections provide information for individual instructions. Parameters in [] are optional. Refer to the N2HET assembler user guide for the default values when parameters are omitted. 23.5.3.
Instruction Set www.ti.com The purpose of the comparison is to assert pin action when the angle compare value lies between the old counter value and the new counter value (held in the selected register). Since the angle increment varies from one loop resolution clock to another, an exact equality test cannot be applied.
Instruction Set www.ti.com 23.5.3.2 ACNT (Angle Count) Syntax ACNT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer}] [request={NOREQ | GENREQ | QUIET}] edge={RISING | FALLING} [irq ={OFF | ON}] [control={OFF | ON}] [prv={OFF | ON}] gapend ={25-bit unsigned integer} data={25-bit unsigned integer} } Figure 23-71. ACNT Program Field (P31:P0) 31 26 25 23 22 21 13 12 9 8 7 1 0 0 Request Number BRK Next program address 1001 Edge select Reserved Int.
Instruction Set www.ti.com A period increase is flagged in the deceleration flag (DCF). A period decrease is flagged in the acceleration flag (ACF). If no variation is detected, ACNT increments the counter value each time SCNT reaches its target. If acceleration is detected, ACNT increments the counter value on each timer resolution. If deceleration is detected ACNT does not increment and is thus saturated.
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.3 ADCNST (Add Constant) Syntax ADCNST { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [control={OFF | ON}] remote={label | 9-bit unsigned integer} min_off={25-bit unsigned integer} data={25-bit unsigned integer} [hr_data={7-bit unsigned integer}] } Figure 23-74. ADCNST Program Field (P31:P0) 31 26 25 23 22 21 13 12 9 8 0 0 Reserved BRK Next program address 0101 Remote address 6 3 1 9 4 9 Figure 23-75.
Instruction Set www.ti.com Figure 23-77 andFigure 23-78 illustrate the behavior of ADCNST if the remote data field is or is not zero. Figure 23-77. ADCNST Operation If Remote Data Field[31:7] Is Not Zero 25-bit addition LSBs (HR data field) 32 bits + HR Remote DF HR Immediate DF = Remote DF Figure 23-78.
Instruction Set www.ti.com 23.5.3.
Instruction Set www.ti.com The Sub-Opcode field C[25:3] determines which type of operation (ADD, ADC, AND, OR, SBB, SUB, XOR) is executed by the instruction. A list of these operations and the corresponding Sub-Opcode encoding can be found in Table 23-52. All arithmetic is performed using 32-bit integer math. However, source and destination operands vary in width and can be 9 bits (REMP), 25 bits (A, B) or 32 bits (R,S,T, IMM, REM).
Instruction Set www.ti.com Table 23-54. Destination Operand Choices (continued) Destination Operand Stored Value Address dest rdest IMM D[31:0] = result [31:0] current instruction address C[7] = 1, C[2:1] = 10 n/a NONE n/a n/a C[7] = 0, C[2:1] = 11 C[4:3] = 00 REM D[31:0] = result [31:0] specified by remote[8:0] n/a C[4:3] = 01 REMP P[8:0] = result [8:0] specified by remote[8:0] n/a C[4:3] = 10 Table 23-55.
Instruction Set www.ti.
Instruction Set www.ti.com IC2 = IR1[scount-1] } else { IC2 = IC1 } IN2 = IR2[31]; if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0}; IV2 = (IR2[31] XOR IR1[31]) OR IV1 case 010: // smode = Logical Shift Left IR2[31 : scount] = IR1[31 - scount: 0] if (scount > 0) { IR2[scount - 1 : 0] = 0 } IC2 = IC1 IN2 = IR2[31]; if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0}; IV2 = (IR2[31] XOR IR1[31]) OR IV1 case 011: // smode = Carry Shift Left IR2[31 : scount] = IR1[31 - scount: 0] if (scount>0) { IR2[scount - 1 : 0] = [IC1,...
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.5 ADM32 (Add Move 32) Syntax ADM32 { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] remote={label | 9-bit unsigned integer} [control={OFF | ON}] [init={OFF | ON}] type={IM®TOREG | REM®TOREG | IM&REMTOREG | IM®TOREM} reg={A | B | R | S | T } data={25-bit unsigned integer} [hr_data={7-bit unsigned integer}] } Figure 23-82.
Instruction Set www.ti.com New angle flag (NAF) = 0 A value of OFF results in no change to the system flags. Default: OFF type Specifies the move type to be executed. Table 23-57. Move Types for ADM32 Type C4 C3 Add Destination(s) Cycles IM®TOREG 0 0 Imm. data field + Reg. A, B, R, Register A, B, R, S, or S, or T T REM®TOREG 0 1 Remote data field + Reg. A, B, Register A, B, R, S, or R, S, or T T 2 IM&REMTOREG 1 0 Imm.
Instruction Set www.ti.com Figure 23-85. ADM32 Add and Move Operation for IM®TOREG (Case 00) 25/32-bit addition/move LSBs (HR data field) 32 bits HR Immediate DF + HR Register A, B, R, S or T (dashed for R, S, T) = HR Register A, B, R, S or T (dashed for R, S, T) Figure 23-86.
Instruction Set www.ti.com 23.5.3.6 APCNT (Angle Period Count) Syntax APCNT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer}] [request={NOREQ | GENREQ | QUIET}] [irq={OFF | ON}] type={FALL2FALL | RISE2RISE} [control={OFF | ON}] prv={OFF | ON}}] period={25-bit unsigned integer} data={25-bit unsigned integer} } Figure 23-87. APCNT Program Field (P31:P0) 31 26 25 23 22 21 13 12 9 8 7 6 5 0 0 Request Number BRK Next program address 1110 Int.
Instruction Set www.ti.com APCNT uses the step width flags (SWF0 and SWF1) defined by SCNT to detect period durations shorter than one step, and then disables capture. The edge select encoding is shown in Table 23-58. irq ON generates an interrupt when the edge state is satisfied. OFF prevents an interrupt from being generated. Default: OFF. type Specifies the edge type that triggers the instruction. Default: Fall2Fall. Table 23-58.
Instruction Set www.ti.com } If (GPF == 1) Register T = Period count; If (Data Field register < Step width) { Register T = Period count; APCNT Undflw flag = 1; Period Count = 000000h; } Data field register = 000000h; } else { Register T = Period count; } Prv bit = Current Lx value of HET[2] pin; Jump to Next Program Address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, see Section 23.2.7.
Instruction Set www.ti.com 23.5.3.7 BR (Branch) Syntax BR { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer}] [request={NOREQ | GENREQ | QUIET}] [control={OFF | ON}] [prv={OFF | ON}] cond_addr={label | 9-bit unsigned integer} [pin= {pin number}] event={NOCOND | FALL | RISE | BOTH | ZERO | NAF | LOW | HIGH | C | NC | EQ | Z | NE | NZ | N | PZ | V | NV | ZN | P | GE | LT | GT | LE | LO | HS } [irq={OFF | ON}] } Figure 23-90.
Instruction Set www.ti.com irq ON generates an interrupt when the event occurs that triggers the jump. If irq is set to OFF, no interrupt is generated. Default: OFF. Table 23-59.
Instruction Set www.ti.com 23.5.3.8 CNT (Count) Syntax CNT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer}] [request={NOREQ | GENREQ | QUIET}] [angle_count={OFF | ON}] [reg={A | B | T | NONE}] [comp ={EQ | GE}] [irq={OFF | ON}] [control={OFF | ON}] max={25-bit unsigned integer} [data={25-bit unsigned integer] } Figure 23-93.
Instruction Set www.ti.com angle_count Specifies when the counter is incremented. A value of ON causes the counter value to be incremented only if the new angle flag is set (NAF_global = 1). A value of OFF increments the counter each time the CNT instruction is executed. Default value for this field is OFF. comp When set to EQ the counter is reset, when it is equal to the maximum count. When set to GE the counter is reset, when it is greater or equal to the maximum count. Default: GE.
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.
Instruction Set www.ti.com Figure 23-98. DADM64 Data Field (D31:D0) 31 7 6 0 Data HR Data 25 7 Cycles Two Register modified Register T (implicitly) Description This instruction modifies the data field and the control field at the remote address. The remote data field value is not just replaced, but is added with the DADM64 data field. DADM64 has two distinct syntaxes. In the first syntax, bit values may be set by assigning a value to each of the control fields.
Instruction Set www.ti.com 23.5.3.10 DJZ (Decrement and Jump if Zero)† Syntax DJZ { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] [control={OFF | ON}] [cond_addr={label | 9-bit unsigned integer}] [reg={A | B | T | NONE}] [irq={OFF | ON}] [data={25-bit unsigned integer] } Figure 23-100. DJZ Program Field (P31:P0) 31 26 25 23 0 Request Number 6 3 22 21 BRK 13 12 Next program address 1 9 9 8 7 6 5 0 1010 Res.
Instruction Set www.ti.com cond_addr This field is not optional for the DJZ instruction. irq ON generates an interrupt when the data field reaches zero. No interrupt is generated when the bit is OFF. Default: OFF. data Specifies the 25-bit integer value used as a counter. This counter is decremented each time the DJZ instruction is executed until the counter reaches 0. Default: 0.
Instruction Set www.ti.com 23.5.3.
Instruction Set www.ti.com If R, S, or T registers are selected, and if the 25-bit data field matches, ECMP updates the register with the 32-bit value (D31-D0). If the hr_lr bit is cleared, the pin action will occur after a high resolution delay from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored. This delay is programmed in the data field (D6–D0). The behavior of the pins is governed by the four action options in bits C4:C3.
Instruction Set www.ti.com If (register T is selected) T register = Compare value (32 bit); Jump to Conditional Address; } } elseIf (Z == 1 AND Opposite action == 1) { If (Enable Pin action == 1) { Selected Pin = opposite Pin Action AT next loop resolution clock; } Jump to Next Program Address; } else // Angle Comp. bit == 1 AND NAF_global == 0 { Jump to Next Program Address; } The specific interrupt flag that is triggered depends on the address from which the instruction is executed, see Section 23.2.7.
Instruction Set www.ti.com 23.5.3.12 ECNT (Event Count) Syntax ECNT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] [control={OFF | ON}] [prv={OFF | ON}] [cond_addr={label | 9-bit unsigned integer}] pin={pin number} event={NAF | FALL | RISE | BOTH | ACCUHIGH | ACCULOW} [reg={A | B | R| S | T | NONE}] [irq={OFF | ON}] [data={25-bit unsigned integer] } Figure 23-106.
Instruction Set www.ti.com event The event that triggers the counter. Table 23-61. Event Encoding Format for ECNT Count Conditions Mode Int.
Instruction Set www.ti.com 23.5.3.
Instruction Set www.ti.com Cycles One Register modified T (if save sub bit P[5] is set) Description This instruction compares the magnitude of the 25-bit data value stored in the data field (D31-D7) and the 25-bit value stored in the selected ALU register (A, B, R, S, or T). If the hr_lr bit is reset, pin action will occur after a delay from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored. This delay is programmed in the data field (D6-D0).
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.14 MOV32 (MOVE 32) Syntax MOV32 { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] remote={label | 9-bit unsigned integer} [control={OFF | ON}] [z_cond={OFF | ON}] [init={OFF | ON}]| ON}] type={IMTOREG | IMTOREG&REM | REGTOREM | REMTOREG} [reg={A | B | R | S | T | NONE}] [data={25-bit unsigned integer] [hr_data={7-bit unsigned integer}] } Figure 23-112.
Instruction Set www.ti.com remote Determines the location of the remote address. Default: Current instruction + 1. z_cond When set to OFF the MOV32 performs the move operation specified by the move type whenever it is executed (independent on the state of the Z-Flag). When set to ON the MOV32 performs the move operation specified by the move type only when the Z-Flag is set. init (Optional) Determines whether or not system flags are initialized.
Instruction Set www.ti.com Figure 23-116. MOV32 Move Operation for IMTOREG&REM (Case 01) 25/32-bit move LSBs (HR data field) 32 bits HR Immediate DF HR HR Remote DF Register A, B, R, S or T (dashed for R, S, T) Figure 23-117. MOV32 Move Operation for REGTOREM (Case 10) 25/32-bit move HR Register A, B, R, S, or T (dashed for R, S, T) HR Remote DF LSBs (HR data field = 0 if A or B) Figure 23-118.
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.
Instruction Set www.ti.com Figure 23-121. MOV64 Data Field (D31:D0) 31 7 6 0 Data HR Data 25 7 Cycles One Register modified None Description This instruction modifies the data field and the control field at the remote address. MOV64 has two distinct syntaxes. In the first syntax, bit values may be set by assigning a value to each of the control fields. This syntax is convenient for modifying control fields that are arranged similarly to the format of the MOV64 control field.
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.16 PCNT (Period/Pulse Count) Syntax PCNT { [hr_lr={HIGH | LOW}] [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] [irq={OFF | ON}] type={FALL2RISE | RISE2FALL | FALL2FALL | RISE2RISE} pin={pin number} [control={OFF | ON}] [prv={OFF | ON}] [period={25-bit unsigned integer}] [data={25-bit unsigned integer] [hr_data= {7-bit unsigned integer} } Figure 23-123.
Instruction Set www.ti.com irq (Optional) Specifies whether or not an interrupt is generated. A value of ON sends an interrupt when a new value is captured. If OFF is selected, no interrupt is generated. type (Optional) Determines the type of counter that is implemented. Table 23-66.
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.17 PWCNT (Pulse Width Count) Syntax PWCNT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] [hr_lr={HIGH | LOW}] [control={OFF | ON}] [cond_addr={label | 9-bit unsigned integer} [en_pin_action={OFF | ON}] pin ={pin number} [action={CLEAR | SET | PULSELO | PULSEHI}] [reg={A | B | T | NONE}] [irq={OFF | ON}] [data={25-bit unsigned integer] [hr_data={7-bit unsigned integer}] } Figure 23-126.
Instruction Set www.ti.com The specified pin action is performed as long as the count after count value is decremented is greater than 0. The opposite pin action is performed when the count after decrement just reaches 0. If the hr_lr bit is reset, the opposite pin action will be taken after a HR delay from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored. This delay is programmed in bits [D6:D0]. irq ON generates an interrupt when the data field value reaches 0.
Instruction Set www.ti.com If ([C28:C27] == 11) Generate quiet request on request line [P25:P23]; } Jump to Conditional Address } The specific interrupt flag that is triggered depends on the address from which the instruction is executed, see Section 23.2.7.
Instruction Set www.ti.com 23.5.3.
Instruction Set www.ti.com Figure 23-131. RADM64 Data Field (D31:D0) 31 7 6 0 Data HR Data 25 7 Cycles Normally One Cycle. Two cycles if writing to remote address that is also the next address. Register modified None Description This instruction modifies the data field, the HR data field and the control field at the remote address. The advantage over DADM64 is that It executes one cycle faster. In case the R, S, or T register is selected, the addition is a 32-bit addition.
Instruction Set www.ti.com Table 23-68. RADM64 Control Field Descriptions (continued) irq data hr_data cntl_val Maintains the control field for the remote instruction. Specifies the 25-bit initial value for the data field. If omitted, the field defaults to 0. Seven least significant bits of the 32-bit data field. Default: 0. Specifies the 29 least significant bits of the Control field.
Instruction Set www.ti.com 23.5.3.19 RCNT (Ratio Count) Syntax RCNT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [control={OFF | ON}] divisor={25-bit unsigned integer} [data={25-bit unsigned integer] } Figure 23-133. RCNT Program Field (P31:P0) 31 26 25 23 22 21 13 12 9 8 7 6 5 4 3 1 0 0 Reserved BRK Next program address 1010 Res. 00 Step width Res. 1 6 3 1 9 4 1 2 2 3 1 Figure 23-134.
Instruction Set www.ti.
Instruction Set www.ti.com 23.5.3.20 SCMP (Sequence Compare) Syntax SCMP { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] [control={OFF | ON}] [en_pin_action={OFF | ON}] cond_addr={label | 9-bit unsigned integer} pin ={pin number} [action={CLEAR | SET}] [restart={OFF | ON}] [irq={OFF | ON}] [data={25-bit unsigned integer] } Figure 23-136.
Instruction Set www.ti.com When the compared values match in angle mode, a pin can be set or reset according to the pin action bit (C4). The pin does not change states if the enable pin action bit (C22) is reset. The restart enable bit (C1) provides the option to unconditionally restart a sequence using the X-flag bit of ACMP.
Instruction Set www.ti.com 23.5.3.21 SCNT (Step Count) Syntax SCNT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] step={8 | 16 | 32 | 64} [control={OFF | ON}] gapstart={25-bit unsigned integer} [data={25-bit unsigned integer] } Figure 23-139. SCNT Program Field (P31:P0) 31 26 25 23 22 21 13 12 9 8 7 6 5 4 3 1 0 0 Reserved BRK Next program address 1010 Res. 00 Step width Res. 1 6 3 1 9 4 1 2 2 3 1 Figure 23-140.
Instruction Set www.ti.com Table 23-69. Step Width Encoding for SCNT (continued) P5 P4 Step Width (K) 0 1 16 1 0 32 1 1 64 gapstart Defines the gap start angle, which SCNT writes to register A. The gap start value has no effect on the SCNT instruction, but if the ACNT instruction is being used, register A must contain the correct gap start value. For a typical toothed wheel gear: GAPSTART = (stepwidth × (actual teeth on gear - 1)) + 1.
Instruction Set www.ti.com 23.5.3.22 SHFT (Shift) Syntax SHFT { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] smode={OR0 | OL0 | OR1 | OL1 | ORZ | OLZ | IRM | ILL | IRZ | ILZ} [control={OFF | ON}] [prv={OFF | ON}] [cond_addr={label | 9-bit unsigned integer} cond={UNC | FALL | RISE} pin ={pin number} [reg={A | B | R | S | T | NONE}] [irq={OFF | ON}] [data={25-bit unsigned integer] } Figure 23-142.
Instruction Set www.ti.com smode Shift mode Table 23-70.
Instruction Set www.ti.com } else { Z } else { Z } If ([P3:P0] == 1010) = LSB of the Immediate Data Field; if ([P3:P0] == 1011) = MSB of the Immediate Data Field; } If( (Immediate Data Field == all 0’s) OR (Immediate Data Field == all 1’s)) { if (Interrupt Enable == 1) HETFLG[n] = 1; { /* n depends on address */ } Jump to Conditional Address; } else { Jump to Next Program Address; } Prv.
Instruction Set www.ti.com 23.5.3.23 WCAP (Software Capture Word) Syntax WCAP { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] [hr_lr={HIGH | LOW}] [control={OFF | ON}] [prv={OFF | ON}] [cond_addr={label | 9-bit unsigned integer}] pin ={pin number} event={NOCOND | FALL | RISE | BOTH} reg={A | B | R | S | T | NONE} [irq={OFF | ON}] [data={25-bit unsigned integer] [hr_data={7-bit unsigned integer}] } Figure 23-145.
Instruction Set www.ti.com event Specifies the event that triggers the capture. Table 23-72. Event Encoding Format for WCAP C6 C5 Capture Condition 0 0 Always 0 1 Capture on falling edge 1 0 Capture on rising edge 1 1 Capture on rising and falling edge irq ON generates an interrupt when the capture condition is met. No interrupt is generated for OFF. Default: OFF. data Specifies the 25-bit integer value to be written to the data field or selected register. hr_data HR capture value.
Instruction Set www.ti.com 23.5.3.24 WCAPE (Software Capture Word and Event Count) Syntax WCAPE { [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] [reqnum={3-bit unsigned integer} [request={NOREQ | GENREQ | QUIET}] [control={OFF | ON}] [prv={OFF | ON}] [cond_addr={label | 9-bit unsigned integer} pin ={pin number} event={NOCOND | FALL | RISE | BOTH} [reg={A | B | R | S | T | NONE}] [irq={OFF | ON}] [ts_data={25-bit unsigned integer] [ec_data={7-bit unsigned integer}] } Figure 23-148.
Instruction Set www.ti.com event Specifies the event that triggers the capture. Table 23-73. Event Encoding Format for WCAPE C6 C5 Capture Condition 0 0 Always 0 1 Capture on falling edge 1 0 Capture on rising edge 1 1 Capture on rising and falling edge irq ON generates an interrupt when the capture condition is met. No interrupt is generated for OFF. Default: OFF. ts_data Specifies the 25-bit integer value for [D31:D7] Default: 0.
Chapter 24 SPNU562 – May 2014 High-End Timer Transfer Unit (HTU) Module This chapter describes the high-end timer transfer unit (HTU) module. The HTU is similar to the DMA (Direct Memory Access) module, but it is specialized to transfer NHET (High End Timer) data to or from the microcontroller RAM. NOTE: This chapter describes a superset implementation of the HTU module that includes features and functionality that require DMA.
Overview www.ti.com 24.1 Overview The HET transfer unit is a dedicated direct memory access controller which transfers data between the NHET RAM and RAM buffers located in the main memory address range. This eliminates time consuming CPU accesses to the NHET RAM to gather measurement data or creating output waveforms and thus freeing up the CPU to perform other tasks. 24.1.
Module Operation www.ti.com 24.2 Module Operation The HTU is tightly coupled to the NHET and is not intended to transfer data from other peripheral modules. It initiates transfers with the help of requests generated by the NHET program and configurable control packets. Figure 24-1 shows a system block diagram of the HTU and the main path for the data transfer.
Module Operation www.ti.com Figure 24-2. HTU Block Diagram HTU NHET Control Data Data FIFO Address Normal Memory Protection 8 SCR2 Request Quiet 8 Request Control Packet RAM with Parity Transfers between NHET RAM and the main memory are triggered by 8 different normal NHET requests. Quiet requests are used for specific cases and are discussed in Section 24.2.4.1. Control packets, which store the source and destination addresses, the transfer count and other information (see Section 24.
Module Operation www.ti.com 24.2.1 Data Transfers between Main RAM and NHET RAM 24.2.1.1 Addressing Modes The addressing modes of a control packet need to be distinguished between the main RAM of the CPU and the NHET RAM. Main RAM For each double control packet (see Section 24.2.1.3) the addressing mode for the main RAM (RAM0/1) can be configured to constant or post-increment mode in register IHADDRCT.
Module Operation www.ti.com Figure 24-4. Single Buffer Timing and Memory Representation t1 TU request (1) Element Counter Element Number X X X 5 4 3 2 1 6 7 8 9 10 5 4 3 2 1 1 2 3 4 5 t2 5 4 3 2 1 11 12 13 14 15 Memory View 15 14 13 12 Increasing Address 11 10 9 1 Buffer 8 7 15 6 15 5 15 4 15 3 15 2 15 1 Before the application reads the buffer, it has to disable the control packet to avoid that new data overwrites the buffer while it's being accessed by the application.
Module Operation www.ti.com Figure 24-5. Timing Example for Circular Buffer Mode end of buffer end of buffer request 3 element counter buffer location 2 1 3 2 1 3 1Ch 20h 24h 10h 14h 18h 2 1 3 2 1 3 10h 14h 18h 28h 2Ch 30h 2 1 3 1Ch 20h 24h 2 1 28h 2Ch 30h busy bit frame counter CFTCTx U 2 1 0 2 1 full address CFADDRx U 1Ch 28h 34h 1Ch 28h buffer full flag BFINTFL 24.2.1.
Module Operation www.ti.com Figure 24-6.
Module Operation www.ti.com The examples of Figure 24-7 assumes IETCOUNT=3 (Initial Element Transfer Count), IFTCOUNT=3 (Initial Frame Transfer Count, SIZE=0 (Size of Transfer = 32-bit) and ADDFM=0 (Addressing Mode Main Memory = Post Increment). So there are in total 9 32-bit values in buffer A and B. It also assumes IFADDRB=10h and IFADDRA=40h. "U" means uninitialized. Figure 24-7.
Module Operation www.ti.com There could be a case where the CPU wants to do main memory operations, but does not want the HTU modifying the main memory. It could happen that a request was already active, but the frame transfer hasn't started yet when the application disabled the control packets. The timing diagram in Figure 24-8 shows this scenario. Figure 24-8.
Module Operation www.ti.com NOTE: If the HTUEN bit is cleared during a frame is transferred, then the frame will be completed before the HTU is disabled. 24.2.4 HTU Overload and Request Lost Detection If the number of different HTU request sources is "high", the period between the requests is "short" and/or the initial element counter values are "big", then the HTU could get into a overload situation.
Module Operation www.ti.com Figure 24-10. Timing which Generates No Request Lost Error LRP Signal Quiet Request L1_Instr_DF[31:7] Quiet Request 3 L2_Instr_DF[31:7] 6 1 2 L3_Instr_DF[31:7] 3 2 Delay caused by TU load t1 t2 t3 t4 t5 t6 t7 Frame Request Request Figure 24-11.
Module Operation www.ti.com In the case of very light HTU load, but higher signal requirements (for example, high frequency), the quiet request could also be used to define periods in which the data read by a control packet is safe.
Module Operation www.ti.com If an element transfer of DCP x generates a memory protection error, then: 1. The element counter of DCP x is cleared. 2. All new element transfers on DCP x are stopped. 3. The active busy bit of DCP x is cleared. 4. DCP x is disabled in the CPENA register. The DCPs other than DCP x will not be affected. 5. The FT flag will be set. 6. An error is signaled to the ESM module. 24.2.
Module Operation www.ti.com 24.2.6.1 Parity Bit Mapping and Testing To test the parity checking mechanism, the parity RAM can be made accessible in order to allow manual fault insertion. Once the TEST bit is set, the parity bits are mapped to address FF4E 0200h. When in test mode (the parity RAM is accessible), no parity checking will be done when reading from parity RAM, but parity checking will still be performed for read accesses to the DCP RAM.
Use Cases www.ti.com 24.3 Use Cases 24.3.1 Example: Single Element Transfer with One Trigger Request This example considers the case that the HTU fills a RAM buffer in the main (CPU) data RAM. The HTU reads from the instruction which generates the HTU requests. This example uses a PCNT instruction. Every time the PCNT has captured a new pulse or period value, it will automatically generate a transfer request to the HTU, which then transfers the value from the NHET RAM to the buffer RAM.
Use Cases www.ti.com 32-Bit-Transfer of data fields: Table 24-6 shows how the internal element counter, frame counter and the address registers change over time for the example described above. Every time the PCNT instruction captures a new value it generates a request to the HTU, which starts a frame. At the end of each frame the frame counter decrements. Table 24-6.
Use Cases www.ti.com 24.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields Table 24-8 shows how the internal element counter, frame counter and the address registers change over time assuming the same example as in Section 24.3.2, but now with a transfer size set to 64-bit. The HET address now points to the control field of the instruction, so CF and DF are transferred as 64 bit data. Table 24-8.
HTU Control Registers www.ti.com 24.4 HTU Control Registers Table 24-10 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The offset is relative to the associated peripheral select. See the following sections for detailed descriptions of the registers. The base address for the control registers is FFF7 A400h for HTU1 and FFF7 A500h for HTU2. The address locations not listed, are reserved. Table 24-10.
HTU Control Registers www.ti.com 24.4.1 Global Control Register (HTU GC) Figure 24-14. Global Control Register (HTU GC) [offset = 00] 31 25 24 Reserved 23 17 VBUSHOLD R-0 R/WP-0 15 9 8 16 Reserved HTUEN R-0 R/WP-0 7 1 0 Reserved DEBM Reserved HTURES R-0 R/WP-0 R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 24-11.
HTU Control Registers www.ti.com 24.4.2 Control Packet Enable Register (HTU CPENA) This register enables or disables the individual double control packets (DCP). Figure 24-15. Control Packet Enable Register (HTU CPENA) [offset = 04h] 31 16 Reserved R-0 15 0 CPENA R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 24-12.
HTU Control Registers www.ti.com 24.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0) This register displays the status of individual control packets. Figure 24-16.
HTU Control Registers www.ti.com 24.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1) This register displays the status of individual control packets. Figure 24-17.
HTU Control Registers www.ti.com 24.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3) Figure 24-19. Control Packet (CP) Busy Register 3 (HTU BUSY3) [offset = 14h] 31 25 24 23 17 16 Reserved BUSY6A Reserved BUSY6B R-0 R/WPC-0 R-0 R/WPC-0 15 9 8 7 1 0 Reserved BUSY7A Reserved BUSY7B R-0 R/WPC-0 R-0 R/WPC-0 LEGEND: R/W = Read/Write; R = Read only; WPC = Write 1 in privilege mode only to clear the bit; -n = value after reset Table 24-18.
HTU Control Registers www.ti.com Table 24-19. Active Control Packet and Error Register (HTU ACPE) Field Descriptions (continued) Bit 28-24 Field Value ERRETC Description Error Element Transfer Count If one of the following conditions happens the current element transfer counter of the control packet (specified by ERRCPN) is captured to ERRETC. Please see also Conditions for Frame Transfer Interruption. • Request Lost Error of control packet specified by ERRCPN. This is independent of the CORL bit.
HTU Control Registers www.ti.com 24.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL) Figure 24-21. Request Lost and Bus Error Control Register (HTU RLBECTRL) [offset = 20h] 31 17 15 9 Reserved BERINTENA R-0 R/WP-0 8 7 1 CORL R-0 16 Reserved R/WP-0 0 Reserved RLINTENA R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 24-20.
HTU Control Registers www.ti.com 24.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS) This registers allows to enable the buffer full interrupts for the different control packets. Reading registers BFINTS and BFINTC will return the same bits indicating the status which interrupt is enabled (1) or disabled (0). Figure 24-22.
HTU Control Registers www.ti.com 24.4.11 Interrupt Mapping Register (HTU INTMAP) Figure 24-24. Interrupt Mapping Register (HTU INTMAP) [offset = 2Ch] 31 17 16 Reserved MAPSEL R-0 R/WP-0 15 0 CPINTMAP R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 24-23. Interrupt Mapping Register (HTU INTMAP) Field Descriptions Bit Field 31-17 Reserved 16 MAPSEL 15-0 Value 0 Description Read returns 0. Writes have no effect.
HTU Control Registers www.ti.com 24.4.12 Interrupt Offset Register 0 (HTU INTOFF0) The INTOFF0 register reflects the highest priority interrupt flag bit set in the BERINTFL, RLOSTFL or BFINTFL flag registers with the appropriate CPINTMAP bit set to 0. The priority order (from high to low) is: BER, RLOST, buffer-full. Interrupts for request lines with lower number (higher row in the table next page) have higher priority. Figure 24-25.
HTU Control Registers www.ti.com 24.4.13 Interrupt Offset Register 1 (HTU INTOFF1) This register is organized identically to the INTOFF0 register. The difference is that INTOFF1 reflects the highest priority interrupt flag bit set in the BERINTFL, RLOSTFL or BFINTFL flag registers with the appropriate CPINTMAP bit set to 1. Figure 24-26.
HTU Control Registers www.ti.com 24.4.14 Buffer Initialization Mode Register (HTU BIM) This register enables special applications, where one CP is temporarily disabled, but after having reenabled the CP, filling the buffer should not start back at its beginning, but should continue after the last element of the previous run. Figure 24-27.
HTU Control Registers www.ti.com NOTE: For cases E and F above, after the last frame of a buffer, the HTU sets CFTCTx to zero and CFADDRx to the next address after the buffer. If the DCP was disabled during this state, then both CFTCTx and CFADDRx would contain invalid initialization values. Therefore, if a DCP should continue at its current address, then the software should use one of the following two procedures before it (re-) enables the DCP (as per Table 24-27): 1. If CFTCTx ≠ 0 then set BIM=1 2.
HTU Control Registers www.ti.com 24.4.15 Request Lost Flag Register (HTU RLOSTFL) Figure 24-28. Request Lost Flag Register (HTU RLOSTFL) [offset = 40h] 31 16 Reserved R-0 15 0 CPRLFL R/WPC-0 LEGEND: R/W = Read/Write; R = Read only; WPC = Write 1 in privilege mode to clear the bit; -n = value after reset Table 24-28. Request Lost Flag Register (HTU RLOSTFL) Field Descriptions Bit Field 31-16 Reserved 15-0 CPRLFL Value 0 Description Read returns 0. Writes have no effect.
HTU Control Registers www.ti.com 24.4.17 BER Interrupt Flag Register (HTU BERINTFL) A bus error interrupt results due to an address error or a timeout condition on the main memory access. A bus error will stop the frame transfer. Please see Section 24.2.3. Figure 24-30. BER Interrupt Flag Register (HTU BERINTFL) [offset = 48h] 31 16 Reserved R-0 15 0 BERINTFL R/WPC-0 LEGEND: R/W = Read/Write; R = Read only; WPC = Write 1 in privilege mode to clear the bit; -n = value after reset Table 24-30.
HTU Control Registers www.ti.com 24.4.18 Memory Protection 1 Start Address Register (HTU MP1S) This register configures the start address of memory protection region 1. Figure 24-31. Memory Protection 1 Start Address Register (HTU MP1S) [offset = 4Ch] 31 16 STARTADDRESS1 R/WP-0 15 0 STARTADDRESS1 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 24-31.
HTU Control Registers www.ti.com 24.4.20 Debug Control Register (HTU DCTRL) This register allows to create watchpoints on access to a certain location. It is intended to help debug the application execution during program development. Figure 24-33.
HTU Control Registers www.ti.com 24.4.21 Watch Point Register (HTU WPR) This register defines the main memory address of the watchpoint. Figure 24-34. Watch Point Register (HTU WPR) [offset = 58h] 31 16 WP R/WS-0 15 0 WP R/WS-0 LEGEND: R/W = Read/Write; R = Read only; WS = Write in suspend mode only; -n = value after reset Table 24-34.
HTU Control Registers www.ti.com 24.4.23 Module Identification Register (HTU ID) This register is for TI internal purposes and allows to keep track of the HTU module version on different devices. Figure 24-36. Module Identification Register (HTU ID) [offset = 60h] 31 24 23 16 Reserved CLASS R-0 R - Module Class Number 15 8 7 0 TYPE REV R - Class Subtype Number R - Module Revision Number LEGEND: R = Read only; -n = value after reset Table 24-36.
HTU Control Registers www.ti.com 24.4.24 Parity Control Register (HTU PCR) Figure 24-37. Parity Control Register (HTU PCR) [offset = 64h] 31 17 Reserved R-0 15 9 8 16 COPE R/WP-0 7 4 3 0 Reserved TEST Reserved PARITY_ENA R-0 R/WP-0 R-0 R/WP-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 24-37. Parity Control Register (HTU PCR) Field Descriptions Bit 31-17 16 Field Reserved Value 0 COPE Description Read returns 0.
HTU Control Registers www.ti.com 24.4.25 Parity Address Register (HTU PAR) Figure 24-38. Parity Address Register (HTU PAR) [offset = 68h] 31 17 15 9 16 Reserved PEFT R-0 R/WPC-0 8 0 Reserved PAOFF R-0 R-X LEGEND: R/W = Read/Write; R = Read only; WPC = Write 1 in privilege mode to clear the bit; -n = value after reset; X = undefined Table 24-38. Parity Address Register (HTU PAR) Field Descriptions Bit 31-10 16 Field Reserved Value 0 PEFT Description Read returns 0.
HTU Control Registers www.ti.com 24.4.26 Memory Protection Control and Status Register (HTU MPCS) Figure 24-39.
HTU Control Registers www.ti.com Table 24-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions (continued) Bit Field 15-12 Reserved 11-8 CPNUM1 7-6 Reserved 5 INTENA01 4 3 2 1 Value 0 Description Read returns 0. Writes have no effect. Control Packet Number for single memory protection region configuration. CPNUM1 holds the number of the CP, which has caused the first memory protection error when only one memory protection region is used.
HTU Control Registers www.ti.com Table 24-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions (continued) Bit 0 1106 Field Value REG0ENA Description Region Enable 0 0 The protection outside the memory region defined by the MP0S and MP0E registers is not enabled. This means the HTU can access any implemented memory space. 1 The protection outside the memory region defined by the MP0S and MP0E registers is enabled.
HTU Control Registers www.ti.com 24.4.27 Memory Protection Start Address Register 0 (HTU MP0S) This register configures the start address of memory protection region 0 Figure 24-40. Memory Protection Start Address Register 0 (HTU MP0S) [offset = 74h] 31 16 STARTADDRESS0 R/WP-0 15 0 STARTADDRESS0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 24-40.
Double Control Packet Configuration Memory www.ti.com 24.5 Double Control Packet Configuration Memory All bits marked "reserved' are implemented in RAM and will be initialized to unknown values after power on. Reserved locations can be written and read but should be written with zero to ensure future compatibility. The HTU RAM can be cleared with the system RAM initialization function. Table 24-42 provides a summary of the memory configuration.
Double Control Packet Configuration Memory www.ti.com 24.5.1 Initial Full Address A Register (HTU IFADDRA) Figure 24-42. Initial Full Address A Register (HTU IFADDRA) 31 16 IFADDRA R/WP-X 15 0 IFADDRA R/WP-X LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown Table 24-43. Initial Full Address A Register (HTU IFADDRA) Field Descriptions Bit 31-0 Field Description IFADDRA Initial Address of Buffer A in main memory.
Double Control Packet Configuration Memory www.ti.com 24.5.3 Initial NHET Address and Control Register (HTU IHADDRCT) Figure 24-44.
Double Control Packet Configuration Memory www.ti.com Table 24-45. Initial NHET Address and Control Register (HTU IHADDRCT) Field Descriptions (continued) Bit Field 15-13 Reserved 12-2 IHADDR Value 0 Description Read returns 0. Writes have no effect. Initial NHET Address The initial NHET Address points to the NHET field, which is the first element of the frame. The NHET address (Bits 12:2) increments by one for each 32-bit NHET field and starts with zero at the first 32-bit field in the NHET RAM.
Double Control Packet Configuration Memory www.ti.com 24.5.5 Current Full Address A Register (HTU CFADDRA) Figure 24-46. Current Full Address A Register (HTU CFADDRA) 31 16 CFADDRA R/WP-X 15 0 CFADDRA R/WP-X LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown Table 24-47.
Double Control Packet Configuration Memory www.ti.com 24.5.6 Current Full Address B Register (HTU CFADDRB) Figure 24-47. Current Full Address B Register (HTU CFADDRB) 31 16 CFADDRB R/WP-X 15 0 CFADDRB R/WP-X LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown Table 24-48.
Double Control Packet Configuration Memory www.ti.com 24.5.7 Current Frame Count Register (HTU CFCOUNT) The current frame count register enables the software to find out the recent element in the frozen buffer while the counter of the active buffer decrements. Figure 24-48.
Examples www.ti.com 24.6 Examples 24.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP Table 24-50. Application Examples for Setting the Transfer Modes of CP A and B of a DCP CP A CP B One shot Not used Buffer A can be used as a "one shot" buffer. A buffer full interrupt enabled for CP A can signal reaching the end of the buffer. Auto switch One shot Can double the buffer size for a "one shot" buffer.
Examples www.ti.com After some time the CPU intends to read buffer B: B1 B2 B3 B4 B5 B6 B7 B8 CPU enables CP A and disables CP B by writing to the CPENA register. After this switch, the HTU fills buffer A. Filling buffer A starts with its initial full address and initial frame counter CPU waits for CP B busy bit equals zero Optional: CPU verifies that the CP B request lost flag is not set.
Chapter 25 SPNU562 – May 2014 General-Purpose Input/Output (GIO) Module This chapter describes the general-purpose input/output (GIO) module. The GIO module provides the family of devices with input/output (I/O) capability. The I/O pins are bidirectional and bit-programmable. The GIO module also supports external interrupt capability. Topic 25.1 25.2 25.3 25.4 25.5 25.6 ........................................................................................................................... Overview....
Overview www.ti.com 25.1 Overview The GIO module offers general-purpose input and output capability. It supports up to eight 8-bit ports for a total of up to 64 GIO terminals. Each of these 64 terminals can be independently configured as input or output and configured as required by the application. The GIO module also supports generation of interrupts whenever a rising edge or falling edge or any toggle is detected on up to 32 of these GIO terminals.
Quick Start Guide www.ti.com 25.2 Quick Start Guide The GIO module comprises two separate components: an input/output (I/O) block and an interrupt generation block. Figure 25-2 and Figure 25-3 show what the user should do after reset to configure the GIO module as I/O or for generating interrupts. Figure 25-2.
Quick Start Guide www.ti.com Figure 25-3. Interrupt Generation Function Quick Start Flow Chart Power-On Reset Enable Peripherals by setting PENA bit in Clock Control Register (0xFFFFFFD0) Enable GIO through PCR (Check devicedatasheet for the peripheral select) Initialize vector interrupt table - Map GIO low level interrupt and / or high level interrupt service routine to pre-defined device specific interrupt channel.
Functional Description of GIO Module www.ti.com 25.3 Functional Description of GIO Module As shown earlier in Figure 25-1 the GIO module comprises of two separate components: an input/output (I/O) block and an interrupt block. 25.3.1 I/O Functions The I/O block allows each GIO terminal to be configured for use as a general-purpose input or output in the application. The GIO module supports multiple registers to control the various aspects of the input and output functions. These are described as follows.
Functional Description of GIO Module • • www.ti.com Rising or falling edge can be selected via the GIOPOL register (Section 25.5.3). If interrupt is required to be generated on both rising and falling edges, this can be configured via the GIOINTDET register (Section 25.5.2). Select the interrupt priority Low or High-level interrupt can be selected through the GIOLVLSET and GIOLVLCLR registers (Section 25.5.5.1 and Section 25.5.5.2). Individual interrupt flags are set in the GIOFLG register (Section 25.
Device Modes of Operation www.ti.com 25.4 Device Modes of Operation The GIO module behaves differently in different modes of operation. There are two main modes: • Emulation mode • Power-down mode (low-power mode) 25.4.1 Emulation Mode Emulation mode is used by debugger tools to stop the CPU at breakpoints to read registers. NOTE: Emulation Mode and Emulation Registers Emulation mode is a mode of operation of the device and is separate from the GIO emulation registers (GIOEMU1 and GIOEMU2).
GIO Control Registers www.ti.com 25.5 GIO Control Registers Table 25-1 shows the summary of the GIO registers. The registers are accessible in 8-, 16-, and 32-bit reads or writes. The start address for the GIO module is FFF7 BC00h. The GIO module supports up to 8 ports. Refer the device datasheet to identify the actual number of GIO ports and the number of pins in each GIO port implemented on this device. The GIO module supports up to 4 interrupt-capable ports.
GIO Control Registers www.ti.com 25.5.1 GIO Global Control Register (GIOGCR0) The GIOGCR0 register contains one bit that controls the module reset status. Writing a zero (0) to this bit puts the module in a reset state. After system reset, this bit must be set to 1 before normal operations can begin on this module. Figure 25-5 and Table 25-2 describe this register. Figure 25-5.
GIO Control Registers www.ti.com 25.5.2 GIO Interrupt Detect Register (GIOINTDET) The GIOINTDET register provides the flexibility to either ignore the polarity of the edges that are recognized as an interrupt, in which case both rising and falling edges are recognized, or recognizing the interrupt on specifically a rising or falling edge as determined by the GIOPOL register. To ensure recognition of the signal as an edge, the signal must maintain the new level for at least one VCLK cycle.
GIO Control Registers www.ti.com 25.5.3 GIO Interrupt Polarity Register (GIOPOL) The GIOPOL register controls the polarity - rising edge (low to high) or falling edge (high to low) - that sets the flag. To ensure recognition of the signal as an edge, the signal must maintain the new level for at least one VCLK cycle. When the device is in low power mode, the interrupts are no longer triggered by an edge, but instead by a level.
GIO Control Registers www.ti.com 25.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) The GIOENASET and GIOENACLR registers control which interrupt-capable pins are actually configured as interrupts. If the interrupt is enabled, the rising or falling or both edges on the selected pin lead to an interrupt. 25.5.4.1 GIOENASET Register Figure 25-8 and Table 25-5 describe this register.
GIO Control Registers www.ti.com 25.5.4.2 GIOENACLR Register This register disables the interrupt. Figure 25-9 and Table 25-6 describe this register. Figure 25-9. GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h] 31 24 23 16 GIOENACLR 3 GIOENACLR 2 R/W-0 R/W-0 15 8 7 0 GIOENACLR 1 GIOENACLR 0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25-6.
GIO Control Registers www.ti.com 25.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR) The GIOLVLSET and GIOLVLCLR registers configure the interrupts as high-level (level 1) or low-level (level 2) going to the VIM. Each interrupt is individually configured. • The high-level interrupts are recorded to GIOOFF1 and GIOEMU1. • The low-level interrupts are recorded to GIOOFF2 and GIOEMU2. 25.5.5.
GIO Control Registers www.ti.com Table 25-7. GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions (continued) Bit Field 7-0 GIOLVLSET 0 Value Description GIO high-priority interrupt for pins GIOA[7:0]. 0 Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2 and GIOEMU2. Write: Writing a 0 to this bit has no effect. 1 Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to GIOOFF1 and GIOEMU1.
GIO Control Registers www.ti.com 25.5.5.2 GIOLVLCLR Register The GIOLVLCLR register is used to configure an interrupt as a low-level interrupt going to the VIM. An interrupt can be configured as a low-level interrupt by writing a 1 into the corresponding bit of the GIOLVLCLR register. Writing a 0 has no effect. Figure 25-11 and Table 25-8 describe this register. Figure 25-11.
GIO Control Registers www.ti.com 25.5.6 GIO Interrupt Flag Register (GIOFLG) The GIOFLG register contains flags indicating that the transition edge (as set in GIOINTDET and GIOPOL) has occurred. The flag is also cleared by reading the appropriate interrupt offset register (GIOOFF1 or GIOOFF2). Figure 25-12 and Table 25-9 describe this register. Figure 25-12.
GIO Control Registers www.ti.com 25.5.7 GIO Offset Register 1 (GIOOFF1) The GIOOFF1 register provides a numerical offset value that represents the pending external interrupt with high priority. The offset value can be used to locate the position of the interrupt routine in a vector table in application software. Figure 25-13 and Table 25-10 describe this register. NOTE: Reading this register clears it, GIOEMU1 and the corresponding flag bit in the GIOFLG register.
GIO Control Registers www.ti.com 25.5.8 GIO Offset B Register (GIOOFF2) The GIOOFF2 register provides a numerical offset value that represents the pending external interrupt with low priority. The offset value can be used to locate the position of the interrupt routine in a vector table in application software. Figure 25-14 and Table 25-11 describe this register. NOTE: Reading this register clears it, GIOEMU2 and the corresponding flag bit in the GIOFLG register.
GIO Control Registers www.ti.com 25.5.9 GIO Emulation A Register (GIOEMU1) The GIOEMU1 register is a read-only register. The contents of this register are identical to the contents of GIOOFF1. The intention for the this register is that software can use it without clearing the flags. Figure 25-15 and Table 25-12 describe this register. NOTE: The corresponding flag in the GIOFLG register is not cleared when the GIOEMU1 register is read. Figure 25-15.
GIO Control Registers www.ti.com 25.5.10 GIO Emulation B Register (GIOEMU2) The GIOEMU2 register is a read-only register. The contents of this register are identical to the contents of GIOOFF2. The intention for the this register is that software can use it without clearing the flags. Figure 25-16 and Table 25-13 describe this register. NOTE: The corresponding flag in the GIOFLG register is not cleared when the GIOEMU2 register is read. Figure 25-16.
GIO Control Registers www.ti.com 25.5.11 GIO Data Direction Registers (GIODIR[A-B]) The GIODIR register controls whether the pins of a given port are configured as inputs or outputs. Figure 25-17 and Table 25-14 describe this register. Figure 25-17. GIO Data Direction Registers (GIODIR[A-B]) [offset = 34h, 54h] 31 16 Reserved R-0 15 8 7 0 Reserved GIODIR[7:0] R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25-14.
GIO Control Registers www.ti.com 25.5.13 GIO Data Output Registers (GIODOUT[A-B]) Values in the GIODOUT register specify the output state (high = 1 or low = 0) of the pins of the port when they are configured as outputs. Figure 25-19 and Table 25-16 describe this register. NOTE: Values in the GIODSET register set the data output control register bits to 1 regardless of the current value in the GIODOUT bits. Figure 25-19.
GIO Control Registers www.ti.com 25.5.15 GIO Data Clear Registers (GIODCLR[A-B]) Values in this register clear the data output register (GIO Data Output Register [A-H]) bit to 0 regardless of its current value. The contents of this register reflect the contents of GIODOUT. Figure 25-21 and Table 25-18 describe this register. Figure 25-21.
GIO Control Registers www.ti.com 25.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]) Values in this register enable or disable the pull control capability of the pins. Figure 25-23 and Table 2520 describe this register. Figure 25-23. GIO Pull Disable Registers (GIOPULDIS[A-B]) [offset = 4Ch, 6Ch] 31 16 Reserved R-0 15 8 7 0 Reserved GIOPULDIS[7:0] R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25-20.
I/O Control Summary www.ti.com 25.6 I/O Control Summary The behavior of the output buffer and the pull control is summarized in Table 25-22. Table 25-22.
Chapter 26 SPNU562 – May 2014 Controller Area Network (DCAN) Module This chapter describes the controller area network (DCAN) module. NOTE: This chapter describes a superset implementation of the DCAN module. Consult your device-specific datasheet to identify the applicability of the DMA-related features, the number of instantiations of the DCAN IP, and the number of mailboxes supported on your specific device being used. Topic .............................................................................
Overview www.ti.com 26.1 Overview The Controller Area Network is a high-integrity, serial, multi-master communication protocol for distributed real-time applications. This CAN module is implemented according to ISO 11898-1 and is suitable for industrial, automotive and general embedded communications. 26.1.1 Features The DCAN module provides the following features: Protocol • Supports CAN protocol version 2.
CAN Blocks www.ti.com The CAN module internally handles functions such acceptance filtering, transfer of messages from and to the Message RAM, handling of transmission requests as well as the generation of interrupts or DMA requests. 26.2 CAN Blocks The DCAN Module, shown in Figure 26-1, comprises of the following basic blocks. 26.2.1 CAN Core The CAN Core consists of the CAN Protocol Controller and the Rx/Tx Shift Register. It handles all ISO 11898-1 protocol functions. 26.2.
CAN Blocks www.ti.com 26.2.4 Message RAM Interface The Interface Register sets control the CPU read and write accesses to the Message RAM. There are three interface registers IF1, IF2, and IF3: • IF1 and IF2 Interface Registers sets for read and write access. • IF3 Interface Register set for read access only. The Interface Registers have the same word-length as the Message RAM. Additional information can be found in Section 26.6. 26.2.
CAN Bit Timing www.ti.com 26.3 CAN Bit Timing The DCAN supports bit rates between less than 1 kBit/s and 1000 kBit/s. Each member of the CAN network has its own clock generator, typically derived from a crystal oscillator. The Bit timing parameters can be configured individually for each CAN node, creating a common Bit rate even though the CAN nodes’ oscillator periods (fosc) may be different. 26.3.
CAN Bit Timing www.ti.com 26.3.1.1 Synchronization Segment The Synchronization Segment (Sync_Seg) is the part of the bit time where edges of the CAN bus level are expected to occur. If an edge occurs outside of Sync_Seg, its distance to the Sync_Seg is called the phase error of this edge. 26.3.1.2 Propagation Time Segment This part of the bit time is used to compensate physical delay times within the CAN network.
CAN Bit Timing www.ti.com 26.3.2 DCAN Bit Timing Registers In the DCAN, the bit timing configuration is programmed in two register bytes, additionally a third byte for a baud rate prescaler extension of 4 bits (BREP) is provided.
CAN Bit Timing www.ti.com The resulting configuration is written into the Bit Timing Register: Tseg2 = Phase_Seg2 - 1 Tseg1 = Phase_Seg1 + Prop_Seg - 1 SJW = SynchronizationJumpWidth - 1 BRP = Prescaler - 1 26.3.2.2 Calculation of BRP Values If Baud and CAN_CLK(VCLK) are already known, the BRP/BRPE values need to be calculated to be programmed into the register. It is calculated using the following equation: BRP = CAN_CLK / (BAUD)(1 + TSEG1 + TSEG2) (35) 26.3.2.
CAN Module Configuration www.ti.com 26.3.2.4 Example for Bit Timing at Low Baudrate In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s. tq delay of bus driver delay of receiver circuit delay of bus line (40m) tProp tSJW tTSeg1 tTSeg2 tSync-Seg bit time tolerance for CAN_CLK 100 200 80 220 1 4 5 3 1 9 0.
CAN Module Configuration www.ti.com Figure 26-3. CAN Bit-timing Configuration Normal Mode Set Init = 1 Set CCE = 1 Wait for Init =1 Initialization Mode Write Bit timing values into BTR Clear CCE and Init CCE = 0 , Init =0 Wait for Init =0 Normal Mode Step 1: Enter “initialization mode” by setting the Init (Initialization) bit in the CAN Control Register. While the Init bit is set, the message transfer from and to the CAN bus is stopped, and the status of the CAN_TX output is recessive (high).
CAN Module Configuration www.ti.com NOTE: The module would not come out of the “initialization mode” if any incorrect BTR values are written in step 4. 26.4.2.2 Configuration of Message Objects The whole Message RAM should be configured before putting the CAN into operation. All the message objects are deactivated by default. You should configure the message object that are to be used to a particular identifier. you can change the configuration of any message object or deactivate it when required.
Message RAM www.ti.com 26.5 Message RAM The DCAN Message RAM contains message objects and ECC bits for the message objects. 26.5.1 Structure of Message Objects Figure 26-4 shows the structure of a message object. The grayed fields are those parts of the message object which are represented in dedicated registers. For example, the transmit request flags of all message objects are represented in centralized transmit request registers. Figure 26-4.
Message RAM www.ti.com Table 26-2. Message Object Field Descriptions (continued) Name Value EOB Description End of Block 0 The message object is part of a FIFO Buffer block and is not the last message object of this FIFO Buffer block. 1 The message object is a single message object or the last message object in a FIFO Buffer Block. Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer.
Message RAM www.ti.com 26.5.2 Addressing Message Objects in RAM The starting location of a particular message object in RAM is: Message RAM base address + (message object number) × 0x20. This means that Message Object 1 starts at offset 0x0020; Message Object 2 starts at offset 0x0040, and so on. NOTE: 0 is not a valid message object number. At address 0x0000, message object number 64 is located. Writing to the address of an unimplemented message object may overwrite an implemented message object.
Message RAM www.ti.com 26.5.3 Message RAM Representation in Debug/Suspend Mode In Debug/Suspend mode, the Message RAM will be memory mapped. This allows the external debug unit to access the Message RAM. NOTE: During Debug/Suspend Mode, the Message RAM cannot be accessed via the IFx register sets. Figure 26-5.
Message RAM www.ti.com 26.5.5 ECC RAM On devices with SECDED implementation for the message RAM, the ECC bits are stored in a dedicated ECC RAM area which is memory mapped as follows: The location of the ECC bits for a particular message object in RAM is: Message RAM base address + 0x1000 + (message object number) * 0x20. NOTE: ’0’ is not a valid message object number. At address 0x1000, the ECC bits of the last implemented message object are located.
Message Interface Register Sets www.ti.com 26.6 Message Interface Register Sets Accesses to the Message RAM are performed via the Interface Register sets: • Interface Register 1 and 2 (IF1 and IF2) • Interface Register 3 (IF3) The IF3 register set can be configured to automatically receive control and user data from the Message RAM when a message object has been updated after reception of a CAN message. The CPU does not need to initiate the transfer from Message RAM to IF3 register set.
Message Interface Register Sets www.ti.com 26.6.2 Using Message Interface Register Sets 1 and 2 The Command Register addresses the desired message object in the Message RAM and specifies whether a complete message object or only parts should be transferred. The data transfer is initiated by writing the message number to the bits [7:0] of the Command Register.
Message Interface Register Sets www.ti.com 26.6.3 Message Interface Register 3 The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from Message RAM by CPU. The intention of this feature of IF3 is to provide an interface for the DMA to read packets efficiently. Table 26-5.
Message Object Configurations www.ti.com 26.7 Message Object Configurations This section describes the possible message object configurations for CAN communication. 26.7.1 Configuration of a Transmit Object for Data Frames Figure 26-9 shows how a Transmit Object can be initialized. Figure 26-9. Initialization of a Transmit Object MsgVal 1 Arb appl. Data appl. Mask appl. EoB 1 Dir 1 NewDat 0 MsgLst 0 RxIE 0 TxIE appl. IntPnd 0 RmtEn appl.
Message Object Configurations www.ti.com 26.7.4 Configuration of a Single Receive Object for Remote Frames Figure 26-11 shows how a Receive Object for Remote Frames can be initialized. Figure 26-11. Initialization of a Single Receive Object for Remote Frames MsgVal 1 Arb appl. Data appl. Mask appl. EoB 1 Dir 1 NewDat 0 MsgLst 0 RxIE appl. TxIE 0 IntPnd 0 RmtEn 0 TxRqst 0 Receive Objects for Remote Frames may be used to monitor Remote Frames on the CAN bus.
Message Handling www.ti.com 26.8 Message Handling When initialization is finished, the DCAN module synchronizes itself to the traffic on the CAN bus. It does acceptance filtering on received messages and stores those frames that are accepted into the designated message objects. The application has to update the data of the messages to be transmitted and enable and request their transmission. The transmission is requested automatically when a matching Remote Frame is received.
Message Handling www.ti.com 26.8.3 Transmission of Messages in Event Driven CAN Communication If the shift register of the CAN Core is ready for loading and if there is no data transfer between the IFx Registers and Message RAM, the d bits in the Message Valid Register and the TxRqst bits in the Transmission Request Register are evaluated.
Message Handling www.ti.com NOTE: After the update of the Transmit Object, the Interface Register set will contain a copy of the actual contents of the object, including the part that had not been updated. 26.8.
Message Handling www.ti.com The actual value of NewDat shows whether a new message has been received since last time when this message object was read. The actual value of MsgLst shows whether more than one message have been received since the last time when this message object was read. MsgLst will not be automatically reset. 26.8.10 Requesting New Data for a Receive Object By means of a Remote Frame, the CPU may request another CAN node to provide new data for a receive object.
Message Handling www.ti.com Figure 26-12.
CAN Message Transfer www.ti.com 26.9 CAN Message Transfer Once the DCAN is initialized and Init bit is reset to zero, the CAN Core synchronizes itself to the CAN bus and is ready for message transfer as per the configured message objects. The CPU may enable the interrupt lines (setting IE0 and IE1 to 1) at the same time when it clears Init and CCE. The status interrupts EIE and SIE may be enabled simultaneously. The CAN communication can be carried out in any of the following two modes: 1.
CAN Message Transfer www.ti.com 26.9.2 Auto-Bus-On Per default, after the DCAN has entered Bus-Off state, the CPU can start a Bus-Off-Recovery sequence by resetting Init bit. If this is not done, the module will stay in Bus-Off state. The DCAN provides an automatic Auto-Bus-On feature which is enabled by bit ABO in CAN Control Register. If set, the DCAN will automatically start the Bus-Off-Recovery sequence.
Interrupt Functionality www.ti.com 26.10.2 Status Change Interrupts The events WakeUpPnd, RxOk, TxOk and LEC in Error and Status Register (DCAN ES) belong to the Status Change Interrupts. The Status Change Interrupt group can be enabled by bit in CAN Control Register. If SIE is set, a Status Change Interrupt will be generated at each CAN frame, independent of bus errors or valid CAN communication, and also independent of the Message RAM configuration.
Global Power Down Mode www.ti.com Figure 26-14. CAN Interrupt Topology 2 Message Object Interrupts IntPndMux(1) Message Object 1 RxIE Receive OK Transmit OK IE1 TxIE DCAN1INT Last Message Object IntPndMux(n) RxIE Receive OK Transmit OK Message Object Interrupts can be Routed to DCAN0INT or DCAN1INT Line IE0 TxIE DCAN0INT To Status Interrupt Details of Interrupt Mapping for actual device will be described in the device specific data sheet. 26.
Local Power Down Mode www.ti.com 26.12 Local Power Down Mode Besides the centralized power down mechanism controlled by the PCR module (global power down, see Section 26.15), the DCAN supports a local power down mode which can be controlled within the DCAN control registers. 26.12.1 Entering Local Power Down Mode The local power down mode is requested by setting the PDR bit in CAN Control Register. The DCAN then finishes all transmit requests of the message objects.
GIO Support www.ti.com Figure 26-15.
Test Modes www.ti.com 26.14 Test Modes The DCAN provides several test modes which are mainly intended for production tests or self test. For all test modes, Test bit in the CAN Control Register needs to be set to one. This enables write access to the Test Register. NOTE: When using any of the Loop Back modes, it must be ensured by software that all message transfers are finished before setting the Init bit to ‘1’. 26.14.
Test Modes www.ti.com 26.14.2 Loop Back Mode The Loop Back Mode is mainly intended for hardware self-test functions. In this mode, the CAN Core uses internal feedback from Tx output to Rx input. Transmitted messages are treated as received messages, and can be stored into message objects if they pass acceptance filtering. The actual value of the CAN_RX input pin is disregarded by the CAN Core. Transmitted messages still can be monitored at the CAN_TX pin.
Test Modes www.ti.com 26.14.3 External Loop Back Mode The External Loop Back Mode is similar to the Loop Back Mode, however it includes the signal path from CAN Core to Tx pin, the Tx pin itself, and the signal path from Tx pin back to CAN Core. When External Loop Back Mode is selected, the input of the CAN core is connected to the input buffer of the Tx pin. With this configuration, the Tx pin IO circuit can be tested. External Loop Back Mode can be activated by setting bit ExL in Test Register to 1.
Test Modes www.ti.com 26.14.4 Loop Back Combined with Silent Mode It is also possible to combine Loop Back Mode and Silent Mode by setting bits LBack and Silent at the same time. This mode can be used for a “Hot Selftest”, that is, the DCAN hardware can be tested without affecting the CAN network. In this mode, the CAN_RX pin is disconnected from the CAN Core and no dominant bits will be sent on the CAN_TX pin.
SECDED Mechanism www.ti.com 26.15 SECDED Mechanism The DCAN module provides a single error correction and double error detection (SECDED) mechanism to ensure data integrity of Message RAM data. For each message object (136 bits) in the Message RAM, 9 ECC bits will be calculated. See Section 26.5.5. The ECC bits are stored in a dedicated RAM. They will be generated on write accesses and will be checked on read accesses.
Debug/Suspend Mode www.ti.com 26.16 Debug/Suspend Mode The module supports the usage of an external debug unit by providing functions like pausing DCAN activities and making Message RAM content accessible via VBUSP interface. Before entering debug/suspend mode, the circuit will either wait until a started transmission or reception will be finished and Bus idle state is recognized, or immediately interrupt a current transmission or reception. This is depending on bit IDS in CAN Control Register.
DCAN Control Registers www.ti.com Table 26-6. DCAN Control Registers (continued) Offset Acronym Register Description Section 9Ch DCAN NWDAT12 New Data 12 Register Section 26.17.16 A0h DCAN NWDAT34 New Data 34 Register Section 26.17.16 A4h DCAN NWDAT56 New Data 56 Register Section 26.17.16 A8h DCAN NWDAT78 New Data 78 Register Section 26.17.16 ACh DCAN INTPNDX Interrupt Pending X Register Section 26.17.17 B0h DCAN INTPND12 Interrupt Pending 12 Register Section 26.17.
DCAN Control Registers www.ti.com 26.17.1 CAN Control Register (DCAN CTL) NOTE: The Bus-Off recovery sequence (see CAN specification) cannot be shortened by setting or resetting Init bit. If the module goes Bus-Off, it will automatically set the Init bit and stop all bus activities. When the Init bit is cleared by the application again, the module will then wait for 129 occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal operation.
DCAN Control Registers www.ti.com Table 26-7. CAN Control Register (DCAN CTL) Field Descriptions (continued) Bit Field 19 DE2 Value Description Enable DMA request line for IF2 0 Disabled 1 Enabled Note: A pending DMA request for IF2 remains active until first access to one of the IF2 registers. 18 DE1 Enable DMA request line for IF1 0 Disabled 1 Enabled Note: A pending DMA request for IF1 remains active until first access to one of the IF1 registers.
DCAN Control Registers www.ti.com Table 26-7. CAN Control Register (DCAN CTL) Field Descriptions (continued) Bit 3 2 1 0 1184 Field Value EIE Description Error Interrupt Enable 0 Disabled - PER, BOff and EWarn bits cannot generate an interrupt. 1 Enabled - PER, BOff and EWarn bits can generate an interrupt at DCAN0INT line and affect the Interrupt Register. SIE Status Change Interrupt Enable 0 Disabled - WakeUpPnd, RxOk, TxOk and LEC bits cannot generate an interrupt.
DCAN Control Registers www.ti.com 26.17.2 Error and Status Register (DCAN ES) Interrupts are generated by bits PER, BOff, and EWarn (if EIE bit in CAN Control Register is set) and by bits WakeUpPnd, RxOk, TxOk, and LEC (if SIE bit in CAN Control Register is set). A change of bit EPass will not generate an Interrupt. NOTE: Reading the Error and Status Register clears the WakeUpPnd, PER, RxOk and TxOk bits and set the LEC to value of 7.
DCAN Control Registers www.ti.com Table 26-8. Error and Status Register (DCAN ES) Field Descriptions (continued) Bit Field 4 RxOK 3 2-0 Value Description Received a message successfully 0 No message has been successfully received since the last time when this bit was read by the CPU. This bit is never reset by DCAN internal events.
DCAN Control Registers www.ti.com 26.17.3 Error Counter Register (DCAN ERRC) Figure 26-22. Error Counter Register (DCAN ERRC) [offset = 08h] 31 16 Reserved R-0 15 14 8 7 0 RP REC TEC R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 26-9. Error Counter Register (DCAN ERRC) Field Descriptions Bit 31-16 15 Field Reserved Value 0 RP Description These bits are always read as 0. Writes have no effect.
DCAN Control Registers www.ti.com 26.17.4 Bit Timing Register (DCAN BTR) NOTE: This register is only writable if CCE and Init bits in the CAN Control Register are set. The CAN bit time may be programmed in the range of 8 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 CAN_CLK periods. With a CAN_CLK of 8 MHz and BRPE = 00, the reset value of 2301h configures the DCAN for a bit rate of 500kBit/s. For details see Section 26.3.2.1. Figure 26-23.
DCAN Control Registers www.ti.com 26.17.5 Interrupt Register (DCAN INT) Figure 26-24. Interrupt Register (DCAN INT) [offset = 10h] 31 24 23 16 Reserved Int1ID R-0 R-0 15 0 Int0ID R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26-11. Interrupt Register (DCAN INT) Field Descriptions Bit Field 31-24 Reserved 23-16 Int1ID Value 0 Description These bits are always read as 0. Writes have no effect.
DCAN Control Registers www.ti.com 26.17.6 Test Register (DCAN TEST) For all test modes, the Test bit in CAN Control Register needs to be set to one. If Test bit is set, the RDA, EXL, Tx1, Tx0, LBack and Silent bits are writable. Bit Rx monitors the state of pin CAN_RX and therefore is only readable. All Test Register functions are disabled when Test bit is cleared. NOTE: The Test Register is only writable if Test bit in CAN Control Register is set.
DCAN Control Registers www.ti.com 26.17.7 Parity Error Code Register (DCAN PERR) If a double bit error is detected, the PER flag will be set in the Error and Status Register. This bit is not reset by the SECDED mechanism; it must be reset by reading the Error and Status Register. In addition to the PER flag, the SECDED Error Code Register will indicate the memory area where the double bit error has been detected (message number).
DCAN Control Registers www.ti.com 26.17.9 ECC Diagnostic Status Register (DCAN ECCDIAG STAT) Figure 26-28. ECC Diagnostic Status Register (DCAN ECCDIAG STAT) [offset = 28h] 31 16 Reserved R-0 15 9 8 7 1 0 Reserved DEFLG DIAG Reserved SEFLG DIAG R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset; U = Undefined Table 26-15.
DCAN Control Registers www.ti.com 26.17.10 ECC Control and Status Register (DCAN ECC CS) Figure 26-29. ECC Control and Status Register (DCAN ECC CS) [offset = 2Ch] 31 28 27 24 23 20 19 16 Reserved SBE_EVT_EN Reserved ECCMODE R-0 R/WP-5h R-0 R/WP-Ah 15 9 8 7 1 0 Reserved DEFLG Reserved SEFLG R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset; U = Undefined Table 26-16.
DCAN Control Registers www.ti.com 26.17.11 ECC Single Bit Error Code Register (DCAN ECC SERR) If an ECC single bit error is detected, the SEFLG flag will be set in the ECC Control and Status Register. In addition to the SEFLG flag, the ECC Single Bit Error Code Register will indicate the memory area where the single bit error has been detected (message object number only).
DCAN Control Registers www.ti.com 26.17.12 Auto-Bus-On Time Register (DCAN ABOTR) NOTE: On write access to the CAN Control register while Auto-Bus-On timer is running, the AutoBus-On procedure will be aborted. During Debug/Suspend mode, running Auto-Bus-On timer will be paused. Figure 26-31. Auto-Bus-On Time Register (DCAN ABOTR) [offset = 80h] 31 0 ABO Time R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 26-18.
DCAN Control Registers www.ti.com 26.17.14 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) These registers hold the TxRqst bits of the implemented message objects. By reading out these bits, the CPU can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the CPU via the IF1/IF2 Message Interface Registers, or by the Message Handler after reception of a remote frame or after a successful transmission. Figure 26-33.
DCAN Control Registers www.ti.com 26.17.15 New Data X Register (DCAN NWDAT X) With the New Data X Register, the CPU can detect if one or more bits in the different New Data Registers are set. Each register bit represents a group of eight message objects. If at least on of the NewDat bits of these message objects are set, the corresponding bit in the New Data X Register will be set. Figure 26-37.
DCAN Control Registers www.ti.com 26.17.16 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) These registers hold the NewDat bits of the implemented message objects. By reading out these bits, the CPU can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message Handler after reception of a data frame or after a successful transmission. Figure 26-38.
DCAN Control Registers www.ti.com 26.17.17 Interrupt Pending X Register (DCAN INTPND X) With the Interrupt Pending X Register, the CPU can detect if one or more bits in the different Interrupt Pending Registers are set. Each bit of this register represents a group of eight message objects. If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. Figure 26-42.
DCAN Control Registers www.ti.com 26.17.18 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78) These registers hold the IntPnd bits of the implemented message objects. By reading out these bits, the CPU can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message Handler after a reception or a successful transmission. Figure 26-43.
DCAN Control Registers www.ti.com 26.17.19 Message Valid X Register (DCAN MSGVAL X) With the Message Valid X Register, the CPU can detect if one or more bits in the different Message Valid Registers are set. Each bit of this register represents a group of eight message objects. If at least one of the MsgVal bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. Figure 26-47.
DCAN Control Registers www.ti.com 26.17.20 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78) These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the CPU can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message Handler after a reception or a successful transmission. Figure 26-48.
DCAN Control Registers www.ti.com 26.17.21 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78) The IntMux flag determine for each message object, which of the two interrupt lines (DCAN0INT or DCAN1INT) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN Control Register.
DCAN Control Registers www.ti.com 26.17.22 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD) The IF1/IF2 Command Register configure and Initiate the transfer between the IF1/IF2 Register sets and the Message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command Register.
DCAN Control Registers www.ti.com Table 26-24. IF1/IF2 Command Register Field Descriptions Bit 31-24 23 22 Field Reserved Value 0 WR/RD Description These bits are always read as 0. Writes have no effect.
DCAN Control Registers www.ti.com Table 26-24.
DCAN Control Registers www.ti.com 26.17.23 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object. The function of the relevant message objects bits is described in Section 26.5.1. NOTE: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write protected. Figure 26-58.
DCAN Control Registers www.ti.com 26.17.24 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB) The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The function of the relevant message objects bits is described in Section 26.5.1. The Arbitration bits ID, Xtd, and Dir are used to define the identifier and type of outgoing messages and (together with the Mask bits Msk, MXtd, and MDir) for acceptance filtering of incoming messages.
DCAN Control Registers www.ti.com Table 26-26. IF1/IF2 Arbitration Register Field Descriptions Bit Field 31 MsgVal Value Description Message Valid 0 The message object is ignored by the Message Handler. 1 The message object is used by the Message Handler. Note: The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register. MsgVal must also be reset if the messages object is no longer used in operation.
DCAN Control Registers www.ti.com 26.17.25 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL) The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object. The function of the relevant message objects bits is described in Section 26.5.1. NOTE: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write protected. Figure 26-62.
DCAN Control Registers www.ti.com Table 26-27. IF1/IF2 Message Control Register Field Descriptions Bit 31-16 15 14 13 12 Field Value Reserved 0 NewDat Description These bits are always read as 0. Writes have no effect. New Data 0 No new data has been written into the data portion of this message object by the Message Handler since the last time this flag was cleared by the CPU. 1 The Message Handler or the CPU has written new data into the data portion of this message object.
DCAN Control Registers www.ti.com 26.17.26 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB) The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first Figure 26-64.
DCAN Control Registers www.ti.com 26.17.27 IF3 Observation Register (DCAN IF3OBS) The IF3 register set can automatically be updated with received message objects without the need to Initiate the transfer from Message RAM by CPU (Additional information can be found in Section 26.5.1). The observation flags (Bits [4:0]) in the IF3 Observation register are used to determine, which data sections of the IF3 Interface Register set have to be read in order to complete a DMA read cycle.
DCAN Control Registers www.ti.com Table 26-28.
DCAN Control Registers www.ti.com 26.17.28 IF3 Mask Register (DCAN IF3MSK) Figure 26-69. IF3 Mask Register (DCAN IF3MSK) [offset = 144h] 31 30 29 MXtd MDir Rsvd 28 Msk[28:16] 16 R-1 R-1 R-1 R-1FFFh 15 0 Msk[15:0] R-FFFFh LEGEND: R = Read; -n = value after reset Table 26-29. IF3 Mask Register (DCAN IF3MSK) Field Descriptions Bit Field 31 MXtd Value Description Mask Extended Identifier 0 The extended identifier bit (IDE) has no effect on acceptance filtering.
DCAN Control Registers www.ti.com 26.17.29 IF3 Arbitration Register (DCAN IF3ARB) Figure 26-70. IF3 Arbitration Register (DCAN IF3ARB) [offset = 148h] 31 30 29 MsgVal Xtd Dir 28 ID[28:16] 16 R-0 R-0 R-0 R-0 15 0 ID[15:0] R-0 LEGEND: R = Read; -n = value after reset Table 26-30. IF3 Arbitration Register (DCAN IF3ARB) Field Descriptions Bit Field 31 MsgVal Value Description Message Valid 0 The message object is ignored by the Message Handler.
DCAN Control Registers www.ti.com 26.17.30 IF3 Message Control Register (DCAN IF3MCTL) Figure 26-71. IF3 Message Control Register (DCAN IF3MCTL) [offset = 14Ch] 31 16 Reserved R-0 15 14 13 12 11 10 9 8 NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7 6 4 3 0 EoB Reserved DLC R-0 R-0 R-0 LEGEND: R = Read; -n = value after reset Table 26-31.
DCAN Control Registers www.ti.com Table 26-31. IF3 Message Control Register (DCAN IF3MCTL) Field Descriptions (continued) Bit Field 7 EoB Value Description End of Block 0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block 1 The message object is a single message object or the last message object in a FIFO Buffer block Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer.
DCAN Control Registers www.ti.com 26.17.32 IF3 Update Enable Registers (DCAN IF3UPD12 to DCAN IF3UPD78) The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UpdEn flag is set. This means that an active NewDat flag of this message object (for example, due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set.
DCAN Control Registers www.ti.com 26.17.33 CAN TX IO Control Register (DCAN TIOC) The CAN_TX pin of the DCAN module can be used as general-purpose IO pin if CAN function is not needed. NOTE: The values of the IO Control registers are only writable if Init bit of CAN Control Register is set. The OD, Func, Dir, and Out bits of the CAN TX IO Control register are forced to certain values when Init bit of CAN Control Register is reset (see bit descriptions). Figure 26-78.
DCAN Control Registers www.ti.com Table 26-33. CAN TX IO Control Register (DCAN TIOC) Field Descriptions (continued) Bit 0 Field Value Description In CAN_TX data in. 0 The CAN_TX pin is at logic low (0). 1 The CAN_TX pin is at logic high (1). Note: When CAN_TX pin is connected to a CAN transceiver, an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed (for example, while the DCAN module is reset). 26.17.
DCAN Control Registers www.ti.com Table 26-34. CAN RX IO Control Register (DCAN RIOC) Field Descriptions (continued) Bit 2 Field Value Dir Description CAN_RX data direction. This bit controls the direction of the CAN_RX pin when it is configured to be in GIO mode only (RIOC.Func = 0). 0 The CAN_RX pin is an input. 1 The CAN_RX pin is an output. Forced to 0, if Init bit of CAN control register is reset. 1 0 Out CAN_RX data out write.
Chapter 27 SPNU562 – May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP) This chapter provides the specifications for a 16-bit configurable synchronous multi-buffered multi-pin serial peripheral interface (MibSPI). This chapter also provides the specifications for MibSPI with Parallel Pin Option (MibSPIP). The MibSPI is a programmable-length shift register used for high-speed communication between external peripherals or other microcontrollers.
Overview www.ti.com 27.1 Overview 27.1.1 Features The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (two to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller.
Overview www.ti.
Overview www.ti.com 27.1.3 MibSPI /SPI Configurations Table 27-2.
Basic Operation www.ti.com Figure 27-1.
Basic Operation www.ti.com 27.2.1.2.2 Data Sequencing when All Bits Shifted into RXSHIFT Register • If both SPIBUF and RXBUF are empty, the received data in RX shift register is directly copied into SPIBUF and the receive DMA request (if enabled) is generated and the receive-interrupt (if enabled) is generated. The RXEMPTY flag in SPIBUF is cleared at the same time. • If SPIBUF is already full at the end of receive completion, the RX shift register contents is copied to RXBUF.
Basic Operation www.ti.com 27.2.2.1 Data Handling for TX and RX Transfer Groups 27.2.2.1.1 Data Sequencing of a Transmit Data In multi-buffer mode, any buffer that needs to be transmitted over by the SPI, should be associated with a Transfer Group. Each TG (Transfer Group) will have a Trigger Source based on which it’ll be triggered. Once a TG is triggered, the buffers belonging to it will be transmitted. Sequencer(FSM) controls the data flow from the multi-buffer RAM to the Shift Register.
Basic Operation www.ti.com The SPI generates a request on the RX_DMA_REQ line each time the received data is copied to the SPIBUF. 27.2.3.2 DMA in Multi-Buffer Mode The MibSPI provides sophisticated programmable DMA control logic that completely eliminates the necessity of CPU intervention for data transfers, once programmed. When the multi-buffer mode is used, the DMA enable bit in the SPIINT0 register is ignored.
Basic Operation www.ti.com 27.2.4 Interrupts There are two levels of vectorized interrupts supported by the SPI. These interrupts can be caused under the following circumstances: • Transmission error • Receive overrun • Receive complete (receive buffer full) • Transmit buffer empty These interrupts may be enabled or disabled via the SPIINT0 register.
Basic Operation www.ti.com Figure 27-4. TG Interrupt Structure 0 Finished ENAx LVLx 0 Suspended TG x LVL 0 1 1 ENAx Vector LVL 1 LVLx X +1 Bit 0 The RXOVRN interrupt is generated when a buffer in the RXRAM is overwritten by a new received word. While writing newly received data to a RXRAM location, if the RXEMPTY bit of the corresponding location is 0, then the RXOVR bit will be set to 1 during the write operation, so that the buffer starts to indicate an overrun.
Basic Operation www.ti.com 27.2.5 Physical Interface The SPI can be configured via software to operate as either a master or a slave. The MASTER bit (SPIGCR1[0]) selects the configuration of the SPISIMO and SPISOMI pins. CLKMOD bit (SPIGCR1[1]) determines whether an internal or external clock source will be used. The slave chip select (SPISCS[7:0]) pins, are used when communicating with multiple slave devices.
Basic Operation www.ti.com 27.2.5.2 Four-Pin Mode with Chip Select The three-pin option and the four-pin options of the SPI / MibSPI are identical in the master mode (CLKMOD = 1), except that the four-pin option uses either SPIENA or SPISCS [7:0] pins. The I/O directions of these pins are determined by the CLKMOD control bit as SPI / MibSPI and not general purpose I/O. 27.2.5.2.1 Four-Pin Option with SPISCS In master mode, each chip select signal is used to select a specific slave.
Basic Operation www.ti.com 27.2.5.2.2 Four-Pin Option with SPIENA The SPIENA operates as a WAIT signal pin. For both the slave and the master, the SPIENA pin must be configured to be functional (SPIPC0[8] = 1). In this mode, an active low signal from the slave on the SPIENA pin allows the master SPI to drive the clock pulse stream. A high signal tells the master to hold the clock signal (and delay SPI activity).
Basic Operation www.ti.com 27.2.5.3 Five-Pin Operation (Hardware Handshaking) Five-pin operation combines the functionality of three-pin mode, plus the enable pin and one or more chip select pins. The result is full hardware handshaking. To use this mode, both the SPIENA pin and the required number of SPISCS [3:0] pins must be configured as functional pins. If the SPIENA pin is in high-z mode (ENABLE_HIGHZ = 1), the slave SPI will put this signal into the highimpedance state by default.
Basic Operation www.ti.com 27.2.6 Advanced Module Configuration Options 27.2.6.1 Data Formats To support multiple different types of slaves in one SPI network, four independent data word formats are implemented that allow configuration of individual data word length, polarity, phase, and bit rate. Each word transmitted can select which data format to use via the bits DFSEL[1:0] in its control field from one of the four data word formats. Same data format can be supported on multiple chip selects.
Basic Operation www.ti.com 27.2.6.2 Clocking Modes SPICLK may operate in four different modes, depending on the choice of phase (delay/no delay) and the polarity (rising edge/falling edge) of the clock. The data input and output edges depend on the values of both POLARITY and PHASE as shown in Table 27-3. Table 27-3. Clocking Modes POLARITY PHASE 0 0 Action Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
Basic Operation www.ti.com Figure 27-14. Clock Mode with Polarity = 1 and Phase = 0 Write SPIDAT SPICLK 1 2 3 4 5 6 7 SPISIMO MSB D6 D5 D4 D3 D2 D1 LSB SPISOMI D7 D6 D5 D4 D3 D2 D1 D0 8 receive sample Data is output on the falling edge of SPICLK. Input data is latched on the rising edge of SPICLK. Figure 27-15.
Basic Operation www.ti.com 27.2.6.2.1 Data Transfer Example Figure 27-16 illustrates a SPI data transfer between two devices using a character length of five bits. Figure 27-16.
Basic Operation www.ti.com 27.2.6.3 Decoded and Encoded Chip Select (Master Only) In this device the SPI can connect to up to 4 individual slave devices using chip-selects by routing one wire to each slave. The 4 chip selects in the control field are directly connected to the 4 pins. The default value of each chip select (not active) can be configured via the register CSDEF.
Basic Operation www.ti.com 27.2.6.4.2 Transmit-End-to-Chip-Select-Inactive-Delay (T2CDELAY) T2CDELAY is used in master mode only. It defines a hold time for the slave device that delays the chip select deactivation by a multiple of VBUSPCLK cycles after the last bit is transferred. T2CDELAY can be configured between 2 and 256 VBUSPCLK cycles. The hold time value is calculated as: t T2CDELAY= (T2CDELAY +1) × VCLK Period Figure 27-18 is the timing diagram when T2CDELAY of 4 VCLK Cycles. Figure 27-18.
Basic Operation www.ti.com 27.2.6.4.4 Chip-Select-Active-to-ENA-Signal-Active-Time-Out (C2EDELAY) C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response. C2EDELAY defines the maximum time between the SPI / MibSPI activating the chip select signal and the addressed slave responding by activating the ENA signal. C2EDELAY defines a time-out value as a multiple of SPI clocks.
Basic Operation www.ti.com 27.2.6.5.2.1 CSHOLD Bit in Master Mode Each word in a master-mode SPI can be individually initialized for one of the two modes via the CSHOLD bit in its control field. If the CSHOLD bit is set in the control field of a word, the chip select signal will not be deactivated until the next control field is loaded with new chip select information.
Basic Operation www.ti.com 27.2.6.6 Parallel Mode (Multiple SIMO/SOMI Support, not available on all devices) In order to increase throughput, the parallel mode of the SPI enables the module to send data over more than one data line (Parallel 2, 4 or 8). When parallel mode is used, the data length must be set as 16 bits. Only module MIBSPIP5 supports Parallel Mode. This feature increases throughput by 2 for 2 pins, by 4 for 4 pins, or by 8 for 8 pins.
Basic Operation www.ti.com 27.2.6.6.1 Parallel Mode Block Diagram Figure 27-22 and Figure 27-23 show the parallel connections to the SPI shift register. Figure 27-22. Block Diagram Shift Register, MSB First SIMO0 SIMO1 SIMO2 SIMO3 SIMO4 SIMO5 SIMO6 SIMO7 SIMO[7:0] Parallel mode MULTIPLEXER SPI Shift register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOMI0 SOMI1 SOMI2 SOMI3 SOMI4 SOMI5 SOMI6 SOMI7 DEMULTIPLEXER SOMI[7:0] Figure 27-23.
Basic Operation www.ti.com 27.2.6.6.2 Parallel Mode Pin Mapping, MSB First Table 27-4 and Table 27-5 describe the SOMI and SIMO pin mapping when the SPI is used in parallel mode (1, 2, 4, 8) pin mode, MSB first. NOTE: MSB-first or LSB-first can be configured using the SHIFTDIRx bit of the SPIFMTx registers. Table 27-4.
Basic Operation www.ti.com 27.2.6.6.3 Parallel Mode Pin Mapping, MSB-First, LSB-First Table 27-6 and Table 27-7 describe the SIMO and SOMI pin mapping when SPI is used in parallel mode (1, 2, 4, 8) pin mode, LSB first. Table 27-6. Pin Mapping for SIMO Pin with LSB First Parallel Mode Shift Register Bit SIMO[7:0] 1 0 0 2 8 1 0 0 12 3 8 2 4 1 4 8 0 0 14 7 12 6 10 5 8 4 6 3 4 2 2 1 0 0 Table 27-7.
Basic Operation www.ti.com 27.2.6.6.4 2-Data Line Mode (MSB First, Phase 0, Polarity 0) In 2-data line mode (master mode) the shift register bits 15 and 7 will be connected to the pins SIMO[1] and SIMO[0], and the shift register bits 8 and 0 will be connected to the pins SOMI[1] and SOMI[0] or vice versa in slave mode. After writing to the SPIDAT0/SPIDAT1 register, the bits 15 and 7 will be output on SIMO[1] and SIMO[0] on the rising edge if SPICLK.
Basic Operation www.ti.com 27.2.6.6.5 4-Data Line Mode (MSB First, Phase 0, Polarity 0) In 4-data line mode (master mode) the shift register bits 15, 11, 7, and 3 will be connected to the pins SIMO[3], SIMO[2], SIMO[1], and SIMO[0], and the shift register bits 12, 8, 4, and 0 will be connected to the pins SOMI[3], SOMI[2], SOMI[1], and SOMI[0] (or vice versa in slave mode).
Basic Operation www.ti.com 27.2.6.6.6 8-Data Line Mode (MSB First, Phase 0, Polarity 0) In 8-data line mode (master mode) the shift register bits 15, 13, 11, 9, 7, 5 and 3 will be connected to the pins SIMO[7], SIMO[6], SIMO[5], SIMO[4], SIMO[3], SIMO[2], SIMO[1], and SIMO[0], and the shift-register bits 14, 12, 10, 8, 6, 4, and 0 will be connected to the pins SOMI[7], SOMI[6], SOMI[5], SOMI[4], SOMI[3], SOMI[2], SOMI[1], and SOMI[0] (or vice versa in slave mode).
Basic Operation www.ti.com Figure 27-29. 8 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0) VCLK SPICLK SIMO[7] 15 14 SIMO[6] 13 12 SIMO[5] 11 10 SIMO[4] 9 8 SIMO[3] 7 6 SIMO[2] 5 4 SIMO[1] 3 2 SIMO[0] 1 0 SOMI[7] 15 14 SOMI[6] 13 12 SOMI[5] 11 10 SOMI[4] 9 8 SOMI[3] 7 6 SOMI[2] 5 4 SOMI[1] 3 2 SOMI[0] 1 0 NOTE: Modulo Count Parallel Mode is not supported in this device. 27.2.6.
Basic Operation www.ti.com Figure 27-30. Multi-buffer in Slave Mode Buffer RAM TG 0 Trigger CTRL & Tx STAT & Rx Seq. TG 14 Trigger RXBUF CS decoder Shift Register SPISCS [3:0] SPISOMI SPICLK SPIENA Parity SPISIMO When the SPIDAT1 register is updated, the enable signal is released, and the transaction could begin. If the enable signal is not used, the master should wait for 6 VBUSPCLK cycles before sending the clock to begin the transaction.
Basic Operation www.ti.com 27.2.6.8 Transfer Groups The size of the multi-buffer RAM depends on the implementation. It comprises 0 to 128/256 buffers, whereas 0 buffers considers the special case of no multi-buffer RAM. Each entry in the multi-buffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The multi-buffer RAM can be partitioned into multiple transfer group with variable number of buffers each. 27.2.6.8.
Basic Operation www.ti.com 27.2.7 General-Purpose I/O All of the SPI pins may be programmed via the SPIPCx control registers to be either functional or generalpurpose I/O pins. If the SPI function is to be used, application software must ensure that at least the SPICLK pin and the SOMI and/or SIMO pins are configured as SPI functional pins, and not as GIO pins, or else the SPI state machine will be held in reset, preventing SPI transactions.
Basic Operation www.ti.com 27.2.9.2 ENA Signal Time-Out (Master Only) The SPI in master mode waits for the hardware handshake signal (ENA) coming from the addressed slave before performing a data transfer. To avoid stalling the SPI by a non-responsive slave device a time-out value can be configured. If the time-out counter overflows before an active ENA signal is sampled the TIMEOUT flag in the status register SPIFLG is set and the TIMEOUT flag in the status field of the corresponding buffer is set.
Basic Operation www.ti.com 27.2.10 Test Features 27.2.10.1 Internal Loop-Back Test Mode (Master Only) The internal loop-back self-test mode can be utilized to test the SPI transmit and receive paths, including the shift registers, the SPI buffer registers, and the parity generator.
Basic Operation www.ti.com Figure 27-31. I/O Paths During I/O Loopback Modes tr TX SHIFT REG TX LPBK_TYPE RXP_ENA RX SHIFT REG Reeeeeeeeee RX Checks the analog loopback path through the receive buffer Checks the analog loopback path through the transmit buffer Digital loopback path 1 This diagram is intended to illustrate loopback paths and therefore may omit some normal-mode paths. 27.2.10.2.
Basic Operation www.ti.com 27.2.11 Module Configuration MibSPI/MibSPIP can be configured to function as Normal SPI and Multi-buffered SPI. Upon power-up or a system-level reset, each bit in the module registers is set to a default state. The registers are writable only after the RESET bit is set to 1. 27.2.11.1 Compatibility (SPI) Mode Configuration The following list details the configuration steps that software should perform prior to the transmission or reception of data.
Basic Operation www.ti.com 27.2.11.2 MibSPI Mode Configuration The following list details the configuration steps that software should perform prior to the transmission or reception of data in MIBSPI mode. As long as SPIENA is held low the entire time that the SPI is being configured, the order in which the registers are programmed is not important. • Enable SPI by setting RESET bit. • Set MSPIENA to 1 to get access to multi-buffer mode registers.
Control Registers www.ti.com 27.3 Control Registers This section describes the SPI control, data, and pin registers. The registers support 8-bit, 16-bit and 32bit writes. The offset is relative to the associated base address of this module in a system. The base address for the control registers is FFF7 F400h for MibSPI1, FFF7 F600h for MibSPI2, FFF7 F800h for MibSPI3, FFF7 FA00h for MibSPI4, and FFF7 FC00h for MibSPI5.
Control Registers www.ti.com Table 27-8. SPI Registers (continued) Offset Acronym Register Description 124h PAR_ECC_STAT Parity/ECC Status Register Section 27.3.38 Section 128h UERRADDR1 Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM Section 27.3.39 12Ch UERRADDR0 Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM Section 27.3.40 130h RXOVRN_BUF_ADDR RXRAM Overrun Buffer Address Register Section 27.3.
Control Registers www.ti.com 27.3.2 SPI Global Control Register 1 (SPIGCR1) Figure 27-33. SPI Global Control Register 1 (SPIGCR1) [offset = 04h] 31 25 24 23 17 16 Reserved SPIEN Reserved LOOPBACK R-0 R/W-0 R-0 R/WP-0 15 9 8 Reserved 7 POWERDOWN R-0 2 1 0 Reserved CLKMOD MASTER R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 27-10.
Control Registers www.ti.com Table 27-10. SPI Global Control Register 1 (SPIGCR1) Field Descriptions (continued) Bit Field 0 Value Description MASTER SPISIMO/SPISOMI pin direction determination. Sets the direction of the SPISIMO and SPISOMI pins. Note: For master-mode operation of the SPI, MASTER bit should be set to 1 and CLKMOD bit can be set either 1 or 0. The master-mode SPI can run on an external clock on SPICLK. For slave mode operation, both the MASTER and CLKMOD bits should be cleared to 0.
Control Registers www.ti.com Table 27-11. SPI Interrupt Register (SPIINT0) Field Descriptions (continued) Bit 9 Field Value TXINTENA Description Causes an interrupt to be generated every time data is written to the shift register, so that the next word can be written to TXBUF. Setting this bit will generate an interrupt if the TXINTFLG bit (SPI Flag Register (SPIFLG)[9]) is set to 1. 0 No interrupt will be generated upon TXINTFLG being set to 1.
Control Registers www.ti.com 27.3.4 SPI Interrupt Level Register (SPILVL) Figure 27-35. SPI Interrupt Level Register (SPILVL) [offset = 0Ch] 31 16 Reserved R-0 15 10 9 8 Reserved TXINTLVL RXINTLVL R-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 Reserved RXOVRNINTL Reserved BITERRLVL DESYNCLVL PARERRLVL TIMEOUTLVL DLENERRLVL R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-12.
Control Registers www.ti.com 27.3.5 SPI Flag Register (SPIFLG) Software must check all flag bits when reading this register. Figure 27-36.
Control Registers www.ti.com Table 27-13. SPI Flag Register (SPIFLG) Field Descriptions (continued) Bit 8 Field Value RXINTFLG Description Receiver-full interrupt flag. This flag is set when a word is received and copied into the buffer register (SPIBUF). If RXINTEN is enabled, an interrupt is also generated.
Control Registers www.ti.com Table 27-13. SPI Flag Register (SPIFLG) Field Descriptions (continued) Bit 3 Field Value DESYNCFLG Description Desynchronization of slave device. Desynchronization monitor is active in master mode only. This flag can be cleared by one of the following methods: • Write a 1 to this bit. • Set SPIENA bit to 0. 2 0 No slave desynchronization detected. 1 A slave device is desynchronized.
Control Registers www.ti.com 27.3.6 SPI Pin Control Register 0 (SPIPC0) NOTE: Register bits vary by device Register bits 31:24 and 23:16 of SPIPC0 to SPIPC9 reflect the number of SIMO/SOMI data lines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices with less than 8 data lines, only a subset of these bits are available. Unimplemented bits return 0 upon read and are not writable. Figure 27-37.
Control Registers www.ti.com Table 27-14. SPI Pin Control (SPIPC0) Field Descriptions (continued) Bit Field 9 Value CLKFUN 8 SPI clock function. This bit determines whether the SPICLK pin is to be used as a general-purpose I/O pin, or as a SPI functional pin. 0 The SPICLK pin is a GIO pin. 1 The SPICLK pin is a SPI functional pin. ENAFUN 7-0 Description SPIENA function. This bit determines whether the SPIENA pin is to be used as a general-purpose I/O pin or as a SPI functional pin.
Control Registers www.ti.com Table 27-15. SPI Pin Control Register (SPIPC1) Field Descriptions (continued) Bit Field 23-16 Value SIMODIR Description SPISIMOx direction. Controls the direction of SPISIMOx when used for general-purpose I/O. If SPISIMOx pin is used as a SPI functional pin, the I/O direction is determined by the MASTER bit in the SPIGCR1 register. Note: Duplicate Control Bits for SPISIMO. Bit 16 is not physically implemented. It is a mirror of Bit 10.
Control Registers www.ti.com 27.3.8 SPI Pin Control Register 2 (SPIPC2) NOTE: Register bits vary by device Register bits 31:24 and 23:16 of this register reflect the number of SIMO/SOMI data lines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices with less than 8 data lines, only a subset of these bits are available. Unimplemented bits return 0 upon read and are not writable. Figure 27-39.
Control Registers www.ti.com 27.3.9 SPI Pin Control Register 3 (SPIPC3) NOTE: Register bits vary by device Register bits 31:24 and 23:16 of this register reflect the number of SIMO/SOMI data lines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices with less than 8 data lines, only a subset of these bits are available. Unimplemented bits return 0 upon read and are not writable. Figure 27-40.
Control Registers www.ti.com Table 27-17. SPI Pin Control Register 3 (SPIPC3) Field Descriptions (continued) Bit Field 8 Value ENADOUT 7-0 Description SPIENA data out write. Only active when the SPIENA pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0 The SPIENA pin is logic 0. 1 The SPIENA pin is logic 1. SCSDOUT SPISCSx data out write.
Control Registers www.ti.com Table 27-18. SPI Pin Control Register 4 (SPIPC4) Field Descriptions (continued) Bit Field 23-16 Value SIMOSET Description SPISIMOx data out set. This bit is only active when the SPISIMOx pin is configured as a generalpurpose output pin. Bit 10 or bit 16 can be used to set the SOMI0 pin. If a 32-bit write is performed, bit 10 will have priority over bit 16. 0 Read: SPISIMIx is logic 0. Write: No effect. 1 Read: SPISIMIx is logic 1.
Control Registers www.ti.com 27.3.11 SPI Pin Control Register 5 (SPIPC5) NOTE: Register bits vary by device Register bits 31:24 and 23:16 of this register reflect the number of SIMO/SOMI data lines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices with less than 8 data lines, only a subset of these bits are available. Unimplemented bits return 0 upon read and are not writable. Figure 27-42.
Control Registers www.ti.com Table 27-19. SPI Pin Control Register 5 (SPIPC5) Field Descriptions (continued) Bit Field 9 Value CLKCLR Description SPICLK data out clear. This bit is only active when the SPICLK pin is configured as a generalpurpose output pin. 0 Read: The current value on SPICLK is 0. Write: No effect. 1 Read: The current value on SPICLK is 1. Write: Logic 0 is placed on SPICLK pin if it is in general-purpose output mode. 8 ENACLR SPIENA data out clear.
Control Registers www.ti.com Table 27-20. SPI Pin Control Register 6 (SPIPC6) Field Descriptions Bit 31-24 Field Value SOMIPDR Description SPISOMIx open drain enable. This bit enables open drain capability for the SPISOMIx pin if the following conditions are met: • SOMIDIRx = 1 (SPISOMIx pin configured in GIO mode as an output) • SOMIDOUTx = 1 Bit 11 or bit 24 can both be used to enable open-drain for SOMI0. If a 32-bit write is performed, bit 11 will have priority over bit 24.
Control Registers www.ti.com 27.3.13 SPI Pin Control Register 7 (SPIPC7) NOTE: Register bits vary by device Register bits 31:24 and 23:16 of this register reflect the number of SIMO/SOMI data lines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices with less than 8 data lines, only a subset of these bits are available. Unimplemented bits return 0 upon read and are not writable.
Control Registers www.ti.com Table 27-21. SPI Pin Control Register 7 (SPIPC7) Field Descriptions (continued) Bit Field 9 Value CLKPDIS 8 CLK pull control enable/disable. This bit enables pull control capability for the pin SPICLK pin if it is in input mode regardless of whether it is in functional or GIO mode. 0 Pull control on the CLK pin is enabled. 1 Pull control on the CLK pin is disabled. ENAPDIS 7-0 Description ENABLE pull control enable/disable.
Control Registers www.ti.com Table 27-22. SPI Pin Control Register 8 (SPIPC8) Field Descriptions (continued) Bit 23-16 Field Value SIMOPSEL Description SPISIMOx pull select. This bit selects the type of pull logic at the SPISIMOx pin. Note: Bit 10 or bit 16 can be used to set pull-select for SPISOMI0. If a 32-bit write is performed, bit 10 will have priority over bit 16. 15-12 11 10 9 8 7-0 Reserved 0 Pull down on SPISIMOx pin 1 Pull up on SPISIMOx pin 0 Read returns 0.
Control Registers www.ti.com 27.3.16 SPI Transmit Data Register 1 (SPIDAT1) Figure 27-47. SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch] 31 29 28 27 26 Reserved CSHOLD Rsvd WDEL 25 DFSEL 24 23 CSNR 16 R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 15 0 TXDATA R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-24.
Control Registers www.ti.com 27.3.17 SPI Receive Buffer Register (SPIBUF) Figure 27-48. SPI Receive Buffer Register (SPIBUF) [offset = 40h] 31 30 29 28 27 26 25 24 RXEMPTY RXOVR TXFULL BITERR DESYNC PARITYERR TIMEOUT DLENERR R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0 23 16 LCSNR R-0 15 0 RXDATA R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-25.
Control Registers www.ti.com Table 27-25. SPI Receive Buffer Register (SPIBUF) Field Descriptions (continued) Bit Field 28 BITERR Value Description Bit error.There was a mismatch of internal transmit data and transmitted data. 0 No bit error occurred. Note: This flag is cleared to 0 when the RXDATA portion of the SPIBUF register is read. 1 27 DESYNC A bit error occurred.
Control Registers www.ti.com 27.3.18 SPI Emulation Register (SPIEMU) Figure 27-49. SPI Emulation Register (SPIEMU) [offset = 44h] 31 16 Reserved R-8000h 15 0 EMU_RXDATA R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-26. SPI Emulation Register (SPIEMU) Field Descriptions Bit Field 31-16 Reserved 15-0 EMU_RXDATA Value Description 8000h Reserved 0-FFFFh SPI receive data. The SPI emulation register is a mirror of the SPIBUF register.
Control Registers www.ti.com Table 27-27. SPI Delay Register (SPIDELAY) Field Descriptions (continued) Bit 23-16 Field Value Description T2CDELAY 0-1FFh Transmit-end-to-chip-select-inactive-delay. See Figure 27-52 for an example. T2CDELAY is used only in master mode. It defines a hold time for the slave device that delays the chip select deactivation by a multiple of VCLK cycles after the last bit is transferred.
Control Registers www.ti.com Figure 27-51. Example: t = 8 VCLK Cycles C2TDELAY SCS CLK SOMI VCLK tC2TDELAY Figure 27-52. Example: t = 4 VCLK Cycles T2CDELAY SCS CLK SOMI VCLK tT2CDELAY Figure 27-53. Transmit-Data-Finished-to-ENA-Inactive-Timeout SCS ENA CLK SOMI t 1 Figure 27-54.
Control Registers www.ti.com 27.3.20 SPI Default Chip Select Register (SPIDEF) Figure 27-55. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch] 31 16 Reserved R-0 15 8 7 0 Reserved CSDEF R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-28. SPI Default Chip Select Register (SPIDEF) Field Descriptions Bit Field 31-8 Reserved 7-0 CDEF Value 0 Description Read returns 0. Writes have no effect. Chip select default pattern. Master-mode only.
Control Registers www.ti.com 27.3.21 SPI Data Format Registers (SPIFMT[3:0]) Figure 27-56.
Control Registers www.ti.com Table 27-29. SPI Data Format Registers (SPIFMTn) Field Descriptions (continued) Bit Field 19 HDUPLEX_ENAx Value Description Half Duplex transfer mode enable for Data Format x. This bit controls the I/O function of SOMI/SIMO lines for a specific requirement where in the case of Master mode, TX pin SIMO will act as an RX pin, and in the case of Slave mode, RX pin - SIMO will act as a TX pin.. 0 Normal Full Duplex transfer.
Control Registers www.ti.com 27.3.22 Interrupt Vector 0 (INTVECT0) NOTE: The TG interrupt is not available in MibSPI in compatibility mode. Therefore, there is no possibility to access this register in compatibility mode. Figure 27-57. Interrupt Vector 0 (NTVECT0) [offset = 60h] 31 16 Reserved R-0 15 6 5 1 0 Reserved INTVECT0 SUSPEND0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-30.
Control Registers www.ti.com NOTE: In multi-buffer mode, INTVECT0 contains the interrupt for the highest priority transfer group. A read from INTVECT0 automatically causes the next-highest priority transfer group's interrupt status to get loaded into INTVECT0 and its corresponding SUSPEND flag to get loaded into SUSPEND0. The transfer group with the lowest number has the highest priority, and the transfer group with the highest number has the lowest priority.
Control Registers www.ti.com NOTE: Reading from the INTVECT1 register when "Transmit Empty" is indicated does not clear the TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx register clears the "Transmit Empty" interrupt. NOTE: In multi-buffer mode, INTVECT1 contains the interrupt for the highest priority transfer group.
Control Registers www.ti.com Table 27-32. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions Bit 31-30 29 28-26 Field Reserved Value 0 MODCLKPOL3 23-22 21 0 Normal SPICLK in all the modes. 1 Polarity of the SPICLK will be inverted if Modulo mode is selected. MMODE3 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if modulo option is supported by the module).
Control Registers www.ti.com Table 27-32. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions (continued) Bit 12-10 Field Value MMODE1 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if modulo option is supported by the module).
Control Registers www.ti.com NOTE: Accessibility of Registers Registers from this offset address onwards are not accessible in SPI compatibility mode. They are accessible only in the multi-buffer mode. 27.3.25 Multi-buffer Mode Enable Register (MIBSPIE) NOTE: Accessibility of Multi-Buffer RAM The multi-buffer RAM is not accessible unless the MSPIENA bit set to 1.
Control Registers www.ti.com 27.3.26 TG Interrupt Enable Set Register (TGITENST) The register TGITENST contains the TG interrupt enable flags for transfer-finished and for transfersuspended events. Each of the enable bits in the higher half-word and the lower half-word of TGITENST belongs to one TG. The register map shown in Figure 27-61 and Table 27-34 represents a super-set device with the maximum number of TGs (16) assumed. The actual number of bits available varies per device. Figure 27-61.
Control Registers www.ti.com 27.3.27 TG Interrupt Enable Clear Register (TGITENCR) The register TGITENCR is used to clear the interrupt enables for the TG-completed interrupt and the TGsuspended interrupts. The register map shown in Figure 27-62 and Table 27-35 represents a super-set device with the maximum number of TGs (16) assumed. The actual number of bits available varies per device. Figure 27-62.
Control Registers www.ti.com 27.3.28 Transfer Group Interrupt Level Set Register (TGITLVST) The register TGITLVST sets the level of interrupts for transfer completed interrupt and for transfer suspended interrupt to level 1. The register map shown in Figure 27-63 andTable 27-36 represents a super-set device with the maximum number of TGs (16) assumed. The actual number of bits available varies per device. Figure 27-63.
Control Registers www.ti.com 27.3.29 Transfer Group Interrupt Level Clear Register (TGITLVCR) The register TGITLVCR clears the level of interrupts for transfer completed interrupt and for transfer suspended interrupt to level 0. The register map shown in Figure 27-64 and Table 27-37 represents a super-set device with the maximum number of TGs (16) assumed. The actual number of bits available varies per device. Figure 27-64.
Control Registers www.ti.com 27.3.30 Transfer Group Interrupt Flag Register (TGINTFLAG) The TGINTFLAG register comprises the transfer group interrupt flags for transfer-completed interrupts (INTFLGRDYx) and for transfer-suspended interrupts (INTFLGSUSx). Each of the interrupt flags in the higher half-word and the lower half-word of TGINTFLAG belongs to one TG. The register map shown in Figure 27-65 and Table 27-38 represents a super-set device with the maximum number of TGs (16) assumed.
Control Registers www.ti.com 27.3.31 Tick Count Register (TICKCNT) One of the trigger sources for TGs is an internal periodic time trigger. This time trigger is called a tick counter and is basically a down-counter with a preload/reload value. Every time the tick counter detects an underflow it reloads the initial value and toggles the trigger signal provided to the TGs.
Control Registers www.ti.com 27.3.32 Last TG End Pointer (LTGPEND) Figure 27-68. Last TG End Pointer (LTGPEND) [offset = 94h] 31 15 29 28 24 23 16 Reserved TG IN SERVICE Reserved R-0 R-0 R-0 14 8 7 0 Rsvd LPEND Reserved R-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-40. Last TG End Pointer (LTGPEND) Field Descriptions Bit Field 31-29 Reserved 28-24 TG IN SERVICE Value 0 Description Reads returns 0. Writes have no effect.
Control Registers www.ti.com 27.3.33 TGx Control Registers (TGxCTRL) Each TG can be configured via one dedicated control register. The register description below shows one control register(x) which is identical for all TGs. For example, the control register for TG 2 is named TG2CTRL and is located at base address + 98h + 4 × 2. The actual number of available control registers varies by device. Figure 27-69.
Control Registers www.ti.com Table 27-41. TG Control Registers (TGxCTRL) Field Descriptions (continued) Bit Field 23-20 Value TRIGEVTx Description Type of trigger event. A level-triggered TG can be stopped by de-activating the level trigger. However, the following restrictions apply. • Deactivating the level trigger for a TG during a NOBRK transfer does not stop the transfers until all of the ICOUNT number of buffers are transferred for the NOBRK buffer.
Control Registers www.ti.com Table 27-41. TG Control Registers (TGxCTRL) Field Descriptions (continued) Bit 19-16 Field Value TRIGSRCx Description Trigger source. After reset, the trigger sources of all TGs are disabled. 0 Disabled 1h EXT0 External trigger source 0. The actual source varies per device (for example, HET I/O channel, event pin). 2h EXT1 External trigger source 1. The actual source varies per device (for example, HET I/O channel, event pin). 3h EXT2 External trigger source 2.
Control Registers www.ti.com 27.3.34 DMA Channel Control Register (DMAxCTRL) Each DMA channel can be configured via one dedicated control register. The register description below shows one exemplary control register that is identical for all DMA channels; for example, the control register for DMA channel 0 is named DMA0CTRL. The MibSPI supports up to 8 bidirectional DMA channels. The number of bidirectional DMA channels varies by device.
Control Registers www.ti.com Table 27-42. DMA Channel Control Register (DMAxCTRL) Field Descriptions (continued) Bit Field 14 TXDAMENAx 13 Value Description Transmit data DMA channel enable. 0 No DMA request upon new transmit data. 1 The physical DMA channel for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data.
Control Registers www.ti.com 27.3.35 DMAxCOUNT Register (ICOUNT) NOTE: These registers are used only if the LARGE COUNT bit in the DMACNTLEN register is set. The number of bidirectional DMA channels varies by device. The number of DMA channels and hence the number of DMA registers varies by device. Figure 27-71. DMAxCOUNT Register (ICOUNT) [offset = F8h-114h] 31 16 ICOUNTx R/W-0 15 0 COUNTx R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27-43.
Control Registers www.ti.com 27.3.36 DMA Large Count (DMACNTLEN) Figure 27-72. DMA Large Count Register (DMACNTLEN) [offset = 118h] 31 16 Reserved R-0 15 1 0 Reserved LARGE COUNT R-0 R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 27-44. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions Bit 31-1 0 Field Reserved Value 0 LARGE COUNT SPNU562 – May 2014 Submit Documentation Feedback Description Read returns 0.
Control Registers www.ti.com 27.3.37 Parity/ECC Control Register (PAR_ECC_CTRL) Figure 27-73. Parity/ECC Control Register (PAR_ECC_CTRL) [offset = 120] 31 28 27 24 23 20 19 16 Reserved SBE_EVT_EN Reserved EDAC_MODE R-0 R/W-5h R-0 R/WP-Ah 15 9 8 7 4 3 0 Reserved PTESTEN Reserved EDEN R-0 R/WP-0 R-0 R/W-5h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset Table 27-45.
Control Registers www.ti.com 27.3.38 Parity/ECC Status Register (PAR_ECC_STAT) Figure 27-74. Parity/ECC Status Register (PAR_ECC_STAT) [offset = 124] 31 16 Reserved R-0 15 10 9 8 Reserved SBE_FLG1 SBE_FLG0 R-0 R/W1C-0 R/W1C-0 7 1 0 Reserved 2 UERR_ FLG1 UERR_ FLG0 R-0 R/W1C-0 R/W1C-0 LEGEND: R/W = Read/Write; R = Read only; W1C = Clear type flag; -n = value after reset Table 27-46.
Control Registers www.ti.com 27.3.39 Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1) Figure 27-75. Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1) [offset = 128h] 31 16 Reserved R-0 15 11 10 0 Reserved UERRADDR1 R-0 RC-x LEGEND: R/W = Read/Write; R = Read only; RC = Read to clear; -n = value after reset Table 27-47.
Control Registers www.ti.com Table 27-48. Effect of BIG_ENDIAN Port on UERRADDR1[1:0] Bits Endianness UERRADDR1[1:0] Fault Location is Among the RAM Bits 1 (Big Endian) 0 (Little Endian) 00 11 01 10 15:8 10 01 23:16 11 00 31:24 7:0 NOTE: When ECC is supported, UERRADDR0 will indicate only word address. UERRADDR0[1:0] will always be 00.
Control Registers www.ti.com 27.3.40 Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) Figure 27-76. Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) [offset = 12Ch] 31 16 Reserved R-0 15 11 10 0 Reserved UERRADDR0 R-0 RC-x LEGEND: R/W = Read/Write; R = Read only; RC = Read to clear; -n = value after reset Table 27-49.
Control Registers www.ti.com Table 27-50. Effect of BIG_ENDIAN Port on UERRADDR0[1:0] Bits Endianness Fault Location is Among the RAM Bits 1 (Big Endian) 0 (Little Endian) 00 11 01 10 15:8 10 01 23:16 11 00 31:24 UERRADDR0[1:0] 7:0 NOTE: When ECC is supported, UERRADDR0 will indicate only word address. UERRADDR0[1:0] will always be 00. 27.3.
Control Registers www.ti.com 27.3.42 I/O-Loopback Test Control Register (IOLPBKTSTCR) This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog. In addition, it contains control bits to induce error conditions into the module. These are to be used only for module testing. All of the control/status bits in this register are valid only when the IOLPBKTSTENA field is set to Ah. Figure 27-78.
Control Registers www.ti.com Table 27-52. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions (continued) Bit Field 16 CTRL DLENERR Value Description Controls inducing of the data length error during I/O loopback test mode. 0 Do not cause a data-length error. 1 Induce a data-length error. Master mode: The SPIENA pin (if functional) is forced to 1 when the module starts shifting data.
Control Registers www.ti.com 27.3.43 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This is an extension of SPIFMT0 and SPIFMT1 registers. For example, EPRESCALE_FMT1(7:0) of EXTENDED_PRESCALE1 and PRESCALE1(7:0) of SPIFMT1 register will always reflect the same contents.
Control Registers www.ti.com Table 27-53. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions (continued) Bit 10-0 Field Value Description EPRESCALE_FMT0 0-7FFh EPRESCALE_FMT0. Extended Prescale value for SPIFMT0. EPRESCALE_FMT0 determines the bit transfer rate of data format 0 if the SPI/MibSPI is the network master. EPRESCALE_FMT0 is use to derive SPICLK from VCLK. If the SPI is configured as slave, EPRESCALE_FMT0 does not need to be configured.
Control Registers www.ti.com 27.3.44 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This is an extension of SPIFMT2 and SPIFMT3 registers. For example, EPRESCALE_FMT3(7:0) of EXTENDED_PRESCALE2 and PRESCALE3(7:0) of SPIFMT3 register will always reflect the same contents.
Control Registers www.ti.com Table 27-54. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions (continued) Bit 10-0 Field Value Description EPRESCALE_FMT2 0-7FFh EPRESCALE_FMT2. Extended Prescale value for SPIFMT2. EPRESCALE_FMT0 determines the bit transfer rate of data format 2 if the SPI/MibSPI is the network master. EPRESCALE_FMT2 is use to derive SPICLK from VCLK. If the SPI is configured as slave, EPRESCALE_FMT2 does not need to be configured.
Control Registers www.ti.com 27.3.46 ECC Diagnostic Status Register (ECCDIAG_STAT) NOTE: ECCDIAG_STAT Validity Both SEFLG[1:0] and DEFLG[1:0] are valid only during Diagnostic Mode (when ECCDIAG_EN = 5h). This status register should be write-cleared after coming out of Diagnostic Mode. Figure 27-82.
Control Registers www.ti.com 27.3.47 Single Bit Error Address Register - RXRAM (SBERRADDR1) Figure 27-83. Single Bit Error Address Register - RXRAM (SBERRADDR1) [offset = 148h] 31 16 Reserved R-0 15 11 10 0 Reserved SBERRADDR1 R-0 RC-0 LEGEND: R = Read only; RC = Read to clear; -n = value after reset Table 27-57. Single Bit Error Address Register - RXRAM (SBERRADDR1) Field Descriptions Bit Field Value 31-11 Reserved 10-0 SBERRADDR1 0 Description Read returns 0. Writes have no effect.
Control Registers www.ti.com 27.3.48 Single Bit Error Address Register - TXRAM (SBERRADDR0) Figure 27-84. Single Bit Error Address Register - TXRAM (SBERRADDR0) [offset = 14Ch] 31 16 Reserved R-0 15 11 10 0 Reserved SBERRADDR0 R-0 RC-0 LEGEND: R = Read only; RC = Read to clear; -n = value after reset Table 27-58. Single Bit Error Address Register - TXRAM (SBERRADDR0) Field Descriptions Bit Field Value 31-11 Reserved 10-0 SBERRADDR0 0 Description Read returns 0. Writes have no effect.
Multi-buffer RAM www.ti.com 27.4 Multi-buffer RAM The multi-buffer RAM comprises of all buffers, which can be configured identically. The multi-buffer RAM contains two banks of up to128/256 words of 32 bits for a maximum configuration, one each for TXRAM (replicating the SPIDAT1 register) and RXRAM (replicating the SPIBUF register). The buffers can be partitioned into multiple transfer groups, each containing a variable number of buffers.
Multi-buffer RAM www.ti.com NOTE: Refer to the specific device datasheet for the actual number of transmit and receive buffers. Write to unimplemented buffer is overwriting the corresponding implemented buffer. In MIBSPI, if the RAM SIZE specified is 32 buffers, write to 33rd buffer overwrites 1st buffer, write to 34th buffer overwrites 2nd buffer, and so on. 27.4.1 Multi-buffer RAM Auto Initialization When the MIBSPI is out of reset mode, auto initialization of multi-buffer RAM starts.
Multi-buffer RAM www.ti.com 27.4.3 Multi-buffer RAM Transmit Data Register Each word of TXRAM is a transmit-buffer register. Figure 27-87. Multi-buffer RAM Transmit Data Register [offset = Base + 000-1FFh] 31 29 28 27 26 25 24 23 16 BUFMODE CSHOLD LOCK WDEL DFSEL CSNR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 0 TXDATA R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 27-60.
Multi-buffer RAM www.ti.com Table 27-60. Multi-buffer RAM Transmit Data Register Field Descriptions (continued) Bit Field 26 WDEL Value Description Enable the delay counter at the end of the current transaction. Note: The WDEL bit is supported in master mode only. In slave mode, this bit will be ignored. 0 No delay will be inserted. However, SPISCS pins will still be de-activated for at least for 2VCLK cycles if CSHOLD = 0.
Multi-buffer RAM www.ti.com 27.4.4 Multi-buffer RAM Receive Buffer Register Each word of RXRAM is a receive-buffer register. Figure 27-88. Multi-buffer RAM Receive Buffer Register [offset = RAM Base + 200-3FFh] 31 30 29 28 27 26 25 24 RXEMPTY RXOVR TXFULL BITERR DESYNC PARITYERR TIMEOUT DLENERR RS-1 RC-0 R-0 RC-0 RC-0 RC-0 RC-0 RC-0 23 16 LCSNR R-0 15 0 RXDATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; C = Clear; S = Set; -n = value after reset Table 27-61.
Multi-buffer RAM www.ti.com Table 27-61. Multi-buffer Receive Buffer Register Field Descriptions (continued) Bit Field 28 BITERR Value Description Bit error.There was a mismatch of internal transmit data and transmitted data. 0 No bit error occured. Note: This flag is cleared to 0 when the RXDATA portion of the SPIBUF register is read. 1 27 DESYNC A bit error occurred.
Parity\ECC Memory www.ti.com 27.5 Parity\ECC Memory Parity/ECC portion of multi-buffer RAM is not accessible by the CPU during normal operating modes. However each read or write operation to the Control/Data/Status portion of the multi-buffer RAM causes reads/writes to the parity/ECC portion as well. • Each write to the multi-buffer RAM (either from the VBUS interface or by the MibSPI itself) causes a write operation to the Parity/ECC portion of RAM simultaneously to update the equivalent parity/ECC bits.
Parity\ECC Memory www.ti.com Figure 27-89. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is Disabled or the Feature is Not Implemented Address BASE+0x000h 0 31 Parity/ECC0 TXBUF0 Parity/ECC1 TXBUF1 Parity/ECC126 TXBUF126 Parity/ECC127 TXBUF127 Parity/ECC0 RXBUF0 Parity/ECC1 RXBUF1 TXParity/ECC0 TXParity/ECC1 . . . TXParity/ECC126 BASE+0x5FFh TXParity/ECC127 BASE+0x600h RXParity/ECC0 RXParity/ECC1 . . . . .
Parity\ECC Memory www.ti.com Figure 27-90. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is Enabled Address 0 31 BASE+0x000h Parity/ECC0 TXBUF0 Parity/ECC1 TXBUF1 Parity/ECC254 TXBUF254 Parity/ECC255 TXBUF255 Parity/ECC0 RXBUF0 Parity/ECC1 RXBUF1 . . BASE+0x7FFh 0 31 TXParity/ECC0 TXParity/ECC1 . . . TXParity/ECC254 BASE+0xBFFh TXParity/ECC255 BASE+0xC00h RXParity/ECC0 0 31 BASE+0x400h BASE+0x800h . . . . .
Parity\ECC Memory www.ti.com 27.5.1 Example of Parity Memory Organization Suppose TXBUF5 (6th location in TXRAM) in the multi-buffer RAM is written with a value of A001_AA55. If the polarity of the parity is set to odd, the corresponding parity location parity5 will get updated with equivalent parity of 1011 in its field. During parity-memory test mode, these bits can be individually byte addressed. The return data will be a byte adjusted with actual parity bit in the LSB of the byte.
Parity\ECC Memory www.ti.com 27.5.2 Example of ECC Memory Organization Suppose TXBUF5 (6th location in TXRAM portion) in the multi-buffer RAM is written with a value of A001_AA55, then the corresponding ECC-bits will be updated in ECC location. The ECC bits can be accessed by user, when Memory Test mode is enabled and additionally diagnostic mode is also enabled. The actual ECC bits will be aligned as shown in Figure 27-92. Figure 27-92.
MibSPI Pin Timing Parameters 27.6 www.ti.com MibSPI Pin Timing Parameters The pin timings of SPI can be classified based on its mode of operation. In each mode, different configurations like Phase & Polarity affect the pin timings. The pin directions are based on the mode of operation.
MibSPI Pin Timing Parameters www.ti.com Figure 27-95. SPI/MibSPI Pins During Master Mode in 4-Pin with SPIENA Configuration VCLK Write to SPIDAT SPIENA SPICLK SPISIMO SPISOMI * De-activation of SPIENA pin is controlled by the Slave. * Dotted vertical lines indicate the receive edges Figure 27-96.
MibSPI Pin Timing Parameters www.ti.com 27.6.2 Slave Mode Timings for SPI/MibSPI Figure 27-97. SPI/MibSPI Pins During Slave Mode 3-Pin Configuration Write to SPIDAT VCLK SPICLK SPISOMI SPISIMO * Dotted vertical lines indicate the receive edges Figure 27-98. SPI/MibSPI Pins During Slave Mode in 4-Pin with SPIENA Configuration Write to SPIDAT SPIENA VCLK SPICLK * Diagram shows a relationship between the SPIENA from Slave and SPICLK from Master Figure 27-99.
MibSPI Pin Timing Parameters www.ti.com 27.6.3 Master Mode Timing Parameter Details In case of Master, the module drives out SPICLK. It also drives out the Transmit data on SPISIMO with respect to its internal SPICLK. In case of Master mode, the RX data on SPISOMI pin is registered with respect to SPICLK recieved through Input buffer from the I/O pad. If Chip Select pin is functional, then Master will drive out SPISCS pin(s) before starting the SPICLK.
Chapter 28 SPNU562 – May 2014 Serial Communication Interface (SCI)/Local Interconnect Network (LIN) Module This chapter describes the serial communication interface (SCI) / local interconnect network (LIN) module. The SCI/LIN is compliant to the LIN 2.1 protocol specified in the LIN Specification Package. This module can be configured to operate in either SCI (UART) or LIN mode.
Introduction and Features www.ti.com 28.1 Introduction and Features The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility. The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a Kline.
Introduction and Features www.ti.com 28.1.2 LIN Features The following are the features of the LIN module: • Compatibility with LIN 1.3, 2.0, and 2.1protocols • Configurable Baud Rate up to 20 Kbits/s • Two external pins: LINRX and LINTX.
Introduction and Features www.ti.com 28.1.3 Block Diagram The SCI/LIN module contains core SCI block with added sub-blocks to support LIN protocol. Three Major components of the SCI Module are: • Transmitter • Baud Clock Generator • Receiver Transmitter (TX) contains two major registers to perform the double- buffering: • The transmitter data buffer register (SCITD) contains data loaded by the CPU to be transferred to the shift register for transmission.
Introduction and Features www.ti.com Figure 28-1. SCI Block Diagram TRANSMITTER Address bit† SCITXSHF Shift register LINTX TX EMPTY SCIFLR.11 1 TXWAKE SCIFLR.10 VCLK Peripheral 8 TXRDY SCIFLR.8 Transmit buffer SCITD Baud clock generator TX INT ENA SCISETINT.8 TX INT TXENA SCIGCR1.25 CLOCK SCIGCR1.5 SCI Baud rate registers SCIBAUD RECEIVER SCIRXSHF Shift register BRKDT SCIFLR.0 RXENA SCIGCR1.24 8 RXWAKE SCIFLR.12 1346 Receive buffer SCIRD WAKEUP SCIFLR.1 BRKDT INT ENA SCISETINT.
Introduction and Features www.ti.com Figure 28-2.
SCI www.ti.com 28.2 SCI 28.2.1 SCI Communication Formats The SCI module can be configured to meet the requirements of many applications. Because communication formats vary depending on the specific application, many attributes of the SCI/LIN are user configurable. The list below describes these configuration options: • SCI Frame format • SCI Timing modes • SCI Baud rate • SCI Multiprocessor modes 28.2.1.1 SCI Frame Formats The SCI uses a programmable frame format.
SCI www.ti.com 28.2.1.2 SCI Timing Mode The SCI can be configured to use asynchronous or isosynchronous timing using TIMING MODE bit in SCIGCR1 register. 28.2.1.2.1 Asynchronous Timing Mode The asynchronous timing mode uses only the receive and transmit data lines to interface with devices using the standard universal asynchronous receiver- transmitter (UART) protocol. In the asynchronous timing mode, each bit in a frame has a duration of 16 SCI baud clock periods.
SCI www.ti.com In asynchronous timing mode, the SCI generates a baud clock according to the following formula: VCLK Frequency SCICLK Frequency = ---------------------------------------------------M P + 1 + -----16 Asynchronous baud value = SCICLK Frequency ---------------------------------------------------------16 For P = 0, VCLK Frequency ------------------------------------------------32 Asynchronous baud value = (40) 28.2.1.3.
SCI www.ti.com Table 28-2.
SCI www.ti.com 28.2.1.4 SCI Multiprocessor Communication Modes In some applications, the SCI may be connected to more than one serial communication device. In such a multiprocessor configuration, several frames of data may be sent to all connected devices or to an individual device. In the case of data sent to an individual device, the receiving devices must determine when they are being addressed. When a message is not intended for them, the devices can ignore the following data.
SCI www.ti.com Figure 28-6. Idle-Line Multiprocessor Communication Format Blocks of frames Blocks separated by 10 or more idle bits Data format (pins LINRX, LINTX) Address frame Data Fewer than 10 idle bits Data frame Parity Stop Start Parity Stop Address Start Start Idle period Parity Stop One block of frames Data format expanded Last data Data frame 28.2.1.4.
SCI www.ti.com 28.2.1.5 SCI Multi Buffered Mode To reduce CPU load when Receiving or Transmitting data in interrupt mode or DMA mode, the SCI/LIN module has eight separate Receive and transmit buffers. Multi buffered mode is enabled by setting the MBUF MODE bit. The multi-buffer 3-bit counter counts the data bytes transferred from the SCIRXSHF register to the RDy receive buffers and TDy transmit buffers register to SCITXSHF register.
SCI www.ti.com Figure 28-9.
SCI www.ti.com 28.2.2 SCI Interrupts The SCI/LIN module has two interrupt lines, level 0 and level 1, to the vectored interrupt manager (VIM) module (see Figure 28-10). Two offset registers SCIINTVECT0 and SCIINTVECT1 determine which flag triggered the interrupt according to the respective priority encoders. Each interrupt condition has a bit to enable/disable the interrupt in the SCISETINT and SCICLRINT registers respectively.
SCI www.ti.com Figure 28-11. Interrupt Generation for Given Flags 5-bit INTVECT0 Priority Encoder 0 ... ... INT0 INTx LVL FLAGx ENA INT x ... INT1 ... Priority Encoder 1 5-bit INTVECT1 28.2.2.1 Transmit Interrupt To use transmit interrupt functionality, SET TX INT bit must be enabled and SET TX DMA bit must be cleared. The transmit ready (TXRDY) flag is set when the SCI transfers the contents of SCITD to the shift register, SCITXSHF.
SCI www.ti.com 28.2.2.4 Error Interrupts The following error detection are supported with Interrupt by the SCI module: • Parity errors (PE) • Frame errors (FE) • Break Detect errors (BRKDT) • Overrun errors (OE) • Bit errors (BE) If all of these errors (PE, FE, BRKDT, OE, BE) are flagged, an interrupt for the flagged errors will be generated if enabled. A message is valid for both the transmitter and the receiver if there is no error detected until the end of the frame.
SCI www.ti.com 28.2.3 SCI DMA Interface DMA requests for receive (RXDMA request) and transmit (TXDMA request) are available for the SCI/LIN module. The DMA transfers depending on whether multi-buffer mode bit (MBUF MODE) is enabled or not. For DMA module configuration refer 28.2.3.1 Receive DMA Requests This DMA functionality is enabled/disabled by the CPU using the SET RX DMA/CLR RX DMA bits, respectively.
SCI www.ti.com 28.2.4 SCI Configurations Before the SCI sends or receives data, its registers should be properly configured. Upon power-up or a system-level reset, each bit in the SCI registers is set to a default state. The registers are writable only after the RESET bit is set to 1. Of particular importance is the SWnRST bit. This active-low bit is initialized to 0 and keeps the SCI in a reset state until it is programmed to 1.
SCI www.ti.com 28.2.4.1.2 Receiving Data in Multi-Buffer Mode Multi-Buffer Mode is selected when MBUF MODE bit is 1. In this mode SCI sets the RXRDY bit when programmed number of data are received in the receive buffer, the complete frame. The error condition detection logic is same as Single Buffer Mode, except that it monitors for the complete frame. Like Single Buffer Mode, you can use either Interrupt, DMA or polling method to read the data.
SCI www.ti.com 28.2.5 SCI Low Power Mode The SCI/LIN can be put in either local or global low-power mode. Global low-power mode is asserted by the system and is not controlled by the SCI/LIN. During global low-power mode, all clocks to the SCI/LIN are turned off so the module is completely inactive. Local low-power mode is asserted by setting the POWERDOWN bit; setting this bit stops the clocks to the SCI/LIN internal logic and the module registers.
LIN www.ti.com Following is a sequence of events typical of sleep mode operation: • The SCI is configured and both sleep mode and receive actions are enabled. • An address frame is received and a receive interrupt is generated. • Software compares the received address frame against that set by software and determines that the SCI is not being addressed, so the value of the SLEEP bit is not changed.
LIN www.ti.com The Master Mode of LIN module is compatible with LIN 2.1 standard. 28.3.1.2 Message Frame The LIN protocol defines a message frame format, illustrated in Figure 28-12. Each frame includes one master header, one response, one in-frame response space, and inter-byte spaces. In-frame-response and inter-byte spaces may be 0. Figure 28-12.
LIN www.ti.com 28.3.1.2.2 Response The format of the response is as illustrated in Figure 28-14. There are two types of fields in a response: data and checksum. The data field consists of exactly one data byte, one start bit, and one stop bit, for a total of 10 bits. The LSB is transmitted first. The checksum field consists of one checksum byte, one start bit and one stop bit. The checksum byte is the inverted modulo-256 sum over all data bytes in the data fields of the response. Figure 28-14.
LIN www.ti.com 28.3.1.3 Synchronizer The synchronizer has three major functions in the messaging between master and slave nodes. It generates the master header data stream, it synchronizes to the LIN bus for responding, and it locally detects timeouts. A bit rate is programmed using the prescalers in the BRSR register to match the indicated LIN_speed value in the LIN description file.
LIN www.ti.com 28.3.1.4.2 Superfractional Divider The superfractional divider scheme applies to the following modes: • LIN master mode (synch field + identifier field + response field + checksum field) • LIN slave mode (response field + checksum field) 28.3.1.4.3 Superfractional Divider In LIN Mode Building on the 4-bit fractional divider M (BRSR[27:24], the superfractional divider uses an additional 3-bit modulating value, illustrated in Table 28-7.
LIN www.ti.com 28.3.1.5 Header Generation Automatic generation of the LIN protocol header data stream is supported without CPU interaction. The CPU pr the DMA will trigger a message header generation and the LIN state machine will handle the generation itself. A master node initiates header generation on CPU or DMA writes to the IDBYTE in the LINID register.
LIN www.ti.com NOTE: If the BLIN module, configured as Slave in multi-buffer mode, is in the process of transmitting data while a new header comes in, the module might end up in responding with the data from the previous interrupted response (not the data corresponding to the new ID). To avoid this scenario the following procedure could be used: 1. Check for the Bit Error (BE) during the response transmission.
LIN www.ti.com 28.3.1.5.2 Header Reception and Adaptive Baud Rate A slave node baud rate can optionally be adjusted to the detected bit rate as an option to the LIN module. The adaptive baud rate option is enabled by setting the ADAPT bit. During header reception, a slave measures the baud rate during detection of the synch field. If ADAPT bit is set, then the measured baud rate is compared to the slave node’s programmed baud rate and adjusted to the LIN bus baud rate if necessary.
LIN www.ti.com Figure 28-18.
LIN www.ti.com NOTE: When an inconsistent synch field (ISFE) error occurs, suggested action for the application is to Reset the SWnRST bit and set the SWnRST bit to make sure that the internal state machines are back to their normal states 28.3.1.6 Extended Frames Handling The LIN protocol 2.0 and prior includes two extended frames with identifiers 62 (user-defined) and 63 (reserved extended). The response data length of the user-defined frame (ID 62, or 0x3E) is unlimited.
LIN www.ti.com Figure 28-20. Checksum Compare and Send for Extended Frames Compare Checksum 7 SCIRXSHF 0 RX 0 TX CHECKSUM CALCULATOR Send Checksum 7 SCITXSHF 28.3.1.7 Timeout Control Any LIN node listening to the bus and expecting a response initiated from a master node could flag a noresponse error timeout event. The LIN protocol defines four types of timeout events, which are all handled by the hardware of the LIN module.
LIN www.ti.com Table 28-8. Timeout Values in Tbit Units N TDATA_FIELD TFRAME_MIN TFRAME_MAX 1 10 54 76 2 20 64 90 3 30 74 104 4 40 84 118 5 50 94 132 6 60 104 146 7 70 114 160 8 80 124 174 28.3.1.7.2 Bus Idle Detection The second type of timeout can occur when a node detects an inactive LIN bus: no transitions between recessive and dominant values are detected on the bus.
LIN www.ti.com 28.3.1.8.1 Bit Errors A bit error (BE) is detected at the bit time when the bit value that is monitored is different from the bit value that is sent. A bit error is indicated by the BE flag in SCIFLR. After signaling a BE, the transmission is aborted no later than the next byte. The bit monitor ensures that the transmitted bit in LINTX is the correct value on the LIN bus by reading back on the LINRX pin as shown in Figure 28-21.
LIN www.ti.com 28.3.1.8.4 Checksum Errors A checksum error (CE) is detected and flagged at the receiving end if the calculated modulo-256 sum over all received data bytes (including the ID byte if it is the enhanced checksum type) plus the checksum byte does not result in 0xFF. The modulo-256 sum is calculated over each byte by adding with carry, where the carry bit of each addition is added to the LSB of its resulting sum.
LIN www.ti.com 28.3.1.9 Message Filtering and Validation Message filtering uses the entire identifier to determine which nodes will participate in a response, either receiving or transmitting a response. Therefore, two acceptance masks are used as shown in Figure 2824. During header reception, all nodes filter the ID-Field (ID-Field is the part of the header explained in Figure 28-16) to determine whether they transmit a response or receive a response for the current message.
LIN www.ti.com Figure 28-24.
LIN www.ti.com 28.3.1.10 Receive Buffers To reduce CPU load when receiving a LIN N-byte (with N = 1–8) response in interrupt mode or DMA mode, the SCI/LIN module has eight receive buffers. These buffers can store an entire LIN response in the RDy receive buffers. Figure 28-8 illustrates the receive buffers. The checksum byte following the data bytes is validated by the internal checksum calculator.
LIN www.ti.com 28.3.2 LIN Interrupts LIN and SCI mode have a common Interrupt block as explained in Section 28.2.2. There are 16 interrupt sources in the SCI/LIN module, with 8 of them being LIN mode only, as seen in Table 28-4. A LIN message frame indicating the timing and sequence of the LIN interrupts that could occur is shown in Figure 28-25. Figure 28-25.
LIN www.ti.com 28.3.4 LIN Configurations The following list details the configuration steps that software should perform prior to the transmission or reception of data in LIN mode. As long as SWnRST is held low the entire time that the LIN is being configured, the order in which the registers are programmed is not important. • Enable LIN by setting RESET bit. • Clear SWnRST to 0 before configuring the LIN. • Configure the LINRX and LINTX pins as SCI functional by setting the RX FUNC and TX FUNC bit.
LIN www.ti.com 28.3.4.1.2 Receiving Data in Multi-Buffer Mode Multi-Buffer Mode is selected when MBUF MODE bit is 1. In this mode SCI/LIN sets the RXRDY bit after receiving the programmed number of data in the receive buffer and the checksum field, the complete frame. The error condition detection logic is same as Single Buffer mode, except that it monitors for the complete frame. Like Single Buffer mode, you can use either Interrupt, DMA or polling method to read the data.
Low-Power Mode www.ti.com 28.4 Low-Power Mode The SCI/LIN module can be put in either local or global low-power mode. Global low-power mode is asserted by the system and is not controlled by the SCI/LIN module. During global low-power mode, all clocks to the SCI/LIN are turned off so the module is completely inactive.
Low-Power Mode www.ti.com 28.4.2 Wakeup The wakeup interrupt is used to allow the SCI/LIN module to automatically exit low-power mode. A SCI/LIN wakeup is triggered when a low level is detected on the receive RX pin, and this clears the POWERDOWN bit. NOTE: If the wakeup interrupt is disabled then the SCI/LIN enters low-power mode whenever it is requested to do so, but a low level on the receive RX pin does NOT cause the SCI/LIN to exit low-power mode.
Low-Power Mode www.ti.com 28.4.3 Wakeup Timeouts The LIN protocol defines the following timeouts for a wakeup sequence. After a wakeup signal has been sent to the bus, all nodes wait for the master to send a header. If no synch field is detected before 150 ms (3,000 cycles at 20 kHz) after wakeup signal is transmitted, a new wakeup is sent by the same node that requested the first wakeup. This sequence is not repeated more than two times.
GPIO Functionality www.ti.com 28.6 GPIO Functionality The following section applies to all device pins that can be configured as functional or general-purpose I/O pins. 28.6.1 GPIO Functionality Figure 28-27 illustrates the GPIO functionality. Figure 28-27. GPIO Functionality Output enable Data out Device pin Data in Input enable Pull control disable Pull control logic Pull select Output enable Data out Device pin Data in Input enable Pull control logic Pull control disable 28.6.
GPIO Functionality www.ti.com 28.6.3 Out of Reset The following apply if the device is out of reset: • Pull control. The pull control is enabled by clearing the PD (pull control disable) bit in the SCIPIO7 register (Section 28.7.21). In this case, if the PSL (pull select) bit in the SCIPIO8 register (Section 28.7.22) is set, the pin will have a pull-up. If the PSL bit is cleared, the pin will have a pulldown. If the PD bit is set in the control register, there is no pull-up or pull-down on the pin.
SCI/LIN Control Registers www.ti.com 28.7 SCI/LIN Control Registers The SCI/LIN module registers are based on the SCI registers, with added functionality registers enabled by the LIN MODE bit in the SCIGCR1 register. These registers are accessible in 8-, 16-, and 32-bit reads or writes. The SCI/LIN is controlled and accessed through the registers listed in Table 28-10.
SCI/LIN Control Registers www.ti.com 28.7.1 SCI Global Control Register 0 (SCIGCR0) The SCIGCR0 register defines the module reset. Figure 28-28 and Table 28-11 illustrate this register. Figure 28-28. SCI Global Control Register 0 (SCIGCR0) (offset = 00) 31 16 Reserved R-0 15 1 0 Reserved RESET R-0 R/WP-0 LEGEND: R = Read only; R/WP = Read/Write in privileged mode only; -n = value after reset Table 28-11.
SCI/LIN Control Registers www.ti.com 28.7.2 SCI Global Control Register 1 (SCIGCR1) The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI. Figure 28-29 and Table 28-12 illustrate this register. Figure 28-29.
SCI/LIN Control Registers www.ti.com Table 28-12. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued) Bit Field 16 LOOP BACK 15-14 13 12 Reserved Value Description Loopback bit. This bit is effective in LIN and SCI modes. The self-checking option for the SCI/LIN can be selected with this bit. If the LINITX and LINRX pins are configured with SCI/LIN functionality, then the LINTX pin is internally connected to the LINRX pin.
SCI/LIN Control Registers www.ti.com Table 28-12. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued) Bit 7 Field Value SWnRST Description Software reset (active low). This bit is effective in LIN and SCI modes. 0 The SCI/LIN is in its reset state; no data will be transmitted or received. Writing a 0 to this bit initializes the SCI/LIN state machines and operating flags as defined in Table 28-13 and Table 28-14.
SCI/LIN Control Registers www.ti.com Table 28-12. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued) Bit Field 0 Value COMM MODE Description SCI/LIN communication mode bit. In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. SCI mode: 0 Idle-line mode is used. 1 Address-bit mode is used. LIN mode: 0 ID4 and ID5 are not used for length control. 1 ID4 and ID5 are used for length control.
SCI/LIN Control Registers www.ti.com 28.7.3 SCI Global Control Register 2 (SCIGCR2) The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate a wakeup and for low-power mode control of the LIN module. Figure 28-30 and Table 28-15 illustrate this register. Figure 28-30.
SCI/LIN Control Registers www.ti.com Table 28-15. SCI Global Control Register 2 (SCIGCR2) Field Descriptions (continued) Bit 0 Field Value POWERDOWN SPNU562 – May 2014 Submit Documentation Feedback Description Power down. This bit is effective in LIN or SCI mode. When this bit is set, the SCI/LIN module attempts to enter local low-power mode.
SCI/LIN Control Registers www.ti.com 28.7.4 SCI Set Interrupt Register (SCISETINT) Figure 28-31 and Table 28-16 illustrate this register. Refer Figure 28-31 for details on when different interrupt flags get set in a frame during LIN Mode. Figure 28-31.
SCI/LIN Control Registers www.ti.com Table 28-16. SCI Set Interrupt Register (SCISETINT) Field Descriptions (continued) Bit Field 26 SET FE INT Value Description Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 0 Read: The interrupt is disabled. Write: No effect. 1 25 SET OE INT Read or write: The interrupt is enabled. Set overrun-error interrupt.
SCI/LIN Control Registers www.ti.com Table 28-16. SCI Set Interrupt Register (SCISETINT) Field Descriptions (continued) Bit 8 Field Value SET TX INT Description Set transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 0 Read: The interrupt is disabled. Write: No effect.
SCI/LIN Control Registers www.ti.com 28.7.5 SCI Clear Interrupt Register (SCICLEARINT) Figure 28-32 and Table 28-17 illustrate this register. SCICLEARINT register is used to clear the enabled interrupts without accessing SCISETINT register. Figure 28-32.
SCI/LIN Control Registers www.ti.com Table 28-17. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions (continued) Bit Field 27 CLR NRE INT Value Description Clear no-response-error interrupt. This bit is effective in LIN mode only. This bit disables the NRE interrupt when set. 0 Read: The interrupt is disabled. Write: No effect. 1 Read: The interrupt is enabled. Write: The interrupt is disabled. 26 CLR FE INT Clear framing-error interrupt. This bit is effective in LIN or SCI mode.
SCI/LIN Control Registers www.ti.com Table 28-17. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions (continued) Bit 12-10 9 Field Reserved Value 0 CLR RX INT Description Read returns 0. Writes have no effect. Clear receiver interrupt. This bit is effective in LIN or SCI mode. This bit disables the receiver interrupt when set. 0 Read: The interrupt is disabled. Write: No effect. 1 Read: The interrupt is enabled. Write: The interrupt is disabled.
SCI/LIN Control Registers www.ti.com 28.7.6 SCI Set Interrupt Level Register (SCISETINTLVL) Figure 28-33 and Table 28-18 illustrate this register. Figure 28-33.
SCI/LIN Control Registers www.ti.com Table 28-18. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions (continued) Bit Field 25 SET OE INT LVL Value Description Set overrun-error interrupt level. This bit is effective in LIN or SCI-compatible mode. 0 Read: The interrupt level is mapped to the INT0 line. Write: No effect. 1 24 SET PE INT LVL Read or write: The interrupt level is mapped to the INT1 line. Set parity error interrupt level.
SCI/LIN Control Registers www.ti.com Table 28-18. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions (continued) Bit 0 Field Value SET BRKDT INT LVL Description Set break-detect interrupt level. This bit is effective in SCI-compatible mode only. 0 Read: The interrupt level is mapped to the INT0 line. Write: No effect. 1 1404 Read or write: The interrupt level is mapped to the INT1 line.
SCI/LIN Control Registers www.ti.com 28.7.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL) Figure 28-34 and Table 28-19 illustrate this register. Figure 28-34.
SCI/LIN Control Registers www.ti.com Table 28-19. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions (continued) Bit Field 26 CLR FE INT LVL Value Description Clear framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. 0 Read: The interrupt level is mapped to the INT0 line. Write: No effect. 1 Read: The interrupt level is mapped to the INT1 line. Write: The interrupt level is mapped to the INT0 line. 25 CLR OE INT LVL Clear overrun-error interrupt.
SCI/LIN Control Registers www.ti.com Table 28-19. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions (continued) Bit 6 Field Value CLR TOAWUS INT LVL Description Clear timeout after wakeup signal interrupt. This bit is effective in LIN mode only. 0 Read: The interrupt level is mapped to the INT0 line. Write: No effect. 1 Read: The interrupt level is mapped to the INT1 line. Write: The interrupt level is mapped to the INT0 line.
SCI/LIN Control Registers www.ti.com 28.7.8 SCI Flags Register (SCIFLR) Figure 28-35 and Table 28-20 illustrate this register. Figure 28-35.
SCI/LIN Control Registers www.ti.com Table 28-20. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit Field 29 CE Value Description Checksum error flag. This bit is effective in LIN mode only. This bit is set when a checksum error has been detected by a receiving node. This error is detected by the TED logic. See Section 28.3.1.8 for more information. The type of checksum to be used depends on the CTYPE bit in SCIGCR1.
SCI/LIN Control Registers www.ti.com Table 28-20. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit Field 26 FE Value Description Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatibility mode, only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed.
SCI/LIN Control Registers www.ti.com Table 28-20. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit Field 14 ID RX FLAG Value Description Identifier on receive flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with an receive match and no ID-parity error. See Section 28.3.1.9 for more details. This flag indicates that a new valid identifier has been received on an RX match.
SCI/LIN Control Registers www.ti.com Table 28-20. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit Field 10 TXWAKE Value Description Transmitter wakeup method select. This bit is effective in SCI mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format.
SCI/LIN Control Registers www.ti.com Table 28-20. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit 7 Field Value TOA3WUS Description Timeout after three wakeup signals flag. This bit is effective in LIN mode only. This flag is set if there is no synch break received after three wakeup signals and a period of 1.5 seconds has passed. Such expiration time is used before issuing another round of wakeup signals.
SCI/LIN Control Registers www.ti.com Table 28-20. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit Field 2 IDLE Value Description SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit.
SCI/LIN Control Registers www.ti.com 28.7.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0) Figure 28-36 and Table 28-21 illustrate this register. Figure 28-36. SCI Interrupt Vector Offset 0 (SCIINTVECT0) (offset = 20h) 31 16 Reserved R-0 15 5 4 0 Reserved INTVECT0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-21. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions Bit Field Value 31-5 Reserved 0 4-0 INVECT0 0-1Fh Description Read returns 0.
SCI/LIN Control Registers www.ti.com 28.7.11 SCI Format Control Register (SCIFORMAT) Figure 28-38 and Table 28-23 illustrate this register. Figure 28-38. SCI Format Control Register (SCIFORMAT) (offset = 28h) 31 19 18 16 Reserved LENGTH R-0 R/W-0 15 3 2 0 Reserved CHAR R-0 R/WC-0 LEGEND: R/W = Read/Write; R = Read only; WC = Write in SCI-compatible mode only; -n = value after reset Table 28-23.
SCI/LIN Control Registers www.ti.com 28.7.12 Baud Rate Selection Register (BRS) This section describes the baud rate selection register. Figure 28-39 and Table 28-24 illustrate this register. Figure 28-39. Baud Rate Selection Register (BRS) (offset = 2Ch) 31 30 28 27 24 23 16 Rsvd U M PRESCALER P R-0 R/W-0 R/W-0 R/W-0 15 0 PRESCALER P R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-24.
SCI/LIN Control Registers www.ti.com Table 28-25. Comparative Baud Values for Different P Values, Asynchronous Mode 24-Bit Register Value (1) (2) 1418 Baud Selected (1) (2) Percent Error Decimal Hex Ideal Actual 26 00001A 115200 115740 0.47 53 000035 57600 57870 0.47 80 000050 38400 38580 0.47 162 0000A2 19200 19172 -0.15 299 00012B 10400 10417 0.16 325 000145 9600 9586 -0.15 399 00018F 7812.5 7812.5 0.00 650 00028A 4800 4800 0.
SCI/LIN Control Registers www.ti.com 28.7.13 SCI Data Buffers (SCIED, SCIRD, SCITD) The SCI has three addressable registers in which transmit and receive data is stored. These three registers are available in SCI mode only. 28.7.13.1 Receiver Emulation Data Buffer (SCIED) The SCIED register is addressed at a location different from SCIRD, but is physically the same register. Figure 28-40 and Table 28-26 illustrate this register. Figure 28-40.
SCI/LIN Control Registers www.ti.com 28.7.13.3 Transmit Data Buffer Register (SCITD) Data to be transmitted is written to the SCITD register. Figure 28-42 and Table 28-28 illustrate this register. Figure 28-42. Transmit Data Buffer Register (SCITD) (offset = 38h) 31 16 Reserved R-0 15 8 7 0 Reserved TD R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-28.
SCI/LIN Control Registers www.ti.com 28.7.15 SCI Pin I/O Control Register 1 (SCIPIO1) Figure 28-44 and Table 28-30 illustrate this register. Figure 28-44. SCI Pin I/O Control Register 1 (SCIPIO1) (offset = 40h) 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX DIR RX DIR Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-30.
SCI/LIN Control Registers www.ti.com 28.7.16 SCI Pin I/O Control Register 2 (SCIPIO2) Figure 28-45 and Table 28-33 illustrate this register. Figure 28-45. SCI Pin I/O Control Register 2 (SCIPIO2) (offset = 44h) 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX IN RX IN Reserved R-0 R-X R-X R-X LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = Indeterminate Table 28-33.
SCI/LIN Control Registers www.ti.com 28.7.17 SCI Pin I/O Control Register 3 (SCIPIO3) Figure 28-46 and Table 28-34 illustrate this register. Figure 28-46. SCI Pin I/O Control Register 3 (SCIPIO3) (offset = 48h) 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX OUT RX OUT Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-34.
SCI/LIN Control Registers www.ti.com 28.7.18 SCI Pin I/O Control Register 4 (SCIPIO4) Figure 28-47 and Table 28-35 illustrate this register. Figure 28-47. SCI Pin I/O Control Register 4 (SCIPIO4) (offset = 4Ch) 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX SET RX SET Reserved R-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-35.
SCI/LIN Control Registers www.ti.com 28.7.19 SCI Pin I/O Control Register 5 (SCIPIO5) Figure 28-48 and Table 28-36 illustrate this register. Figure 28-48. SCI Pin I/O Control Register 5 (SCIPIO5) (offset = 50h) 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX CLR RX CLR Reserved R-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-36.
SCI/LIN Control Registers www.ti.com 28.7.20 SCI Pin I/O Control Register 6 (SCIPIO6) Figure 28-49 and Table 28-37 illustrate this register. Figure 28-49. SCI Pin I/O Control Register 6 (SCIPIO6) (offset = 54h) 31 8 Reserved R-0 2 1 0 Reserved 3 TX PDR RX PDR Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-37.
SCI/LIN Control Registers www.ti.com 28.7.21 SCI Pin I/O Control Register 7 (SCIPIO7) Figure 28-50 and Table 28-38 illustrate this register. Figure 28-50. SCI Pin I/O Control Register 7 (SCIPIO7) (offset = 58h) 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX PD RX PD Reserved R-0 R/W-n R/W-n R/W-n LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, Refer to the Terminal Functions in the device datasheet for default pin settings. Table 28-38.
SCI/LIN Control Registers www.ti.com 28.7.22 SCI Pin I/O Control Register 8 (SCIPIO8) Figure 28-51 and Table 28-39 illustrate this register. Figure 28-51. SCI Pin I/O Control Register 8 (SCIPIO8) (offset = 5Ch) 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX PSL RX PSL Reserved R-0 R/W-n R/W-n R/W-n LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, Refer to the Terminal Functions in the device datasheet for default pin settings. Table 28-39.
SCI/LIN Control Registers www.ti.com 28.7.23 LIN Compare Register (LINCOMPARE) Figure 28-52 and Table 28-40 illustrate this register. Figure 28-52. LIN Compare Register (LINCOMPARE) (offset = 60h) 31 16 Reserved R-0 15 10 9 8 7 3 2 0 Reserved SDEL Reserved SBREAK R-0 RWP-0 R-0 RWP-0 LEGEND: R/W = Read/Write; R = Read only; RWP = Read/Write in privileged mode only; -n = value after reset Table 28-40.
SCI/LIN Control Registers www.ti.com 28.7.24 LIN Receive Buffer 0 Register (LINRD0) Figure 28-53 and Table 28-41 illustrate this register. Figure 28-53. LIN Receive Buffer 0 Register (LINRD0) (offset = 64h) 31 24 23 16 RD0 RD1 R-0 R-0 15 8 7 0 RD2 RD3 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-41. LIN Receive Buffer 0 Register (LINRD0) Field Descriptions Bit Field Value Description 31-24 RD0 0-FFh Receive buffer 0.
SCI/LIN Control Registers www.ti.com 28.7.25 LIN Receive Buffer 1 Register (LINRD1) Figure 28-54 and Table 28-42 illustrate this register. Figure 28-54. LIN Receive Buffer 1 Register (RD1) (offset = 68h) 31 24 23 16 RD4 RD5 R-0 R-0 15 8 7 0 RD6 RD7 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-42. LIN Receive Buffer 1 Register (RD1) Field Descriptions Bit Field Value Description 31-24 RD4 0-FFh Receive buffer 4. Byte 4 of the response data byte.
SCI/LIN Control Registers www.ti.com 28.7.26 LIN Mask Register (LINMASK) Figure 28-55 and Table 28-43 illustrate this register. Figure 28-55. LIN Mask Register (LINMASK) (offset = 6Ch) 31 24 23 16 Reserved RX ID MASK R-0 R/WL-0 15 8 7 0 Reserved TX ID MASK R-0 R/WL-0 LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -n = value after reset Table 28-43.
SCI/LIN Control Registers www.ti.com 28.7.27 LIN Identification Register (LINID) Figure 28-56 and Table 28-44 illustrate this register. Figure 28-56. LIN Identification Register (LINID) (offset = 70h) 31 24 23 16 Reserved RECEIVED ID R-0 R-0 15 8 7 0 ID-SlaveTask BYTE ID BYTE R/WL-0 R/WL-0 LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -n = value after reset Table 28-44.
SCI/LIN Control Registers www.ti.com 28.7.28 LIN Transmit Buffer 0 Register (LINTD0) Figure 28-57 and Table 28-45 illustrate this register. Figure 28-57. LIN Transmit Buffer 0 Register (LINTD0) (offset = 74h) 31 24 23 16 TD0 TD1 R/W-0 R/W-0 15 8 7 0 TD2 TD3 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28-45. LIN Transmit Buffer 0 Register (LINTD0) Field Descriptions Bit Field Value Description 31-24 TD0 0-FFh 8-Bit transmit buffer 0.
SCI/LIN Control Registers www.ti.com 28.7.30 Maximum Baud Rate Selection Register (MBRS) Figure 28-59 and Table 28-47 illustrate this register. Figure 28-59. Maximum Baud Rate Selection Register (MBRS) (offset = 7Ch) 31 16 Reserved R-0 15 13 12 0 Reserved MBR R-0 R/WL-DACh LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -n = value after reset Table 28-47.
SCI/LIN Control Registers www.ti.com 28.7.31 Input/Output Error Enable (IODFTCTRL) Register Figure 28-60 and Table 28-48 illustrate this register. After the basic SCI/LIN module configuration, enable the required Error mode to be created followed by IODFT Key enable. NOTE: 1) All the bits are used in IODFT mode only. 2) Each IODFT are expected to be checked individually. 3) ISFE Error will not be Flagged during IODFT mode. Figure 28-60.
SCI/LIN Control Registers www.ti.com Table 28-48. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions (continued) Bit Field 25 PEN 24 Reserved 20-19 PIN SAMPLE MASK 0 No parity error occurs. 1 The parity bit received is toggled so that a parity error occurs. Break detect error enable. This bit is effective in SCI-compatible mode only. This bit is used to create a BRKDT error. 0 No error is created.
Chapter 29 SPNU562 – May 2014 Serial Communication Interface (SCI) Module This chapter contains the description of the serial communication interface (SCI) module. Topic 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 1438 ........................................................................................................................... Introduction ................................................................................................... SCI Communication Formats ..............................
Introduction www.ti.com 29.1 Introduction The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a Kline. 29.1.
Introduction www.ti.com The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. The receiver and transmitter may each be operated independently or simultaneously in full duplex mode. To ensure data integrity, the SCI checks the data it receives for breaks, parity, overrun, and framing errors. The bit rate (baud) is programmable to over 16 million different rates through a 24-bit baud-select register. Figure 29-1 shows the detailed SCI block diagram.
SCI Communication Formats www.ti.com 29.2 SCI Communication Formats The SCI module can be configured to meet the requirements of many applications. Because communication formats vary depending on the specific application, many attributes of the SCI are user configurable. The list below describes these configuration options: • SCI Frame format • SCI Timing modes • SCI Baud rate • SCI Multiprocessor modes 29.2.1 SCI Frame Formats The SCI uses a programmable frame format.
SCI Communication Formats www.ti.com 29.2.2.1 Asynchronous Timing Mode The asynchronous timing mode uses only the receive and transmit data lines to interface with devices using the standard universal asynchronous receiver- transmitter (UART) protocol. In the asynchronous timing mode, each bit in a frame has a duration of 16 SCI baud clock periods. Each bit therefore consists of 16 samples (one for each clock period).
SCI Communication Formats www.ti.com In isosynchronous timing mode, the SCI generates a baud clock according to the following formula: VBUSPCLK Frequency Isosynchronous baud value = ----------------------------------------------------------------BAUD + 1 For BAUD = 0, Isosynchronous baud value = VCLK Frequency ------------------------------------------------32 (56) 29.2.4 SCI Multiprocessor Communication Modes In some applications, the SCI may be connected to more than one serial communication device.
SCI Communication Formats www.ti.com As indicated by Step 3, software should wait for the SCI to clear the TXWAKE bit. However, the SCI clears the TXWAKE bit at the same time it sets TXRDY (that is, transfers data from SCITD into SCITXSHF). Therefore, if the TX INT ENA bit is set, the transfer of data from SCITD to SCITXSHF causes an interrupt to be generated at the same time that the SCI clears the TXWAKE bit.
SCI Communication Formats www.ti.com 29.2.4.2 Address-Bit Multiprocessor Mode In the address-bit protocol, each frame has an extra bit immediately following the data field called an address bit. A frame with the address bit set to 1 is an address frame; a frame with the address bit set to 0 is a data frame. The idle period timing is irrelevant in this mode. Figure 29-5 illustrates the format of several blocks and frames with the address-bit mode.
SCI Interrupts www.ti.com 29.3 SCI Interrupts The SCI module has two interrupt lines, level 0 and level 1, to the vectored interrupt manager (VIM) module (see Figure 29-6). Two offset registers SCIINTVECT0 and SCIINTVECT1 determine which flag triggered the interrupt according to the respective priority encoders. Each interrupt condition has a bit to enable/disable the interrupt in the SCISETINT and SCICLRINT registers, respectively.
SCI Interrupts www.ti.com Figure 29-7. Interrupt Generation for Given Flags 5-bit INTVECT0 Priority Encoder 0 ... ... INT0 INTx LVL FLAGx ENA INT x ... INT1 ... Priority Encoder 1 5-bit INTVECT1 29.3.1 Transmit Interrupt To use transmit interrupt functionality, SET TX INT bit must be enabled and SET TX DMA bit must be cleared. The transmit ready (TXRDY) flag is set when the SCI transfers the contents of SCITD to the shift register, SCITXSHF.
SCI Interrupts www.ti.com 29.3.4 Error Interrupts The following error detection features are supported with Interrupt by the SCI module: • Parity errors (PE) • Frame errors (FE) • Break Detect errors (BRKDT) • Overrun errors (OE) If any of these errors (PE, FE, BRKDT, OE) is flagged, an interrupt for the flagged errors will be generated if enabled. A message is valid for both the transmitter and the receiver if there is no error detected until the end of the frame.
SCI DMA Interface www.ti.com 29.4 SCI DMA Interface DMA requests for receive (RXDMA request) and transmit (TXDMA request) are available for the SCI module. Refer to the DMA module chapter for DMA module configurations. 29.4.1 Receive DMA Requests This DMA functionality is enabled/disabled by the CPU using the SET RX DMA/CLR RX DMA bits, respectively. The receiver DMA request is set when a frame is received successfully and DMA functionality has been previously enabled.
SCI DMA Interface www.ti.com Transmit DMA requests are enabled by the setting SET TX DMA and SET TX INT bits. If the SET TX DMA bit is set, then a TX DMA request is sent to the DMA when data is written to SCITD and TXRDY is set. In other words, CPU needs to write the first data to start a DMA block transfer. For example, we want to transmit a data buffer of 20 bytes. DMA will be set up to transmit 19 bytes. The first data for DMA to transfer is the second byte in the buffer.
SCI Configurations www.ti.com 29.5 SCI Configurations Before the SCI sends or receives data, its registers should be properly configured. Upon power-up or a system-level reset, each bit in the SCI registers is set to a default state. The registers are writable only after the RESET bit is set to 1. Of particular importance is the SWnRST bit. This active-low bit is initialized to 0 and keeps the SCI in a reset state until it is programmed to 1.
SCI Configurations www.ti.com 29.5.2 Transmitting Data The SCI transmitter is enabled if the TX FUNC bit and the TXENA bit are set to 1. If the TX FUNC bit is not set, the SCITX pin functions as a general purpose I/O pin rather than as an SCI function pin. Any value written to the SCITD before TXENA is set to 1 is not transmitted. Both of these control bits allow for the SCI transmitter to be held inactive independently of the receiver.
SCI Low Power Mode www.ti.com 29.6.1 Sleep Mode for Multiprocessor Communication When the SCI receives data and transfers that data from SCIRXSHF to SCIRD, the RXRDY bit is set and if RX INT ENA is set, the SCI also generates an interrupt. The interrupt triggers the CPU to read the newly received frame before another one is received. In multiprocessor communication modes, this default behavior may be enhanced to provide selective indication of new data.
SCI Control Registers www.ti.com 29.7 SCI Control Registers These registers are accessible in 8-, 16-, and 32-bit reads or writes. The SCI is controlled and accessed through the registers listed in Table 29-3. Among the features that can be programmed are the SCI communication and timing modes, baud rate value, frame format, DMA requests, and interrupt configuration. The base address for the control registers is FFF7 E500h for SCI3 and FFF7 E700h for SCI4. Table 29-3.
SCI Control Registers www.ti.com 29.7.1 SCI Global Control Register 0 (SCIGCR0) The SCIGCR0 register defines the module reset. Figure 29-8 and Table 29-4 illustrate this register. Figure 29-8. SCI Global Control Register 0 (SCIGCR0) [offset = 00] 31 16 Reserved R-0 15 1 0 Reserved RESET R-0 RWP-0 LEGEND: R/W = Read/Write; R = Read only; RWP = Read/Write in privileged mode only; -n = value after reset Table 29-4.
SCI Control Registers www.ti.com 29.7.2 SCI Global Control Register 1 (SCIGCR1) The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI. Figure 29-9 and Table 29-5 illustrate this register. Figure 29-9.
SCI Control Registers www.ti.com Table 29-5. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued) Bit Field 16 LOOP BACK 15-10 9 8 Value Reserved Description Loopback bit. The self-checking option for the SCI can be selected with this bit. If the SCITX and SCIRX pins are configured with SCI functionality, then the SCITX pin is internally connected to the SCIRX pin.
SCI Control Registers www.ti.com Table 29-5. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued) Bit 3 Field Value PARITY Description SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. 0 Odd parity is used. 1 Even parity is used. The parity bit is calculated based on the data bits in each frame and the address bit (in address-bit mode). The start and stop fields in the frame are not included in the parity calculation.
SCI Control Registers www.ti.com 29.7.3 SCI Set Interrupt Register (SCISETINT) Figure 29-10 and Table 29-6 illustrate this register. SCISETINT register is used to enable the required interrupts supported by the module. Figure 29-10.
SCI Control Registers www.ti.com Table 29-6. SCI Set Interrupt Register (SCISETINT) Field Descriptions (continued) Bit Field 16 SET TX DMA Value Description Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT). 0 Read: Transmit DMA request is disabled. Write: No effect. 15-10 9 Reserved 1 Read or write: Transmit DMA request is enabled. 0 Read returns 0.
SCI Control Registers www.ti.com 29.7.4 SCI Clear Interrupt Register (SCICLEARINT) Figure 29-11 and Table 29-7 illustrate this register. SCICLEARINT register is used to clear the selected enabled interrupts with out accessing SCISETINT register. Figure 29-11.
SCI Control Registers www.ti.com Table 29-7. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions (continued) Bit Field 17 CLR RX DMA Value Description Clear receive DMA request. This bit disables the receive DMA request when set. 0 Read: The DMA request is disabled. Write: No effect. 1 Read: The receive DMA request is enabled. Write: The receive DMA request for is disabled. 16 CLR TX DMA Clear transmit DMA request. This bit disables the transmit DMA request when set.
SCI Control Registers www.ti.com 29.7.5 SCI Set Interrupt Level Register (SCISETINTLVL) Figure 29-12 and Table 29-8 illustrate this register. This register is used to set the interrupt level for the supported interrupts. Figure 29-12.
SCI Control Registers www.ti.com Table 29-8. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions (continued) Bit Field 8 Value SET TX INT LVL Description Set transmitter interrupt level. 0 Read: The interrupt level is mapped to the INT0 line. Write: No effect. 7-2 Reserved 1 1 Read or write: The interrupt level is mapped to the INT1 line. 0 Read returns 0. Writes have no effect. SET WAKEUP INT LVL Set wakeup interrupt level.
SCI Control Registers www.ti.com Table 29-9. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions (continued) Bit Field 25 CLR CE INT LVL Value Description Clear overrun-error interrupt. 0 Read: The interrupt level is mapped to the INT0 line. Write: No effect. 1 Read: The interrupt level is mapped to the INT1 line. Write: The interrupt level is mapped to the INT0 line. 24 CLR PE INT LVL Clear parity interrupt. 0 Read: The interrupt level is mapped to the INT0 line.
SCI Control Registers www.ti.com 29.7.7 SCI Flags Register (SCIFLR) Figure 29-14 and Table 29-10 illustrate this register. Figure 29-14.
SCI Control Registers www.ti.com Table 29-10. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit Field 24 PE Value Description Parity error flag. This bit is set when a parity error is detected in the received data. In SCI addressbit mode, the parity is calculated on the data and address bit fields of the received frame. In idleline mode, only the data is used to calculate parity.
SCI Control Registers www.ti.com Table 29-10. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit 9 Field Value RXRDY Description Receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA.
SCI Control Registers www.ti.com Table 29-10. SCI Flags Register (SCIFLR) Field Descriptions (continued) Bit Field 1 Value WAKEUP Description Wakeup flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit (SCISETINT[2]) is set.
SCI Control Registers www.ti.com 29.7.8 SCI Interrupt Vector Offset 0 (SCIINTVECT0) Figure 29-15 and Table 29-13 illustrate this register. Figure 29-15. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h] 31 16 Reserved R-0 15 4 3 0 Reserved INTVECT0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-13. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions Bit Field Value 31-4 Reserved 0 3-0 INVECT0 0-Fh Description Read returns 0.
SCI Control Registers www.ti.com 29.7.10 SCI Format Control Register (SCIFORMAT) Figure 29-17 and Table 29-15 illustrate this register. Figure 29-17. SCI Format Control Register (SCIFORMAT) [offset = 28h] 31 16 Reserved R-0 15 3 2 0 Reserved CHAR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-15. SCI Format Control Register (SCIFORMAT) Field Descriptions Bit Field 31-3 Reserved 2-0 CHAR Value 0 Description Read returns 0. Writes have no effect.
SCI Control Registers www.ti.com 29.7.11 Baud Rate Selection Register (BRS) This section describes the baud rate selection register. Figure 29-18 and Table 29-16 illustrate this register. Figure 29-18. Baud Rate Selection Register (BRS) [offset = 2Ch] 31 24 23 16 Reserved BAUD R-0 R/W-0 15 0 BAUD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-16.
SCI Control Registers www.ti.com 29.7.12 SCI Data Buffers (SCIED, SCIRD, SCITD) The SCI has three addressable registers in which transmit and receive data is stored. 29.7.12.1 Receiver Emulation Data Buffer (SCIED) The SCIED register is addressed at a location different from SCIRD, but is physically the same register. Figure 29-19 and Table 29-18 illustrate this register. Figure 29-19.
SCI Control Registers www.ti.com 29.7.12.3 Transmit Data Buffer Register (SCITD) Data to be transmitted is written to the SCITD register. Figure 29-21 and Table 29-20 illustrate this register. Figure 29-21. Transmit Data Buffer Register (SCITD) [offset = 38h] 31 16 Reserved R-0 15 8 7 0 Reserved TD R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-20.
SCI Control Registers www.ti.com 29.7.14 SCI Pin I/O Control Register 1 (SCIPIO1) Figure 29-23 and Table 29-22 illustrate this register. Figure 29-23. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h] 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX DIR RX DIR Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-22.
SCI Control Registers www.ti.com 29.7.15 SCI Pin I/O Control Register 2 (SCIPIO2) Figure 29-24 and Table 29-25 illustrate this register. Figure 29-24. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h] 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX IN RX IN Reserved R-0 R-X R-X R-X LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = Indeterminate Table 29-25.
SCI Control Registers www.ti.com 29.7.16 SCI Pin I/O Control Register 3 (SCIPIO3) Figure 29-25 and Table 29-26 illustrate this register. Figure 29-25. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h] 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX OUT RX OUT Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-26.
SCI Control Registers www.ti.com 29.7.17 SCI Pin I/O Control Register 4 (SCIPIO4) Figure 29-26 and Table 29-27 illustrate this register. Figure 29-26. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch] 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX SET RX SET Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-27.
SCI Control Registers www.ti.com 29.7.18 SCI Pin I/O Control Register 5 (SCIPIO5) Figure 29-27 and Table 29-28 illustrate this register. Figure 29-27. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h] 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX CLR RX CLR Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-28.
SCI Control Registers www.ti.com 29.7.19 SCI Pin I/O Control Register 6 (SCIPIO6) Figure 29-28 and Table 29-29 illustrate this register. Figure 29-28. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h] 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX PDR RX PDR Reserved R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29-29.
SCI Control Registers www.ti.com 29.7.20 SCI Pin I/O Control Register 7 (SCIPIO7) Figure 29-29 and Table 29-30 illustrate this register. Figure 29-29. SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h] 31 8 Reserved R-0 7 2 1 0 Reserved 3 TX PD RX PD Reserved R-0 R/W-n R/W-n R/W-n LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, Refer to the Terminal Functions in the device datasheet for default pin settings. Table 29-30.
SCI Control Registers www.ti.com 29.7.22 Input/Output Error Enable (IODFTCTRL) Register Figure 29-31 and Table 29-32 illustrate this register. After the basic SCI module configuration, enable the required Error mode to be created followed by IODFT Key enable. NOTE: 1. 2. All the bits are used in IODFT mode only. Each IODFT are expected to be checked individually. Figure 29-31.
SCI Control Registers www.ti.com Table 29-32. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions (continued) Bit 18-16 Field Value TX SHIFT 15-12 Reserved 11-8 IODFTENA 7-2 Reserved 1 LPBENA Description Transmit shift. These bits define the amount by which the value on TX pin is delayed so that the value on the RX pin is asynchronous. This feature is not applicable to the start bit. 0 No delay occurs. 1h The value is delayed by 1 SCLK. 2h The value is delayed by 2 SCLK.
GPIO Functionality www.ti.com 29.8 GPIO Functionality The following sections apply to all device pins that can be configured as functional or general-purpose I/O pins. 29.8.1 GPIO Functionality Figure 29-32 illustrates the GPIO functionality. Figure 29-32. GPIO Functionality Output enable Data out Device pin Data in Input enable Pull control disable Pull control logic Pull select Output enable Data out Device pin Data in Input enable Pull control logic Pull control disable 29.8.
GPIO Functionality www.ti.com 29.8.3 Out of Reset The following apply if the device is out of reset: • Pull control. The pull control is enabled by clearing the PD (pull control disable) bit in the SCIPIO7 register (Section 29.7.20). In this case, if the PSL (pull select) bit in the SCIPIO8 register (Section 29.7.21) is set, the pin will have a pull-up. If the PSL bit is cleared, the pin will have a pulldown. If the PD bit is set in the control register, there is no pull-up or pull-down on the pin.
Chapter 30 SPNU562 – May 2014 Inter-Integrated Circuit (I2C) Module This chapter describes the inter-integrated circuit (I2C or I2C) module. The I2C is a multi-master communication module providing an interface between the Texas Instruments (TI) microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2Cbus. This module will support any slave or master I2C compatible device. Topic 30.1 30.2 30.3 30.4 30.5 30.6 30.7 1486 .....................
Overview www.ti.com 30.1 Overview The I2C has the following features: • Compliance to the Philips I2C bus specification, v2.
Overview www.ti.com 30.1.2 Functional Overview The I2C module is a serial bus that supports multiple master devices. In multimaster mode, one or more devices can be connected to the same bus and are capable of controlling the bus. Each I2C device on the bus is recognized by a unique address and can operate as either a transmitter or a receiver, depending on the function of the device.
Overview www.ti.com Figure 30-2.
Overview www.ti.com 30.1.3 Clock Generation As shown in Figure 30-3, the I2C module uses the input clock generated from the device clock generator to generate the module clock and master clock. The I2C input clock is the device peripheral clock (VBUS_CLK). The clock is then divided twice more inside the I2C module to produce the module clock and the master clock. Figure 30-3.
I2C Module Operation www.ti.com NOTE: The master clock frequency defined above does not include rise/fall time and latency of the synchronizer inside the module. The actual transfer rate will be slower than the value calculated from the formula above. Also, due to the nature of SCL synchronization, the SCL clock period could change if SCL synchronization is taking place. 30.2 I2C Module Operation The following section discusses how the I2C module operates. 30.2.
I2C Module Operation www.ti.com 30.2.4 I2C Module Start and Stop Conditions START and STOP conditions are generated by a master I2C module. • The START condition is defined as a high-to-low transition on the SDA line while SCL is high. A master drives this condition to indicate the start of data transfer. The bus is considered to be busy after the START condition, and the bus busy bit (BB) in I2CSR is set to 1. • The STOP condition is defined as a low-to-high transition on the SDA line while SCL is high.
I2C Module Operation www.ti.com 30.2.5.1 7-Bit Addressing Format In the 7-bit addressing format (Figure 30-7), the first byte after the START condition consists of a 7-bit slave address followed by the R/W bit (in the LSB). The R/W bit determines the direction of the data transfer: • R/W = 0: The master writes (transmits) data to the addressed slave. • R/W = 1: The master reads (receives) data from the slave. An extra clock cycle dedicated for acknowledgement (ACK) is inserted after each byte.
I2C Module Operation www.ti.com 30.2.5.4 Free Data Format In this format (Figure 30-10), the first byte after a START condition is a data byte. The ACK bit is inserted after each byte, followed by another 8 bits of data. No address or data direction bit is sent. Therefore, the transmitter and receiver must both support the free data format. The direction of data transmission (transmit or receive) remains constant throughout the transfer.
I2C Operation Modes www.ti.com 30.3 I2C Operation Modes 30.3.1 Master Transmitter Mode All masters begin in this mode. The I2C module is a master and transmits control information and data to a slave. In this mode, data assembled in any of the addressing formats shown in Figure 30-7, Figure 30-8, or Figure 30-9 is shifted out onto the SDA pin and synchronized with the self-generated clock pulses on the SCL pin.
I2C Operation Modes www.ti.com 30.3.5 Low Power Mode The I2C module can be placed in low-power mode by a global low-power mode initiated by the system (by writing to the Peripheral Power-Down Set Register in the Peripheral Central Resource (PCR) module. In effect, low-power mode shuts down all the clocks to the module. In global low-power mode, no registers are visible to the software; nothing can be written to or read from any register. 30.3.
I2C Module Integrity www.ti.com 30.4 I2C Module Integrity The following section discusses how the I2C module maintains priorities and order among signals and commands. 30.4.1 Arbitration If two or more master transmitters simultaneously start a transmission on the same bus, an arbitration procedure is invoked. Figure 30-11 illustrates the arbitration procedure between two devices. The arbitration procedure uses the data presented on the SDA bus by the competing transmitters.
I2C Module Integrity www.ti.com 30.4.2 I2C Clock Generation and Synchronization Under normal conditions only one master device generates the clock signal; the SCL. During the arbitration procedure, however, there are two or more master devices and the clock must be synchronized so that the data output can be compared. Figure 30-12 illustrates clock synchronization. The wired-AND property of the SCL line means that a device that first generates a low period on the SCL overrules the other devices.
Operational Information www.ti.com 30.5 Operational Information The following section provides specific information about how the I2C module operates. 30.5.1 I2C Module Interrupts The I2C module generates seven types of interrupts. These seven interrupts are accompanied with seven interrupt mask bits in the interrupt mask register (I2CIMR) and with seven interrupt flag bits in the status register (I2CSR). 30.5.1.1 I2C Interrupt Requests The I2C module generates the interrupt requests described below.
Operational Information www.ti.com 30.5.2 DMA Controller Events The I2C module has two events that use the DMA controller to synchronously read received data (I2CREVNT) from I2CDRR, and synchronously write data (I2CWEVNT) to the transmit buffer, I2CDXR. The read and write events have the same timing as I2CRRDY (I2CRINT) and I2CXRDY (I2CXINT), respectively. The CPU or the DMA controller reads the received data from I2CDRR and writes the data to be transmitted to I2CDXR.
Operational Information www.ti.com 30.5.5 Pull Up/Pull Down Function I2C module pins can have either an active pull up or active pull down that makes it possible to leave the pins unconnected externally. The pins can be programmed to have the active pull function enabled or disabled by writing to the corresponding bit in the I2CPDIS register. Please see the device-specific data sheet for the default internal pull (pull-up, pull-down or no pull) on the pins.
I2C Control Registers www.ti.com 30.6 I2C Control Registers Table 30-3 provides a summary of the control registers. The upper word (upper 16 bits) of the registers all read as 0s. Writes have no effect on these bits. The base address for the control registers is FFF7 D400h for I2C1 and FFF7 D500h for I2C2. Table 30-3. I2C Control Registers Offset 1502 Acronym Register Description 00h I2COAR I2C Own Address Manager Section 30.6.1 Section 04h I2CIMR I2C Interrupt Mask Register Section 30.6.
I2C Control Registers www.ti.com 30.6.1 I2C Own Address Manager (I2COAR) The 16-bit memory-mapped I2C own address register is used to specify its own address. Figure 30-13 and Table 30-4 describe this register. Figure 30-13. I2C Own Address Manager Register (I2COAR) [offset = 00] 15 10 9 0 Reserved OA R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-4.
I2C Control Registers www.ti.com 30.6.2 I2C Interrupt Mask Register (I2CIMR) The 7-bit memory mapped I2C interrupt mask register is used by the device to enable/disable the interrupts. Figure 30-14 and Table 30-6 describe this register. Figure 30-14.
I2C Control Registers www.ti.com 30.6.3 I2C Status Register (I2CSTR) Figure 30-15 and Table 30-7 describe this register. Figure 30-15.
I2C Control Registers www.ti.com Table 30-7. I2C Status Register (I2CSTR) Field Descriptions (continued) Bit Field 10 XSMT Value Description Transmit shift empty This bit is cleared to 0 to indicate that the transmitter has experienced underflow. Underflow occurs when the transmit shift register is empty and I2CDXR has not been loaded since the last I2CDXR to transmit shift register transfer. The I2C core logic is waiting for I2CDXR write access.
I2C Control Registers www.ti.com Table 30-7. I2C Status Register (I2CSTR) Field Descriptions (continued) Bit Field 2 ARDY Value Description Register access ready interrupt flag This bit is set to 1 when the previously programmed address, data and command has been performed and the status bit has been updated. The flag is used by the device to indicate that the I2C registers are ready to be accessed again.
I2C Control Registers www.ti.com 30.6.4 I2C Clock Divider Low Register (I2CCKL) The I2C clock divider low register is a 16-bit memory mapped register used to divide the master clock down to obtain the I2C serial clock low time. Figure 30-16 and Table 30-8 describe this register. Figure 30-16. I2C Clock Divider Low Register (I2CCKL) [offset = 0Ch] 15 0 CLKL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-8.
I2C Control Registers www.ti.com 30.6.6 I2C Data Count Register (I2CCNT) The I2C data count register is a 16-bit memory-mapped register used to count received or transmitted data bytes. This register is also used to generate the STOP condition which terminates the transfer after the counter reaches zero. Figure 30-18 and Table 30-10 describe this register. Figure 30-18.
I2C Control Registers www.ti.com 30.6.8 I2C Slave Address Register (I2CSAR) The I2C slave address register is a 16-bit memory-mapped register used to specify the address of the slave device to communicate to on the I2C bus. Figure 30-20 and Table 30-12 describe this register. Figure 30-20. I2C Slave Address Register (I2CSAR) [offset = 1Ch] 15 10 9 0 Reserved SA R-0 R/W-3FFh LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-12.
I2C Control Registers www.ti.com 30.6.10 I2C Mode Register (I2CMDR) Figure 30-22 and Table 30-15 describe this register. Figure 30-22. I2C Mode Register (I2CMDR) [offset = 24h] 15 14 13 12 11 10 9 8 NACKMOD FREE STT Reserved STP MST TRX XA R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 2 7 6 5 4 3 RM DLB nIRS STB FDF BC 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-15.
I2C Control Registers www.ti.com Table 30-15. I2C Mode Register (I2CMDR) Field Descriptions (continued) Bit Field 9 TRX Value Description Transmit/receive bit This bit determines the direction of data transmission of the I2C module. See Table 30-17. 8 0 The module is in the receive mode and data on the SDA line is shifted into the data register I2CDRR. 1 The module is in the transmit mode and the data in the I2CDXR is shifted out on the SDA line.
I2C Control Registers www.ti.com Figure 30-23. Typical Timing Diagram of Repeat Mode Master-transmitter (repeat mode) (Please note that this behavior is independent of BCM bit) S Slave address W A Data Set STP bit Data A Data A nA P Interrupt Table 30-16. I2C Module Condition, Bus Activity, and Mode (1) Bus Activities (1) RM STT STP Condition 0 0 0 Idle Mode 0 0 1 Stop P N/A 0 1 0 (Repeat) Start S-A-D..(n)..D Repeat n 0 1 1 (Repeat) Start-Stop S-A-D..(n)..
I2C Control Registers www.ti.com 30.6.11 I2C Interrupt Vector Register (I2CIVR) The I2C interrupt vector register is a 16-bit memory-mapped register used to indicate the occurrence of an interrupt. Figure 30-24 and Table 30-19 describe this register. Figure 30-24. I2C Interrupt Vector Register (I2CIVR) [offset = 28h] 15 12 11 8 7 3 2 0 Reserved TESTMD Reserved INTCODE R-0 R/W-0 R-0 R/WC-0 LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset Table 30-19.
I2C Control Registers www.ti.com 30.6.12 I2C Extended Mode Register (I2CEMDR) The I2C extended mode register is a 16-bit memory-mapped register that contains additional mode select bits. Figure 30-25 and Table 30-21 describe this register. Figure 30-25. I2C Extended Mode Register (I2CEMDR) [offset = 2Ch] 15 2 1 0 Reserved IGNACK BCM R-0 R/W-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-21.
I2C Control Registers www.ti.com 30.6.14 I2C Peripheral ID Register 1 (I2CPID1) Figure 30-27 and Table 30-23 describe this register. Figure 30-27. I2C Peripheral ID Register 1 (I2CPID1) [offset = 34h] 15 8 7 0 CLASS REVISION R-1 R-46h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-23.
I2C Control Registers www.ti.com 30.6.16 I2C DMA Control Register (I2CDMACR) This register contains the transmit and receive DMA enable bits. Figure 30-29 and Table 30-25 describe this register. Figure 30-29. I2C DMA Control Register (I2CDMACR) [offset = 3Ch] 15 2 Reserved 1 0 TXDMAEN RXDMAEN R-0 R/W-1 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-25.
I2C Control Registers www.ti.com 30.6.18 I2C Pin Direction Register (I2CPDIR) This register is used to independently configure each I2C pin, when configured as a general purpose I/O, as either an input or output. Figure 30-31 and Table 30-27 describe this register. Figure 30-31. I2C Pin Direction Register (I2CPDIR) [offset = 4Ch] 15 1 0 Reserved 2 SDADIR SCLDIR R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-27.
I2C Control Registers www.ti.com 30.6.20 I2C Data Output Register (I2CDOUT) This register contains the values sent to the I2C pins. Figure 30-33 and Table 30-29 describe this register. Figure 30-33. I2C Data Output Register (I2CDOUT) [offset 0x54] 15 2 1 0 Reserved SDAOUT SCLOUT R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30-29.
I2C Control Registers www.ti.com 30.6.22 I2C Data Clear Register (I2CDCLR) The I2CDCLR register is an alias of the I2CDOUT register. When written to at this address, writing a 1 to a bit clears the corresponding bit in I2CDOUT to a 0, while writing a 0 leaves it unchanged. Figure 30-35 and Table 30-31 describe this register. Figure 30-35.
I2C Control Registers www.ti.com 30.6.24 I2C Pull Disable Register (I2CPDIS) Values in the I2CPDIS register enable or disable the pull control capability of the pins. A 0 in the I2CPDIS register enables the pull function of the corresponding pin, while a 1 disables the pull function. Figure 3037 and Table 30-33 describe this register. Figure 30-37.
I2C Control Registers www.ti.com 30.6.25.1 Summary The behavior of the input buffer, output buffer, and the pull control is summarized in Table 30-35. Table 30-35.
Sample Waveforms www.ti.com 30.7 Sample Waveforms Figure 30-40 provides waveforms to illustrate the difference between normal operation and backward compatibility mode. Figure 30-40.
Chapter 31 SPNU562 – May 2014 EMAC/MDIO Module This chapter describes the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module. Topic 31.1 31.2 31.3 31.4 31.5 1524 ........................................................................................................................... Introduction ................................................................................................... Architecture ................................
Introduction www.ti.com 31.1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the microcontroller. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and a description of the registers for each module.
Introduction www.ti.com 31.1.3 Functional Block Diagram Figure 31-1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor to the EMAC and MDIO modules. The EMAC control module controls device interrupts and incorporates an 8k-byte internal RAM to hold EMAC buffer descriptors (also known as CPPI RAM). The MDIO module implements the 802.
Introduction www.ti.com 31.1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E). However, the EMAC deviates from the standard in the way it handles transmit underflow errors.
Architecture www.ti.com 31.2.3 Signal Descriptions The microcontrollers support both the MII and the RMII interfaces. Only one of these two interfaces can be used at a time. A separate control register in the I/O Multiplexing Module (IOMM) allows the application to indicate the actual interface being used. This is the bit 24 of the PINMMR160 control register. This bit is set by default and selects the RMII interface. The application can select the MII interface by clearing this bit.
Architecture www.ti.com Table 31-1. EMAC and MDIO Signals for MII Interface Signal Type Description MII_TXCLK I Transmit clock (MII_TXCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MII_TXD and MII_TXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps operation. MII_TXD[3-0] O Transmit data (MII_TXD).
Architecture www.ti.com 31.2.3.2 Reduced Media Independent Interface (RMII) Connections Figure 31-3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection in a typical system. The individual EMAC and MDIO signals for the RMII interface are summarized in Table 31-2. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). Figure 31-3.
Architecture www.ti.com 31.2.4 MII / RMII Signal Multiplexing Control In Each of the MII and RMII interface signals are multiplexed with other functions on this microcontroller. The application must configure the control registers in the I/O multiplexing module in order to enable the MII/RMII functionality on the corresponding I/Os. Table 31-3 shows the byte to be configured to enable the MDIO functions. Table 31-4 shows the byte to be configured to enable the MII or RMII functions.
Architecture www.ti.com 31.2.5 Ethernet Protocol Overview A brief overview of the Ethernet protocol is given in the following subsections. See the IEEE 802.3 standard document for in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method. 31.2.5.1 Ethernet Frame Format All the Ethernet technologies use the same frame structure. The format of an Ethernet frame is shown in Figure 31-4 and described in Table 31-5.
Architecture www.ti.com 31.2.5.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.
Architecture www.ti.com Table 31-6. Basic Descriptor Description Word Offset Field Field Description 0 Next Descriptor Pointer The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor describes a packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field.
Architecture www.ti.com 31.2.6.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked lists as discussed in Section 31.2.6.1. The lists used by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). The EMAC supports eight channels for transmit and eight channels for receive.
Architecture www.ti.com 31.2.6.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 31.2.6.1, using the linked list queue mechanism discussed in Section 31.2.6.2. The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are controlled by the application using the interrupt masks, global interrupt enable, and the completion pointer register (CP).
Architecture www.ti.com Figure 31-7. Transmit Buffer Descriptor Format Word 0 31 0 Next Descriptor Pointer Word 1 31 0 Buffer Pointer Word 2 31 16 15 Buffer Offset 0 Buffer Length Word 3 31 30 29 28 27 26 SOP EOP OWNER EOQ TDOWNCMPLT PASSCRC 25 16 Reserved 15 0 Packet Length Example 31-1. Transmit Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC.
Architecture www.ti.com 31.2.6.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active transmit list. This pointer is not altered by the EMAC.
Architecture www.ti.com 31.2.6.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC. 31.2.6.4.
Architecture www.ti.com 31.2.6.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor (Figure 31-8) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 31-2 shows the receive buffer descriptor described by a C structure. 31.2.6.5.1 Next Descriptor Pointer This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive queue.
Architecture www.ti.com Example 31-2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC.
Architecture www.ti.com 31.2.6.5.4 Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
Architecture www.ti.com 31.2.6.5.11 Pass CRC (PASSCRC) Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC. This flag should be cleared by the software application before submitting the descriptor to the receive queue. 31.2.6.5.12 Jabber Flag This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is a jabber frame and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
Architecture www.ti.com 31.2.7 EMAC Control Module The EMAC control module (Figure 31-9) interfaces the EMAC and MDIO modules to the rest of the system, and also provides a local memory space to hold EMAC packet buffer descriptors. Local memory is used to help avoid contention with device memory spaces. Other functions include the bus arbiter and the interrupt logic control. Figure 31-9.
Architecture www.ti.com 31.2.7.3 Bus Arbiter The EMAC control module bus arbiter operates transparently to the rest of the system. It is used: • To arbitrate between the CPU and EMAC buses for access to internal descriptor memory. • To arbitrate between internal EMAC buses for access to system memory. 31.2.8 MDIO Module The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet Media Access Controller (EMAC).
Architecture www.ti.com 31.2.8.1.1 MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of the VCLK3 peripheral clock in the EMAC control module. The MDIO clock is specified to run up to 2.5 MHz, although typical operation would be 1.0 MHz. Since the VCLK3 peripheral clock frequency is configurable, the application software or driver controls the divide-down amount. See the device datasheet for peripheral clock speed specifications. 31.2.8.1.
Architecture www.ti.com 31.2.8.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to interrogate and control an Ethernet PHY, using a shared two-wired bus. It separately performs autodetection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses.
Architecture www.ti.com 31.2.8.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL). 2. Enable the MDIO module by setting the ENABLE bit in CONTROL. 3.
Architecture www.ti.com 31.2.8.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY control registers.
Architecture www.ti.com 31.2.9 EMAC Module This section discusses the architecture and basic function of the EMAC module. 31.2.9.1 EMAC Module Components The EMAC module (Figure 31-11) interfaces to the outside world through the Media Independent Interface (MII) or Reduced Media Independent Interface (RMII). The interface between the EMAC module and the system core is provided through the EMAC control module.
Architecture www.ti.com 31.2.9.1.3 MAC Receiver The MAC receiver detects and processes incoming network frames, de-frames them, and puts them into the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM. 31.2.9.1.4 Transmit DMA Engine The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to the CPU through the bus arbiter in the EMAC control module. 31.2.9.1.
Architecture www.ti.com Receive operations are initiated by host writes to the appropriate receive channel head descriptor pointer after host initialization and configuration. The SYNC submodule receives packets and strips off the Ethernet related protocol. The packet data is input to the MAC receiver, which checks for address match and processes errors. Accepted packets are then written to the receive FIFO in bursts of 64-byte cells. The receive DMA controller then writes the packet data to memory.
Architecture www.ti.com 31.2.10.1.3 Receive Flow Control When enabled and triggered, receive flow control is initiated to limit the EMAC from further frame reception. Two forms of receive buffer flow control are available: • Collision-based flow control for half-duplex mode • IEEE 802.3x pause frames flow control for full-duplex mode In either case, receive flow control prevents frame reception by issuing the flow control appropriate for the current mode of operation.
Architecture • www.ti.com The 32-bit frame-check sequence (CRC word). All quantities are hexadecimal and are transmitted most-significant byte first. The least-significant bit (LSB) is transferred first in each byte. If the RXBUFFERFLOWEN bit in MACCONTROL is cleared to 0 while the pause time is nonzero, then the pause time is cleared to 0 and a zero count pause frame is sent. 31.2.10.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled).
Architecture www.ti.com 31.2.10.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.
Architecture www.ti.com 31.2.11 Packet Receive Operation 31.2.11.1 Receive DMA Host Configuration To • • • • • • • • • • configure the receive DMA for operation the host must: Initialize the receive addresses. Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. Write the MAC address hash n registers (MACHASH1 and MACHASH2), if multicast addressing is desired.
Architecture www.ti.com 31.2.11.4 Hardware Receive QOS Support Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier format and the associated Tag Control Information (TCI) format priority field. When the incoming frame length/type value is equal to 81.00h, the EMAC recognizes the frame as an Ethernet Encoded Tag Protocol Type. The two octets immediately following the protocol type contain the 16-bit TCI field.
Architecture www.ti.com 31.2.11.7 Receive Frame Classification Received frames are proper (good) frames, if they are between 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRC errors. Received frames are long frames, if their frame count exceeds the value in RXMAXLEN. The RXMAXLEN reset (default) value is 5EEh (1518 in decimal). Long received frames are either oversized or jabber frames.
Architecture www.ti.com Table 31-7. Receive Frame Treatment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN 0 0 X X X Receive Frame Treatment No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred to promiscuous channel. 0 1 0 1 0 Proper data and control frames transferred to promiscuous channel. 0 1 0 1 1 Proper/undersized data and control frames transferred to promiscuous channel.
Architecture www.ti.com 31.2.11.
Architecture www.ti.com 31.2.12 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7. 31.2.12.
Architecture www.ti.com 31.2.13 Receive and Transmit Latency The transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH (configurable through the FIFO control register) cells, or a complete packet, are available in the FIFO. Transmit underrun cannot occur for packet sizes of TXCELLTHRESH times 64 bytes (or less).
Architecture www.ti.com 31.2.15 Reset Considerations 31.2.15.1 Software Reset Considerations The peripheral clock is controlled by the Global Clock Module (GCM), while the reset to the EMAC, MDIO and EMAC control module is controlled by the system module. See the "Architecture" chapter of the Technical Reference Manual for more on how to enable or disable the peripheral clock to the EMAC, MDIO and EMAC control module.
Architecture www.ti.com 31.2.16 Initialization 31.2.16.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral becomes enabled as soon as the system reset is released, and the EMAC peripheral registers are set to their default values. The application software can configure the EMAC peripheral registers as required. 31.2.16.2 EMAC Control Module Initialization The EMAC control module is used for global interrupt enables and to pace interrupts using 1ms time windows.
Architecture www.ti.com 31.2.16.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the work in developing an application or device driver for Ethernet is programming this module.
Architecture www.ti.com 31.2.17 Interrupt Support 31.2.17.
Architecture www.ti.com When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing the packet's last buffer descriptor address to the appropriate channel queue's receive completion pointer located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt mask, regardless of the value written.
Architecture www.ti.com The receive host error conditions are: • Ownership bit not set in input buffer • Zero buffer pointer The application software must acknowledge the EMAC control module after receiving host error interrupts by writing the appropriate C0MISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See Section 31.5.12 for the acknowledge key values. 31.2.17.1.
Architecture www.ti.com 31.2.17.2.2 User Access Completion Interrupt When the GO bit in one of the MDIO register USERACCESS0 transitions from 1 to 0 (indicating completion of a user access) and the corresponding USERINTMASKSET bit in the MDIO user command complete interrupt mask set register (USERINTMASKSET) corresponding to USERACCESS0 is set, a user access completion interrupt (USERINT) is asserted.
Architecture www.ti.com 31.2.18 Power Management Each of the three main components of the EMAC peripheral can be placed in a reduced-power mode to conserve power during periods of low activity. The peripheral clock to the EMAC peripheral is controlled by the processor Global Clock Module (GCM). The GCM allows the application to enable or disable the peripheral clock to the EMAC peripheral.
EMAC Control Module Registers www.ti.com 31.3 EMAC Control Module Registers Table 31-10 lists the memory-mapped registers for the EMAC control module. The base address for these registers is FCF7 8800h. Table 31-10. EMAC Control Module Registers Offset Acronym Register Description 0h REVID EMAC Control Module Revision ID Register Section 31.3.1 4h SOFTRESET EMAC Control Module Software Reset Register Section 31.3.2 Ch INTCONTROL EMAC Control Module Interrupt Control Register Section 31.3.
EMAC Control Module Registers www.ti.com 31.3.1 EMAC Control Module Revision ID Register (REVID) The EMAC control module revision ID register (REVID) is shown in Figure 31-12 and described in Table 31-11. Figure 31-12. EMAC Control Module Revision ID Register (REVID) (offset = 00h) 31 0 REV R-4EC8 0100h LEGEND: R = Read only; -n = value after reset Table 31-11.
EMAC Control Module Registers www.ti.com 31.3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) The EMAC control module interrupt control register (INTCONTROL) is shown in Figure 31-14 and described in Table 31-13. The settings in the INTCONTROL register are used in conjunction with the CnRXIMAX and CnTXIMAX registers. Figure 31-14.
EMAC Control Module Registers www.ti.com 31.3.4 EMAC Control Module Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN) The EMAC control module receive threshold interrupt enable register (C0RXTHRESHEN) is shown in Figure 31-15 and described in Table 31-14. Figure 31-15.
EMAC Control Module Registers www.ti.com 31.3.5 EMAC Control Module Receive Interrupt Enable Registers (C0RXEN) The EMAC control module receive interrupt enable register (C0RXEN) is shown in Figure 31-16 and described in Table 31-15 Figure 31-16.
EMAC Control Module Registers www.ti.com 31.3.6 EMAC Control Module Transmit Interrupt Enable Registers (C0TXEN) The EMAC control module transmit interrupt enable register (C0TXEN) is shown in Figure 31-17 and described in Table 31-16 Figure 31-17.
EMAC Control Module Registers www.ti.com 31.3.7 EMAC Control Module Miscellaneous Interrupt Enable Registers (C0MISCEN) The EMAC control module miscellaneous interrupt enable register (C0MISCEN) is shown in Figure 31-18 and described in Table 31-17 Figure 31-18.
EMAC Control Module Registers www.ti.com 31.3.8 EMAC Control Module Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT) The EMAC control module receive threshold interrupt status register (C0RXTHRESHSTAT) is shown in Figure 31-19 and described in Table 31-18 Figure 31-19.
EMAC Control Module Registers www.ti.com 31.3.9 EMAC Control Module Receive Interrupt Status Registers (C0RXSTAT) The EMAC control module receive interrupt status register (C0RXSTAT) is shown in Figure 31-20 and described in Table 31-19 Figure 31-20.
EMAC Control Module Registers www.ti.com 31.3.10 EMAC Control Module Transmit Interrupt Status Registers (C0TXSTAT) The EMAC control module transmit interrupt status register (C0TXSTAT) is shown in Figure 31-21 and described in Table 31-20 Figure 31-21.
EMAC Control Module Registers www.ti.com 31.3.11 EMAC Control Module Miscellaneous Interrupt Status Registers (C0MISCSTAT) The EMAC control module miscellaneous interrupt status register (C0MISCSTAT) is shown in Figure 3122 and described in Table 31-21 Figure 31-22.
EMAC Control Module Registers www.ti.com 31.3.12 EMAC Control Module Receive Interrupts Per Millisecond Registers (C0RXIMAX) The EMAC control module receive interrupts per millisecond register (C0RXIMAX) is shown in Figure 3123 and described in Table 31-22 Figure 31-23. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX) (offset = 70h) 31 16 Reserved R-0 15 6 5 0 Reserved RXIMAX R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 31-22.
EMAC Control Module Registers www.ti.com 31.3.13 EMAC Control Module Transmit Interrupts Per Millisecond Registers (C0TXIMAX) The EMAC control module transmit interrupts per millisecond register (C0TXIMAX) is shown in Figure 31-24 and described in Table 31-23 Figure 31-24. EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) (offset = 74h) 31 16 Reserved R-0 15 6 5 0 Reserved TXIMAX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-23.
MDIO Registers www.ti.com 31.4 MDIO Registers Table 31-24 lists the memory-mapped registers for the MDIO module. The base address for these registers is FCF7 8900h. Table 31-24. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description 0h REVID MDIO Revision ID Register Section 31.4.1 Section 4h CONTROL MDIO Control Register Section 31.4.2 8h ALIVE PHY Alive Status register Section 31.4.3 Ch LINK PHY Link Status Register Section 31.4.
MDIO Registers www.ti.com 31.4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 31-26 and described in Table 31-26. Figure 31-26.
MDIO Registers www.ti.com 31.4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 31-27 and described in Table 31-27. Figure 31-27. PHY Acknowledge Status Register (ALIVE) (offset = 08h) 31 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset Table 31-27. PHY Acknowledge Status Register (ALIVE) Field Descriptions Bit Field 31-0 ALIVE Value Description MDIO Alive bits.
MDIO Registers www.ti.com 31.4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 31-29 and described in Table 31-29. Figure 31-29.
MDIO Registers www.ti.com 31.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 31-30 and described in Table 31-30. Figure 31-30.
MDIO Registers www.ti.com 31.4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 31-31 and described in Table 31-31. Figure 31-31.
MDIO Registers www.ti.com 31.4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 31-32 and described in Table 31-32. Figure 31-32.
MDIO Registers www.ti.com 31.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 31-33 and described in Table 31-33. Figure 31-33.
MDIO Registers www.ti.com 31.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 31-34 and described in Table 31-34. Figure 31-34.
MDIO Registers www.ti.com 31.4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 31-35 and described in Table 3135. Figure 31-35. MDIO User Access Register 0 (USERACCESS0) (offset = 80h) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset Table 31-35.
MDIO Registers www.ti.com 31.4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 31-36 and described in Table 31-36. Figure 31-36. MDIO User PHY Select Register 0 (USERPHYSEL0) (offset = 84h) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-36.
MDIO Registers www.ti.com 31.4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 31-37 and described in Table 3137. Figure 31-37. MDIO User Access Register 1 (USERACCESS1) (offset = 88h) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset Table 31-37.
MDIO Registers www.ti.com 31.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 31-38 and described in Table 31-38. Figure 31-38. MDIO User PHY Select Register 1 (USERPHYSEL1) (offset = 8Ch) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-38.
EMAC Module Registers www.ti.com 31.5 EMAC Module Registers Table 31-39 lists the memory-mapped registers for the EMAC. The base address for these registers is FCF7 8000h. Table 31-39. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Section 0h TXREVID Transmit Revision ID Register Section 31.5.1 4h TXCONTROL Transmit Control Register Section 31.5.2 8h TXTEARDOWN Transmit Teardown Register Section 31.5.
EMAC Module Registers www.ti.com Table 31-39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 31.5.30 168h EMCONTROL Emulation Control Register Section 31.5.31 16Ch FIFOCONTROL FIFO Control Register Section 31.5.32 170h MACCONFIG MAC Configuration Register Section 31.5.33 174h SOFTRESET Soft Reset Register Section 31.5.
EMAC Module Registers www.ti.com Table 31-39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 200h RXGOODFRAMES Good Receive Frames Register Section 31.5.50.1 204h RXBCASTFRAMES Broadcast Receive Frames Register Section 31.5.50.2 208h RXMCASTFRAMES Multicast Receive Frames Register Section 31.5.50.3 20Ch RXPAUSEFRAMES Pause Receive Frames Register Section 31.5.50.
EMAC Module Registers www.ti.com 31.5.1 Transmit Revision ID Register (TXREVID) The transmit revision ID register (TXREVID) is shown in Figure 31-39 and described in Table 31-40. Figure 31-39. Transmit Revision ID Register (TXREVID) (offset = 00h) 31 0 TXREV R-4EC0 020Dh LEGEND: R = Read only; -n = value after reset Table 31-40. Transmit Revision ID Register (TXREVID) Field Descriptions Bit 31-0 Field Value TXREV Description Transmit module revision 4EC0 020Dh Current transmit revision value 31.
EMAC Module Registers www.ti.com 31.5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 31-41 and described in Table 31-42. Figure 31-41. Transmit Teardown Register (TXTEARDOWN) (offset = 08h) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-42.
EMAC Module Registers www.ti.com 31.5.5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 31-43 and described in Table 31-44. Figure 31-43. Receive Control Register (RXCONTROL) (offset = 14h) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-44.
EMAC Module Registers www.ti.com 31.5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 31-45 and described in Table 31-46. Figure 31-45.
EMAC Module Registers www.ti.com 31.5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 31-46 and described in Table 31-47. Figure 31-46.
EMAC Module Registers www.ti.com 31.5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 31-47 and described in Table 31-48. Figure 31-47.
EMAC Module Registers www.ti.com 31.5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 31-48 and described in Table 31-49. Figure 31-48.
EMAC Module Registers www.ti.com 31.5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 31-49 and described in Table 31-50. Figure 31-49. MAC Input Vector Register (MACINVECTOR) (offset = 90h) 31 28 27 26 25 24 Reserved STATPEND HOSTPEND LINKINT0 USERINT0 R-0 R-0 R-0 R-0 R-0 15 8 23 16 TXPEND R-0 7 0 RXTHRESHPEND RXPEND R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 31-50.
EMAC Module Registers www.ti.com 31.5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) The MAC end of interrupt vector register (MACEOIVECTOR) is shown in Figure 31-50 and described in Table 31-51. Figure 31-50. MAC End Of Interrupt Vector Register (MACEOIVECTOR) (offset = 94h) 31 16 Reserved R-0 15 5 4 0 Reserved INTVECT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-51.
EMAC Module Registers www.ti.com 31.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 31-51 and described in Table 31-52. Figure 31-51.
EMAC Module Registers www.ti.com 31.5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 31-52 and described in Table 31-53. Figure 31-52.
EMAC Module Registers www.ti.com 31.5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 31-53 and described in Table 31-54. Figure 31-53.
EMAC Module Registers www.ti.com 31.5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 31-54 and described in Table 31-55. Figure 31-54.
EMAC Module Registers www.ti.com 31.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 31-55 and described in Table 31-56. Figure 31-55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) (offset = B0h) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTPEND STATPEND R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 31-56.
EMAC Module Registers www.ti.com 31.5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 31-57 and described in Table 31-58. Figure 31-57. MAC Interrupt Mask Set Register (MACINTMASKSET) (offset = B8h) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTMASK STATMASK R-0 R/W1S-0 R/W1S-0 LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset Table 31-58.
EMAC Module Registers www.ti.com 31.5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 31-59 and described in Table 31-60. Figure 31-59.
EMAC Module Registers www.ti.com Table 31-60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field 22 RXCEFEN 21 Reserved 18-16 RXPROMCH 13 Reserved Reserved 10-8 RXBROADCH 7-6 5 4-3 1616 0 Frames containing errors are filtered. 1 Frames containing errors are transferred to memory. Receive copy all frames enable bit.
EMAC Module Registers www.ti.com Table 31-60.
EMAC Module Registers www.ti.com 31.5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 31-61 and described in Table 31-62. Figure 31-61.
EMAC Module Registers www.ti.com 31.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 31-63 and described in Table 31-64. Figure 31-63. Receive Buffer Offset Register (RXBUFFEROFFSET) (offset = 110h) 31 16 Reserved R-0 15 0 RXBUFFEROFFSET R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-64.
EMAC Module Registers www.ti.com 31.5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESHRX7FLOWTHRESH) The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in Figure 31-65 and described in Table 31-66. Figure 31-65. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) (offset = 120h-13Ch) 31 16 Reserved R-0 15 8 7 0 Reserved RXnFLOWTHRESH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-66.
EMAC Module Registers www.ti.com 31.5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 31-67 and described in Table 31-68. Figure 31-67.
EMAC Module Registers www.ti.com Table 31-68. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit 4 3 Field Reserved 1 LOOPBACK 1622 Description Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode, regardless of this bit setting. The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory.
EMAC Module Registers www.ti.com 31.5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 31-68 and described in Table 31-69. Figure 31-68.
EMAC Module Registers www.ti.com Table 31-69. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit 15-12 11 10-8 7-3 2 1 0 1624 Field Value RXERRCODE Reserved Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host error interrupts require hardware reset in order to recover.
EMAC Module Registers www.ti.com 31.5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 31-69 and described in Table 31-70. Figure 31-69. Emulation Control Register (EMCONTROL) (offset = 168h) 31 16 Reserved R-0 15 1 0 Reserved 2 SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-70.
EMAC Module Registers www.ti.com 31.5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 31-71 and described in Table 31-72. Figure 31-71. MAC Configuration Register (MACCONFIG) (offset = 170h) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-3h R-3h 15 8 7 0 ADDRESSTYPE MACCFIG R-2h R-2h LEGEND: R = Read only; -n = value after reset Table 31-72.
EMAC Module Registers www.ti.com 31.5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 31-73 and described in Table 31-74. Figure 31-73. MAC Source Address Low Bytes Register (MACSRCADDRLO) (offset = 1D0h) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31-74.
EMAC Module Registers www.ti.com 31.5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
EMAC Module Registers www.ti.com 31.5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 31-77 and described in Table 31-78. Figure 31-77. Back Off Random Number Generator Test Register (BOFFTEST) (offset = 1E0h) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 31-78.
EMAC Module Registers www.ti.com 31.5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 31-79 and described in Table 31-80. Figure 31-79. Receive Pause Timer Register (RXPAUSE) (offset = 1E8h) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 31-80.
EMAC Module Registers www.ti.com 31.5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in receive address matching (MACADDRLO), is shown in Figure 31-81 and described in Table 31-82. Figure 31-81.
EMAC Module Registers www.ti.com 31.5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register used in receive address matching (MACADDRHI) is shown in Figure 31-82 and described in Table 31-83. Figure 31-82. MAC Address High Bytes Register (MACADDRHI) (offset = 504h) 31 24 23 16 MACADDR2 MACADDR3 R/W-x R/W-x 15 8 7 0 MACADDR4 MACADDR5 R/W-x R/W-x LEGEND: R/W = Read/Write; -x = value is indeterminate after reset Table 31-83.
EMAC Module Registers www.ti.com 31.5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 31-84 and described in Table 31-85. Figure 31-84. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) (offset = 600h-61Ch) 31 0 TXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 31-85.
EMAC Module Registers www.ti.com 31.5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 31-86 and described in Table 31-87. Figure 31-86. Transmit Channel n Completion Pointer Register (TXnCP) (offset = 640h-65Ch) 31 0 TXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 31-87.
EMAC Module Registers www.ti.com 31.5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers (see Figure 31-88) are write-to-decrement. The value written is subtracted from the register value with the result stored in the register.
EMAC Module Registers www.ti.com 31.5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) (offset = 20Ch) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Contained the length/type field value 88.
EMAC Module Registers www.ti.com 31.5.50.7 Receive Oversized Frames Register (RXOVERSIZED) (offset = 218h) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode • Was greater than RXMAXLEN in bytes • Had no CRC error, alignment error, or code error See Section 31.2.6.
EMAC Module Registers www.ti.
EMAC Module Registers www.ti.com 31.5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) (offset = 238h) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: • Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only • Was of any length • Had no late or excessive collisions, no carrier loss, and no underrun 31.5.50.
EMAC Module Registers www.ti.com 31.5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) (offset = 24Ch) The total number of frames transmitted on the EMAC that experienced exactly one collision. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • Had no carrier loss and no underrun • Experienced one collision before successful transmission. The collision was not late.
EMAC Module Registers www.ti.com 31.5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) (offset = 260h) The total number of frames on the EMAC that experienced carrier loss.
EMAC Module Registers www.ti.com 31.5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) (offset = 274h) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC.
EMAC Module Registers www.ti.com 31.5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) (offset = 284h) The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun.
Chapter 32 SPNU562 – May 2014 Enhanced Capture (eCAP) Module The enhanced Capture (eCAP) module is essential in systems where accurate timing of external events is important. This microcontroller implements 6 instances of the eCAP module. Topic 32.1 32.2 32.3 32.4 32.5 1644 ........................................................................................................................... Introduction ................................................................................................
Introduction www.ti.com 32.1 Introduction Uses for eCAP include: • Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors) • Elapsed time measurements between position sensor pulses • Period and duty cycle measurements of pulse train signals • Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors 32.1.
Basic Operation www.ti.com 32.2 Basic Operation 32.2.1 Capture and APWM Operating Mode You can use the eCAP module resources to implement a single-channel PWM generator (with 32 bit capabilities) when it is not being used for input captures. The counter operates in count-up mode, providing a time-base for asymmetrical pulse width modulation (PWM) waveforms.
Basic Operation www.ti.com 32.2.2 Capture Mode Description Figure 32-2 shows the various components that implement the capture function. Figure 32-2.
Basic Operation www.ti.com Figure 32-3. Event Prescale Control Event prescaler 0 PSout 1 By−pass ECAPx pin (from GPIO) /n 5 ECCTL1[EVTPS] prescaler [5 bits] (counter) A When a prescale value of 1 is chosen (ECCTL1[13:9] = 0,0,0,0,0 ), the input capture signal by-passes the prescale logic completely. Figure 32-4. Prescale Function Waveforms ECAPx PSout div 2 PSout div 4 PSout div 6 PSout div 8 PSout div 10 32.2.2.
Basic Operation www.ti.com 32.2.2.3 • • • Continuous/One-Shot Control The Mod4 (2 bit) counter is incremented via edge qualified events (CEVT1-CEVT4). The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped. A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4 counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.
Basic Operation www.ti.com Figure 32-6. Counter and Synchronization Block SYNC ECCTL2[SWSYNC] ECCTL2[SYNCOSEL] SYNCI CTR=PRD Disable Disable ECCTL2[SYNCI_EN] SYNCO Sync out select CTRPHS LD_CTRPHS RST Delta−mode TSCTR (counter 32b) SYSCLK CLK OVF CTR−OVF CTR[31−0] 32.2.2.5 CAP1-CAP4 Registers These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (that is, capture a time-stamp) when their respective LD inputs are strobed.
Basic Operation www.ti.com Note: The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode (ECCTL2[CAP_APWM == 0]). The CTR_PRD and CTR_CMP flags are only valid in APWM mode (ECCTL2[CAP_APWM == 1]). CNTOVF flag is valid in both modes. Figure 32-7.
Basic Operation www.ti.com 32.2.2.8 APWM Mode Operation Main operating highlights of the APWM section: • The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators. • When CAP1/2 registers are not used in capture mode, their contents can be used as Period and Compare values in APWM mode. • Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4).
Application of the ECAP Module www.ti.com 32.3 Application of the ECAP Module The following sections will provide Applications examples and code snippets to show how to configure and operate the eCAP module. For clarity and ease of use, the examples use the eCAP “C” header files. Below are useful #defines which will help in the understanding of the examples.
Application of the ECAP Module www.ti.com 32.3.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger Figure 32-9 shows an example of continuous capture operation (Mod4 counter wraps around). In this figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this gives period (and frequency) information. On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the next state.
Application of the ECAP Module www.ti.com 32.3.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger // Code snippet for CAP mode Absolute Time, Rising edge trigger // Initialization Time //======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP2POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP4POL = EC_RISING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE; ECap1Regs.ECCTL1.bit.
Application of the ECAP Module www.ti.com 32.3.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger In Figure 32-10, the eCAP operating mode is almost the same as in the previous section except capture events are qualified as either rising or falling edge, this now gives both period and duty cycle information: Period1 = t3 – t1, Period2 = t5 – t3, …etc. Duty Cycle1 (on-time %) = (t2 – t1) / Period1 x 100%, etc. Duty Cycle1 (off-time %) = (t3 – t2) / Period1 x 100%, etc.
Application of the ECAP Module www.ti.com 32.3.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Triggers // Code snippet for CAP mode Absolute Time, Rising & Falling edge triggers // Initialization Time //======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP2POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP4POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE; ECap1Regs.ECCTL1.bit.
Application of the ECAP Module www.ti.com 32.3.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger Figure 32-11 shows an example of how the eCAP module can be used to collect Delta timing data from pulse train waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4 counter wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event. Here Capture events are qualified as Rising edge only.
Application of the ECAP Module www.ti.com 32.3.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger // Code snippet for CAP mode Delta Time, Rising edge trigger // Initialization Time //======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP2POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP4POL = EC_RISING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_DELTA_MODE; ECap1Regs.ECCTL1.bit.
Application of the ECAP Module www.ti.com 32.3.
Application of the ECAP Module www.ti.com 32.3.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers // Code snippet for CAP mode Delta Time, Rising and Falling edge triggers // Initialization Time //======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP2POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP4POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_DELTA_MODE; ECap1Regs.ECCTL1.bit.
Application of the APWM Mode www.ti.com 32.4 Application of the APWM Mode In this section, the eCAP module is configured to operate as a PWM generator. Here a very simple single channel PWM waveform is generated from output pin APWMx. The PWM polarity is active high, which means that the compare value (CAP2 reg is now a compare register) represents the on-time (high level) of the period. Alternatively, if the APWMPOL bit is configured for active low, then the compare value represents the off-time.
eCAP Registers www.ti.com 32.5 eCAP Registers Table 32-1 shows the eCAP module control and status registers. The base address for the control registers is FCF7 9300h for eCAP1, FCF7 9400h for eCAP2, FCF7 9500h for eCAP3, FCF7 9600h for eCAP4, FCF7 9700h for eCAP5, and FCF7 9800h for eCAP6. Table 32-1. ECAP Control and Status Registers Address Offset Acronym 00h TSCTR 04h CTRPHS 08h CAP1 0Ch Description Section Time-Stamp Counter Register Section 32.5.
eCAP Registers www.ti.com 32.5.3 Capture-1 Register (CAP1) NOTE: In APWM mode, writing to CAP1/CAP2 active registers also writes the same value to the corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes the shadow mode. Figure 32-16. Capture-1 Register (CAP1) [offset = 08h] 31 0 CAP1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32-4.
eCAP Registers www.ti.com 32.5.5 Capture-3 Register (CAP3) Figure 32-18. Capture-3 Register (CAP3) [offset = 10h] 31 0 CAP3 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32-6. Capture-3 Register (CAP3) Field Descriptions Bits Field Description 31-0 CAP3 In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. You update the PWM period value through this register. In this mode, CAP3 (APRD) shadows CAP1. 32.5.
eCAP Registers www.ti.com 32.5.7 ECAP Control Register 2 (ECCTL2) Figure 32-20. ECAP Control Register 2 (ECCTL2) [offset = 2Ah] 15 11 7 10 9 8 Reserved APWMPOL CAP_APWM SWSYNC R-0 R/W-0 R/W-0 R/W-0 2 1 0 6 5 4 3 SYNCO_SEL SYNCI_EN TSCTRSTOP REARM STOP_WRAP CONT_ONESHT R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32-8.
eCAP Registers www.ti.com Table 32-8. ECAP Control Register 2 (ECCTL2) Field Descriptions (continued) Bits 3 2-1 Field Value REARM Description One-Shot Re-Arming Control, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0 Has no effect (reading always returns a 0) 1 Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero 2) Unfreezes the Mod4 counter 3) Enables capture register loads STOP_WRAP Stop value for one-shot mode.
eCAP Registers www.ti.com 32.5.8 ECAP Control Regiser 1 (ECCTL1) Figure 32-21. ECAP Control Register 1 (ECCTL1) [offset = 28h] 15 14 FREE SOFT 13 PRESCALE 9 CAPLDEN 8 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 CTRRST4 CAP4POL CTRRST3 CAP3POL CTRRST2 CAP2POL CTRRST1 CAP1POL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32-9.
eCAP Registers www.ti.com Table 32-9.
eCAP Registers www.ti.com 32.5.9 ECAP Interrupt Flag Register (ECFLG) Figure 32-22. ECAP Interrupt Flag Register (ECFLG) [offset = 2Eh] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 CTR_CMP CTR_PRD CTROVF CEVT4 CETV3 CEVT2 CETV1 INT R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32-10.
eCAP Registers www.ti.com 32.5.10 ECAP Interrupt Enable Register (ECEINT) The interrupt enable bits block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers.
eCAP Registers www.ti.com 32.5.11 ECAP Interrupt Forcing Register (ECFRC) Figure 32-24. ECAP Interrupt Forcing Register (ECFRC) [offset = 32h] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 CTR_CMP CTR_PRD CTROVF CEVT4 CETV3 CETV2 CETV1 reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32-12.
eCAP Registers www.ti.com 32.5.12 ECAP Interrupt Clear Register (ECCLR) Figure 32-25. ECAP Interrupt Clear Register (ECCLR) [offset = 30h] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 CTR_CMP CTR_PRD CTROVF CEVT4 CETV3 CETV2 CETV1 INT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32-13.
Chapter 33 SPNU562 – May 2014 Enhanced QEP (eQEP) Module The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine for use in a high-performance motion and position-control system. This microcontroller implements 2 instances of the eQEP module. Topic 33.1 33.2 33.3 1674 ................................................................................................
Introduction www.ti.com 33.1 Introduction A single track of slots patterns the periphery of an incremental encoder disk, as shown in Figure 33-1. These slots create an alternating pattern of dark and light lines. The disk count is defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an absolute position.
Introduction www.ti.com Quadrature encoders from different manufacturers come with two forms of index pulse (gated index pulse or ungated index pulse) as shown in Figure 33-3. A nonstandard form of index pulse is ungated. In the ungated configuration, the index edges are not necessarily coincident with A and B signals. The gated index pulse is aligned to any of the four quadrature edges and width of the index pulse and can be equal to a quarter, half, or full period of the quadrature signal. Figure 33-3.
Basic Operation www.ti.com The encoder count (position) is read once during each unit time event. The quantity [x(k) - x(k-1)] is formed by subtracting the previous reading from the current reading. Then the velocity estimate is computed by multiplying by the known constant 1/T (where T is the constant time between unit time events and is known in advance). Estimation based on Equation 66 has an inherent accuracy limit directly related to the resolution of the position sensor and the unit time period T.
Basic Operation www.ti.com 33.2.2 Functional Description The eQEP peripheral contains the following major functional units (as shown in Figure 33-4): • Programmable input qualification for each pin (part of the GPIO MUX) • Quadrature decoder unit (QDU) • Position counter and control unit for position measurement (PCCU) • Quadrature edge-capture unit for low-speed measurement (QCAP) • Unit time base for speed/frequency measurement (UTIME) • Watchdog timer for detecting stalls (QWDOG) Figure 33-4.
Basic Operation www.ti.com 33.2.2.1 eQEP Memory Map Table 33-1 lists the registers with their memory locations, sizes, and reset values. Table 33-1.
Basic Operation www.ti.com 33.2.2.2 Quadrature Decoder Unit (QDU) Figure 33-5 shows a functional block diagram of the QDU. Figure 33-5.
Basic Operation www.ti.com 33.2.2.2.1.1 Quadrature Count Mode The quadrature decoder generates the direction and clock to the position counter in quadrature count mode. Direction Decoding— The direction decoding logic of the eQEP circuit determines which one of the sequences (QEPA, QEPB) is the leading sequence and accordingly updates the direction information in QEPSTS[QDF] bit. Table 33-2 and Figure 33-6 show the direction decoding logic in truth table and state machine form.
Basic Operation www.ti.com Figure 33-7. Quadrature-clock and Direction Decoding QA QB QCLK QDIR QPOSCNT +1 +1 +1 +1 +1 +1 +1 −1 −1 −1 −1 −1 −1 −1 −1 −1 −1 −1 +1 +1 +1 −1 −1 −1 −1 −1 −1 −1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 −1 −1 −1 QA QB QCLK QDIR QPOSCNT Phase Error Flag— In normal operating conditions, quadrature inputs QEPA and QEPB will be 90 degrees out of phase.
Basic Operation www.ti.com 33.2.2.2.1.4 Down-Count Mode The counter direction signal is hardwired for a down count and the position counter is used to measure the frequency of the QEPA input. Setting of the QDECCTL[XCR] bit enables clock generation to the position counter on both edges of a QEPA input, thereby increasing the measurement resolution by 2x factor. 33.2.2.2.2 eQEP Input Polarity Selection Each eQEP input can be inverted using QDECCTL[8:5] control bits.
Basic Operation www.ti.com 33.2.2.3.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00) If the index event occurs during the forward movement, then position counter is reset to 0 on the next eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to the value in the QPOSMAX register on the next eQEP clock. First index marker is defined as the quadrature edge following the first index edge.
Basic Operation www.ti.com 33.2.2.3.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01) If the position counter is equal to QPOSMAX, then the position counter is reset to 0 on the next eQEP clock for forward movement and position counter overflow flag is set. If the position counter is equal to ZERO, then the position counter is reset to QPOSMAX on the next QEP clock for reverse movement and position counter underflow flag is set.
Basic Operation www.ti.com 33.2.2.3.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10) If the index event occurs during forward movement, then the position counter is reset to 0 on the next eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to the value in the QPOSMAX register on the next eQEP clock.
Basic Operation www.ti.com Figure 33-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) QA QB QI QCLK QEPSTS:QDF F9D F9F FA1 FA3 FA4 QPOSCNT F9C FA2 FA0 F9E F9C F9A F98 FA5 F9E FA0 FA2 F97 FA4 FA3 FA1 F9F F9D F9B F99 Index interrupt/ index event marker QPOSILAT F9F 0 QEPSTS:QDLF 33.2.2.3.2.2 Strobe Event Latch The position-counter value is latched to the QPOSSLAT register on the rising edge of the strobe input by clearing the QEPCTL[SEL] bit.
Basic Operation www.ti.com 33.2.2.3.3 Position Counter Initialization The position counter can be initialized using following events: • Index event • Strobe event • Software initialization Index Event Initialization (IEI)— The QEPI index input can be used to trigger the initialization of the position counter at the rising or falling edge of the index input.
Basic Operation www.ti.com For example, if QPOSCMP = 2, the position-compare unit generates a position-compare event on 1 to 2 transitions of the eQEP position counter for forward counting direction and on 3 to 2 transitions of the eQEP position counter for reverse counting direction (see Figure 33-13). Section 33.3.14 shows the layout of the eQEP Position-Compare Control Register (QPOSCTL) and describes the QPOSCTL bit fields. Figure 33-13.
Basic Operation www.ti.com 33.2.2.4 eQEP Edge Capture Unit The eQEP peripheral includes an integrated edge capture unit to measure the elapsed time between the unit position events as shown in Figure 33-15.
Basic Operation www.ti.com Figure 33-15. eQEP Edge Capture Unit 16 0xFFFF QEPSTS:COEF 16 QCTMR QCPRD 16 QCAPCTL:CCPS 3 3-bit binary divider x1, 1/2, 1/4..., 1/128 VCLK3 CAPCLK 16 Capture timer control unit (CTCU) QCAPCTL:CEN QCAPCTL:UPPS QCTMRLAT QCPRDLAT 4 QEPSTS:UPEVNT UPEVNT QEPSTS:CDEF 4-bit binary divider x1, 1/2, 1/4...
Basic Operation www.ti.com Figure 33-17.
Basic Operation www.ti.com Parameter Relevant Register to Configure or Read the Information T Unit Period Register (QUPRD) ΔX Incremental Position = QPOSLAT(k) - QPOSLAT(K-1) X Fixed unit position defined by sensor resolution and ZCAPCTL[UPPS] bits ΔT Capture Period Latch (QCPRDLAT) 33.2.3 eQEP Watchdog The eQEP peripheral contains a 16-bit watchdog timer that monitors the quadrature-clock to indicate proper operation of the motion-control system.
Basic Operation www.ti.com 33.2.5 eQEP Interrupt Structure Figure 33-20 shows how the interrupt mechanism works in the EQEP module. Eleven interrupt events (PCE, PHE, QDC, WTO, PCU, PCO, PCR, PCM, SEL, IEL and UTO) can be generated. The interrupt control register (QEINT) is used to enable/disable individual interrupt event sources. The interrupt flag register (QFLG) indicates if any interrupt event has been latched and contains the global interrupt flag bit (INT).
eQEP Registers www.ti.com 33.3 eQEP Registers Table 33-3 lists the registers of the eQEP. The base address for the control registers is FCF7 9900h for eQEP1 and FCF7 9A00h for eQEP2. Table 33-3. eQEP Registers Address Offset Acronym Register Description Section 00h QPOSCNT eQEP Position Counter Register Section 33.3.1 04h QPOSINIT eQEP Position Counter Initialization Register Section 33.3.2 08h QPOSMAX eQEP Maximum Position Count Register Section 33.3.
eQEP Registers www.ti.com 33.3.1 eQEP Position Counter Register (QPOSCNT) Figure 33-21. eQEP Position Counter Register (QPOSCNT) 31 0 QPOSCNT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-4. eQEP Position Counter Register (QPOSCNT) Field Descriptions Bits Name Description 31-0 QPOSCNT This 32-bit position counter register counts up/down on every eQEP pulse based on direction input.
eQEP Registers www.ti.com 33.3.4 eQEP Position-Compare Register (QPOSCMP) Figure 33-24. eQEP Position-Compare Register (QPOSCMP) 31 0 QPOSCMP R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-7. eQEP Position-Compare Register (QPOSCMP) Field Descriptions Bits Name Description 31-0 QPOSCMP The position-compare value in this register is compared with the position counter (QPOSCNT) to generate sync output and/or interrupt on compare match. 33.3.
eQEP Registers www.ti.com 33.3.7 eQEP Position Counter Latch Register (QPOSLAT) Figure 33-27. eQEP Position Counter Latch Register (QPOSLAT) [offset = 18h] 31 0 QPOSLAT R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-10. eQEP Position Counter Latch Register (QPOSLAT) Field Descriptions Bits Name Description 31-0 QPOSLAT The position-counter value is latched into this register on unit time out event. 33.3.8 eQEP Unit Timer Register (QUTMR) Figure 33-28.
eQEP Registers www.ti.com 33.3.10 eQEP Watchdog Period Register (QWDPRD) Figure 33-30. eQEP Watchdog Period Register (QWDPRD) [offset = 26h] 15 0 QWDPRD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-13. eQEP Watchdog Period Register (QWDPRD) Field Description Bits Name Description 15-0 QWDPRD This register contains the time-out count for the eQEP peripheral watch dog timer.
eQEP Registers www.ti.com 33.3.12 eQEP Control Register (QEPCTL) Figure 33-32. eQEP Control Register (QEPCTL) [offset = 2Ah] 15 14 FREE SOFT 13 PCRM 12 SEI IEI R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 11 4 10 3 2 9 8 1 0 SWI SEL IEL QPEN QCLM UTE WDE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-15.
eQEP Registers www.ti.com Table 33-15. eQEP Control Register (QEPCTL) Field Descriptions (continued) Bits 6 Name Value SEL Description Strobe event latch of position counter 0 The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the QDECCTL register.
eQEP Registers www.ti.com 33.3.13 eQEP Decoder Control Register (QDECCTL) Figure 33-33. eQEP Decoder Control Register (QDECCTL) [offset = 28h] 15 14 13 12 11 10 9 8 QSRC SOEN SPSEL XCR SWAP IGATE QAP R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 5 4 7 6 0 QBP QIP QSP Reserved R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-16.
eQEP Registers www.ti.com 33.3.14 eQEP Position-Compare Control Register (QPOSCTL) Figure 33-34. eQEP Position-Compare Control Register (QPOSCTL) [offset = 2Eh] 15 14 13 12 PCSHDW PCLOAD PCPOL PCE 11 PCSPW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 8 0 PCSPW R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-17.
eQEP Registers www.ti.com 33.3.15 eQEP Capture Control Register (QCAPCTL) Figure 33-35. eQEP Capture Control Register (QCAPCTL) [offset = 2Ch] 15 14 7 6 4 3 0 CEN Reserved CCPS UPPS R/W-0 R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-18.
eQEP Registers www.ti.com 33.3.16 eQEP Interrupt Flag Register (QFLG) Figure 33-36. eQEP Interrupt Flag Register (QFLG) [offset = 32h] 15 11 10 9 8 Reserved 12 UTO IEL SEL PCM R-0 R-0 R-0 R-0 R-0 7 6 5 4 3 2 1 0 PCR PCO PCU WTO QDC PHE PCE INT R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-19.
eQEP Registers www.ti.com 33.3.17 eQEP Interrupt Enable Register (QEINT) Figure 33-37. eQEP Interrupt Enable Register (QEINT) [offset = 30h] 15 12 7 11 10 9 8 Reserved UTO IEL SEL PCM R-0 R/W-0 R/W-0 R/W-0 R/W-0 3 2 1 0 6 5 4 PCR PCO PCU WTO QDC QPE PCE Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-20.
eQEP Registers www.ti.com 33.3.18 eQEP Interrupt Force Register (QFRC) Figure 33-38. eQEP Interrupt Force Register (QFRC) [offset = 36h] 15 12 7 11 10 9 8 Reserved UTO IEL SEL PCM R-0 R/W-0 R/W-0 R/W-0 R/W-0 3 2 1 0 6 5 4 PCR PCO PCU WTO QDC PHE PCE Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-21.
eQEP Registers www.ti.com 33.3.19 eQEP Interrupt Clear Register (QCLR) Figure 33-39. eQEP Interrupt Clear Register (QCLR) [offset = 34h] 15 12 7 11 10 9 8 Reserved UTO IEL SEL PCM R-0 R/W-0 R/W-0 R/W-0 R/W-0 3 2 1 0 6 5 4 PCR PCO PCU WTO QDC PHE PCE INT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-22.
eQEP Registers www.ti.com 33.3.20 eQEP Capture Timer Register (QCTMR) Figure 33-40. eQEP Capture Timer Register (QCTMR) [offset = 3Ah] 15 0 QCTMR R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-23. eQEP Capture Time Register (QCTMR) Field Descriptions Bits Name Description 15-0 QCTMR This register provides time base for edge capture unit.
eQEP Registers www.ti.com 33.3.21 eQEP Status Register (QEPSTS) Figure 33-41. eQEP Status Register (QEPSTS) [offset = 38h] 15 8 Reserved R-0 7 6 5 4 3 UPEVNT FIDF QDF QDLF COEF R-1 R-0 R-0 R-0 R/W-1 2 1 0 CDEF FIMF PCEF R/W-1 R/W-1 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-24.
eQEP Registers www.ti.com 33.3.22 eQEP Capture Timer Latch Register (QCTMRLAT) Figure 33-42. eQEP Capture Timer Latch Register (QCTMRLAT) [offset = 3Eh] 15 0 QCTMRLAT R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33-25. eQEP Capture Timer Latch Register (QCTMRLAT) Field Descriptions Bits Name Description 15-0 QCTMRLAT The eQEP capture timer value can be latched into this register on two events viz., unit timeout event, reading the eQEP position counter. 33.3.
Chapter 34 SPNU562 – May 2014 Enhanced Pulse Width Modulator (ePWM) Module The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipments. The features supported by the ePWM make it especially suitable for digital motor control. Topic 34.1 34.2 34.3 34.4 1712 ........................................................................................................................... Introduction .
Introduction www.ti.com 34.1 Introduction An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis.
Introduction www.ti.com Figure 34-1.
Introduction www.ti.com Figure 34-2.
Introduction www.ti.com 34.1.2 Register Mapping The complete ePWM module control and status register set is grouped by submodule as shown in Table 34-1. Each register set is duplicated for each instance of the ePWM module. Table 34-1.
ePWM Submodules www.ti.com Table 34-1. ePWM Module Control and Status Register Set Grouped by Submodule (continued) Privileged Mode Write Only? Description Address Offset (1) Size (x16) Shadow DCFWINDOW 6Eh 1 No No Digital Compare Filter Window Register DCFOFFSETCNT 6Ch 1 No No Digital Compare Filter Offset Counter Register DCCAP 72h 1 Yes No Digital Compare Counter Capture Register DCFWINDOWCNT 70h 1 No No Digital Compare Filter Window Counter Register Name 34.
ePWM Submodules www.ti.com Table 34-2. Submodule Configuration Parameters (continued) Submodule Configuration Parameter or Option PWM-chopper (PC) • • • • Trip-zone (TZ) • Configure the ePWM module to react to one, all, or none of the trip-zone signals or digital compare events. • Specify the tripping action taken when a fault occurs: Create a chopping (carrier) frequency. Pulse width of the first pulse in the chopped pulse train. Duty cycle of the second and subsequent pulses.
ePWM Submodules www.ti.com 34.2.2 Time-Base (TB) Submodule Each ePWM module has its own time-base submodule that determines all of the event timing for the ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work together as a single system. Figure 34-3 illustrates the time-base module's place within the ePWM. Figure 34-3.
ePWM Submodules www.ti.com Figure 34-4 shows the critical signals and registers of the time-base submodule. Table 34-4 provides descriptions of the key signals associated with the time-base submodule. Figure 34-4. Time-Base Submodule Signals and Registers TBPRD Period Shadow TBCTL[PRDLD] TBPRD Period Active TBCTL[SWFSYNC] 16 DCBEVT1.sync (A) CTR = PRD TBCTR[15:0] EPWMxSYNCI 16 CTR = Zero Reset Zero Counter UP/DOWN Mode Dir Load Max CTR_dir CTR_max TBCLK DCAEVT1.
ePWM Submodules www.ti.com Table 34-4. Key Time-Base Signals (continued) Signal Description CTR = CMPB Time-base counter equal to active counter-compare B register (TBCTR = CMPB). This event is generated by the counter-compare submodule and used by the synchronization out logic CTR_dir Time-base counter direction. Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is increasing and low when it is decreasing.
ePWM Submodules www.ti.com Figure 34-5. Time-Base Frequency and Period TPWM 4 PRD 4 4 3 3 2 3 2 1 2 1 0 Z 1 0 0 For Up Count and Down Count TPWM 4 4 TPWM = (TBPRD + 1) x TTBCLK FPWM = 1/ (TPWM) PRD 4 3 3 2 3 2 1 2 1 0 1 Z 0 0 TPWM TPWM 4 3 3 3 2 2 1 3 2 2 1 0 CTR_dir 1 1 0 0 Up For Up and Down Count TPWM = 2 x TBPRD x TTBCLK FPWM = 1 / (TPWM) 4 Down Up Down The memory address of the shadow period register is the same as the active register.
ePWM Submodules www.ti.com The proper procedure for enabling ePWM clocks is as follows: 1. Enable ePWM module clocks using the IOMM control registers for each ePWM module instance 2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module. 3. Configure ePWM modules: prescaler values and ePWM modes. 4. Set TBCLKSYNC = 1. 34.2.2.3.3 Time-Base Counter Synchronization A time-base synchronization scheme connects all of the ePWM modules on a device.
ePWM Submodules www.ti.com Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN] bit is set, then the time-base counter (TBCTR) of the ePWM module will be automatically loaded with the phase register (TBPHS) contents when one of the following conditions occur: • EPWMxSYNCI: Synchronization Input Pulse: The value of the phase register is loaded into the counter register when an input synchronization pulse is detected (TBPHS → TBCTR).
ePWM Submodules www.ti.com Figure 34-7.
ePWM Submodules www.ti.com Figure 34-8. Time-Base Down-Count Mode Waveforms TBCTR[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0x000 EPWMxSYNCI CTR_dir CTR = zero CTR = PRD CNT_max Figure 34-9.
ePWM Submodules www.ti.com Figure 34-10. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event TBCTR[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0x0000 EPWMxSYNCI UP UP UP CTR_dir DOWN DOWN DOWN CTR = zero CTR = PRD CNT_max 34.2.3 Counter-Compare (CC) Submodule Figure 34-11 illustrates the counter-compare submodule within the ePWM. Figure 34-12 shows the basic structure of the counter-compare submodule. Figure 34-11.
ePWM Submodules www.ti.com Figure 34-12. Detailed View of the Counter-Compare Submodule Time Base (TB) Module TBCTR[15:0] 16 CTR = CMPA CMPA[15:0] CTR = PRD CTR =0 Shadow load 16 CMPA Compare A Active Reg. CMPA Compare A Shadow Reg. CMPCTL[LOADAMODE] TBCTR[15:0] Digital comparator A CMPCTL [SHDWAFULL] CMPCTL [SHDWAMODE] Action Qualifier (AQ) Module 16 CTR = CMPB CMPB[15:0] 16 CTR = PRD CTR = 0 Shadow load Digital comparator B CMPB Compare B Active Reg. CMPB Compare B Shadow Reg.
ePWM Submodules www.ti.com Table 34-6. Counter-Compare Submodule Key Signals Signal Description of Event Registers Compared CTR = CMPA Time-base counter equal to the active counter-compare A value TBCTR = CMPA CTR = CMPB Time-base counter equal to the active counter-compare B value TBCTR = CMPB CTR = PRD Time-base counter equal to the active period. Used to load active counter-compare A and B registers from the shadow register TBCTR = TBPRD CTR = ZERO Time-base counter equal to zero.
ePWM Submodules • • www.ti.com Down-count mode: used to generate an asymmetrical PWM waveform. Up-down-count mode: used to generate a symmetrical PWM waveform. To illustrate the operation of the first three modes, the timing diagrams in Figure 34-13 through Figure 3416 show when events are generated and how the EPWMxSYNCI signal interacts. Figure 34-13.
ePWM Submodules www.ti.com Figure 34-15. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On Synchronization Event TBCTR[15:0] 0xFFFF TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR = CMPB CTR = CMPA Figure 34-16.
ePWM Submodules www.ti.com 34.2.4 Action-Qualifier (AQ) Submodule Figure 34-17 shows the action-qualifier (AQ) submodule (see shaded block) in the ePWM system. The action-qualifier submodule has the most important role in waveform construction and PWM generation. It decides which events are converted into various action types, thereby producing the required switched waveforms at the EPWMxA and EPWMxB outputs. Figure 34-17.
ePWM Submodules www.ti.com The action-qualifier submodule is based on event-driven logic. It can be thought of as a programmable cross switch with events at the input and actions at the output, all of which are software controlled via the set of registers shown in Table 34-7. Figure 34-18.
ePWM Submodules • www.ti.com Do Nothing: Keep outputs EPWMxA and EPWMxB at same level as currently set. Although the "Do Nothing" option prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this event can still trigger interrupts and ADC start of conversion. See the Event-trigger Submodule description in Section 34.2.8 for details. Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be configured to generate actions on a given output.
ePWM Submodules www.ti.com 34.2.4.3 Action-Qualifier Event Priority It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case events are assigned a priority by the hardware. The general rule is events occurring later in time have a higher priority and software forced events always have the highest priority. The event priority levels for updown-count mode are shown in Table 34-9. A priority level of 1 is the highest priority and level 7 is the lowest.
ePWM Submodules www.ti.com Table 34-12. Behavior if CMPA/CMPB is Greater than the Period (continued) Counter Mode Compare on Up-Count Event CAD/CBD Down-Count Mode Never occurs. Compare on Down-Count Event CAD/CBD If CMPA/CMPB < TBPRD, the event will occur on a compare match (TBCTR=CMPA or CMPB). If CMPA/CMPB ≥ TBPRD, the event will occur on a period match (TBCTR=TBPRD). Up-Down-Count Mode If CMPA/CMPB < TBPRD and the counter is incrementing, the event occurs on a compare match (TBCTR=CMPA or CMPB).
ePWM Submodules www.ti.com Figure 34-20.
ePWM Submodules www.ti.com Figure 34-21. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB—Active High TBCTR TBPRD value Z P CB CA Z P CB CA Z P Z P CB CA Z P CB CA Z P EPWMxA EPWMxB A PWM period = (TBPRD + 1 ) × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active high (that is, high time duty proportional to CMPA). C Duty modulation for EPWMxB is set by CMPB and is active high (that is, high time duty proportional to CMPB).
ePWM Submodules www.ti.com Figure 34-22. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB—Active Low TBCTR TBPRD value P CA P CA P EPWMxA P CB CB P P EPWMxB A PWM period = (TBPRD + 1 ) × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA). C Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).
ePWM Submodules www.ti.com Example 34-2. Code Sample for Figure 34-22 // Initialization Time // = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.TBPRD = 600; // EPwm1Regs.CMPA.half.CMPA = 350; // EPwm1Regs.CMPB = 200; // EPwm1Regs.TBPHS = 0; // EPwm1Regs.TBCTR = 0; // EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // EPwm1Regs.TBCTL.
ePWM Submodules www.ti.com Example 34-3. Code Sample for Figure 34-23 // Initialization Time // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.TBPRD = 600; // Period = 601 TBCLK counts EPwm1Regs.CMPA.half.CMPA = 200; // Compare A = 200 TBCLK counts EPwm1Regs.CMPB = 400; // Compare B = 400 TBCLK counts EPwm1Regs.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTR = 0; // clear TB counter EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.
ePWM Submodules www.ti.com Figure 34-24. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Active Low TBCTR TBPRD value CA CA CA CA EPWMxA CB CB CB CB EPWMxB A PWM period = 2 x TBPRD × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA). C Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).
ePWM Submodules www.ti.com Figure 34-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Complementary TBCTR TBPRD value CA CA CA CA EPWMxA CB CB CB CB EPWMxB A PWM period = 2 × TBPRD × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low, i.e., low time duty proportional to CMPA C Duty modulation for EPWMxB is set by CMPB and is active high, i.e.
ePWM Submodules www.ti.com Figure 34-26. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active Low TBCTR CA CA CB CB EPWMxA Z P Z P EPWMxB A PWM period = 2 × TBPRD × TBCLK B Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse placement techniques. C Duty modulation for EPWMxA is set by CMPA and CMPB. D Low time duty for EPWMxA is proportional to (CMPA + CMPB).
ePWM Submodules www.ti.com 34.2.5 Dead-Band Generator (DB) Submodule Figure 34-27 illustrates the dead-band submodule within the ePWM module. Figure 34-27.
ePWM Submodules www.ti.com 34.2.5.3 Operational Highlights for the Dead-Band Submodule The following sections provide the operational highlights. The dead-band submodule has two groups of independent selection options as shown in Figure 34-28. • Input Source Selection: The input signals to the dead-band module are the EPWMxA and EPWMxB output signals from the action-qualifier. In this section they will be referred to as EPWMxA In and EPWMxB In.
ePWM Submodules www.ti.com Although all combinations are supported, not all are typical usage modes. Table 34-14 documents some classical dead-band configurations. These modes assume that the DBCTL[IN_MODE] is configured such that EPWMxA In is the source for both falling-edge and rising-edge delay. Enhanced, or non-traditional modes can be achieved by changing the input signal source.
ePWM Submodules www.ti.com Figure 34-29 shows waveforms for typical cases where 0% < duty < 100%. Figure 34-29.
ePWM Submodules www.ti.com The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED) delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is delayed by.
ePWM Submodules www.ti.com 34.2.6 PWM-Chopper (PC) Submodule Figure 34-30 illustrates the PWM-chopper (PC) submodule within the ePWM module. The PWM-chopper submodule allows a high-frequency carrier signal to modulate the PWM waveform generated by the action-qualifier and dead-band submodules. This capability is important if you need pulse transformer-based gate drivers to control the power switching elements. Figure 34-30.
ePWM Submodules www.ti.com Figure 34-31. PWM-Chopper Submodule Operational Details Bypass 0 EPWMxA EPWMxA Start One shot OSHT PWMA_ch 1 Clk Pulse-width VCLK4 /8 PCCTL [OSHTWTH] Divider and duty control PCCTL [OSHTWTH] Pulse-width PCCTL [CHPEN] PSCLK PCCTL[CHPFREQ] PCCTL[CHPDUTY] Clk One shot EPWMxB PWMB_ch 1 OSHT EPWMxB Start Bypass 0 34.2.6.4 Waveforms Figure 34-32 shows simplified waveforms of the chopping action only; one-shot and duty-cycle control are not shown.
ePWM Submodules 34.2.6.4.1 www.ti.com One-Shot Pulse The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or period of the first pulse is given by: T1stpulse = TVCLK3 × 8 × OSHTWTH Where TVCLK3 is the period of the system clock (VCLK3) and OSHTWTH is the four control bits (value from 1 to 16) Figure 34-33 shows the first and subsequent sustaining pulses and Table 34-17 gives the possible pulse width values for a VCLK3 = 100 MHz. Figure 34-33.
ePWM Submodules www.ti.com 34.2.6.4.2 Duty Cycle Control Pulse transformer-based gate drive designs need to comprehend the magnetic properties or characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist the gate drive designer, the duty cycles of the second and subsequent pulses have been made programmable.
ePWM Submodules www.ti.com 34.2.7 Trip-Zone (TZ) Submodule Figure 34-35 shows how the trip-zone (TZ) submodule fits within the ePWM module. Each ePWM module is connected to six TZn signals (TZ1 to TZ6). TZ1 to TZ3 are sourced from the GPIO mux. TZ4 is sourced from a combination of EQEP1ERR and EQEP2ERR signals. TZ5 is connected to the system oscillator or PLL clock fail logic, and TZ6 is sourced from the debug mode halt indication output from the CPU.
ePWM Submodules www.ti.com 34.2.7.2 Controlling and Monitoring the Trip-Zone Submodule The trip-zone submodule operation is controlled and monitored through the following registers: Table 34-18.
ePWM Submodules • • www.ti.com One-Shot (OSHT): When a one-shot trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits is carried out immediately on the EPWMxA and/or EPWMxB output. Table 34-19 lists the possible actions. In addition, the one-shot trip event flag (TZFLG[OST]) is set and a EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and VIM peripheral. The one-shot trip condition must be cleared manually by writing to the TZCLR[OST] bit.
ePWM Submodules www.ti.com Example 34-7. Trip-Zone Configurations Scenario A: A one-shot trip event on TZ1 pulls both EPWM1A, EPWM1B low and also forces EPWM2A and EPWM2B high. • Configure the ePWM1 registers as follows: – TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM1 – TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event. – TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
ePWM Submodules www.ti.com 34.2.7.4 Generating Trip Event Interrupts Figure 34-36 and Figure 34-37 illustrate the trip-zone submodule control and interrupt logic, respectively. DCAEVT1/2 and DCBEVT1/2 signals are described in further detail in Section 34.2.9. Figure 34-36. Trip-Zone Submodule Mode Control Logic TZCTL[TZA, TZ1 TZ2 TZ3 TZB, DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2] DCAEVT1.force DCAEVT2.force DCBEVT1.force DCBEVT2.
ePWM Submodules www.ti.com Figure 34-37. Trip-Zone Submodule Interrupt Logic TZFLG[CBC] TZEINT[CBC] TZFLG[INT] TZCLR[INT] Clear Latch Set Generate Interrupt Pulse EPWMxTZINT (PIE) When Input = 1 Clear Latch Set TZCLR[CBC] Clear Latch Set TZCLR[OST] CBC Force Output Event TZFLG[OST] TZEINT[OST] OST Force Output Event TZFLG[DCAEVT1] TZEINT[DCAEVT1] Clear Latch Set TZCLR[DCAEVT1] DCAEVT1.inter TZFLG[DCAEVT2] TZEINT[DCAEVT2] Clear Latch Set TZCLR[DCAEVT2] DCAEVT2.
ePWM Submodules www.ti.com 34.2.
ePWM Submodules www.ti.com Figure 34-39.
ePWM Submodules www.ti.com The event-trigger submodule monitors various event conditions (the left side inputs to event-trigger submodule shown in Figure 34-40) and can be configured to prescale these events before issuing an Interrupt request or an ADC start of conversion. The event-trigger prescaling logic can issue Interrupt requests and ADC start of conversion at: • Every event • Every second event • Every third event Figure 34-40.
ePWM Submodules www.ti.com Figure 34-41 shows the event-trigger's interrupt generation logic. The interrupt-period (ETPS[INTPRD]) bits specify the number of events required to cause an interrupt pulse to be generated. The choices available are: • Do not generate an interrupt. • Generate an interrupt on every event • Generate an interrupt on every second event • Generate an interrupt on every third event Which event can cause an interrupt is configured by the interrupt selection (ETSEL[INTSEL]) bits.
ePWM Submodules www.ti.com Figure 34-41. Event-Trigger Interrupt Generator ETFLG[INT] ETCLR[INT] Clear Latch Set ETPS[INTCNT] EPWMxINT Generate Interrupt Pulse When Input = 1 1 ETSEL[INTSEL] 0 Clear CNT 2-bit Counter 0 Inc CNT ETSEL[INT] ETPS[INTPRD] ETFRC[INT] 000 001 010 011 100 101 101 111 0 CTR=Zero CTR=PRD CTRU=CMPA CTRD=CMPA CTRU=CMPB CTRD=CMPB Figure 34-42 shows the operation of the event-trigger's start-of-conversion-A (SOCA) pulse generator.
ePWM Submodules www.ti.com Figure 34-43 shows the operation of the event-trigger's start-of-conversion-B (SOCB) pulse generator. The event-trigger's SOCB pulse generator operates the same way as the SOCA. Figure 34-43. Event-Trigger SOCB Pulse Generator ETCLR[SOCB] Clear Latch Set ETFLG[SOCB] ETPS[SOCBCNT] ETSEL[SOCBSEL] Clear CNT Generate SOC Pulse When Input = 1 SOCB 2-bit Counter ETFRC[SOCB] 000 001 010 011 100 101 101 111 Inc CNT ETSEL[SOCB] ETPS[SOCBPRD] A DCBEVT1.
ePWM Submodules www.ti.com 34.2.9.1 Purpose of the Digital Compare Submodule The key functions of the digital compare submodule are: • TZ1, TZ2, and TZ3 inputs generate Digital Compare A High/Low (DCAH, DCAL) and Digital Compare B High/Low (DCBH, DCBL) signals.
ePWM Submodules www.ti.com 34.2.9.3 Operation Highlights of the Digital Compare Submodule The following sections describe the operational highlights and configuration options for the digital compare submodule. 34.2.9.3.1 Digital Compare Events As illustrated in Figure 34-44 earlier in this section, trip zone inputs (TZ1, TZ2, and TZ3) can be selected via the DCTRIPSEL bits to generate the Digital Compare A High and Low (DCAH/L) and Digital Compare B High and Low (DCBH/L) signals.
ePWM Submodules www.ti.com Figure 34-45 and Figure 34-46 show how the DCAEVT1, DCAEVT2, or DCEVTFILT signals are processed to generate the digital compare A event force, interrupt, soc and sync signals. Figure 34-45. DCAEVT1 Event Triggering DCACTL[EVT1SRCSEL] DCACTL[EVT1FRCSYNCSEL] DCEVTFILT 1 DCAEVT1 0 Async 1 Sync DCAEVT1.force 0 TZEINT[DCAEVT1] TBCLK Set Latch Clear DCAEVT1.inter TZFLG[DCAEVT1] TZCLR[DCAEVT1] DCAEVT1.soc DCACTL[EVT1SOCE] DCAEVT1.
ePWM Submodules www.ti.com Figure 34-47 and Figure 34-48 show how the DCBEVT1, DCBEVT2, or DCEVTFILT signals are processed to generate the digital compare B event force, interrupt, soc and sync signals. Figure 34-47. DCBEVT1 Event Triggering DCBCTL[EVT1SRCSEL] DCEVTFILT 1 DCBEVT1 0 DCBCTL[EVT1FRCSYNCSEL] async Sync 1 DCBEVT1.force 0 TBCLK TZEINT[DCBEVT1] set Latch clear TZCLR[DCBEVT1] DCBEVT1.inter TZFLG[DCBEVT1] DCBEVT1.soc DCBCTL[EVT1SOCE] DCBEVT1.
ePWM Submodules www.ti.com 34.2.9.3.2 Event Filtering The DCAEVT1/2 and DCBEVT1/2 events can be filtered via event filtering logic to remove noise by optionally blanking events for a certain period of time. This is useful for cases where the analog comparator outputs may be selected to trigger DCAEVT1/2 and DCBEVT1/2 events, and the blanking logic is used to filter out potential noise on the signal prior to tripping the PWM outputs or generating an interrupt or ADC start-of-conversion.
ePWM Submodules www.ti.com Figure 34-50. Blanking Window Timing Diagram Period TBCLK CTR = PRD or CTR = 0 Offset(n) BLANKWDW Offset(n+1) Window(n) Window(n+1) Offset(n) BLANKWDW Offset(n+1) Window(n) Offset(n) Window(n+1) Offset(n+1) BLANKWDW Window(n+1) Window(n) 34.2.10 Proper Interrupt Initialization Procedure When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to spurious events due to the ePWM registers not being properly initialized.
Application Examples www.ti.com 34.3 Application Examples An ePWM module has all the local resources necessary to operate completely as a standalone module or to operate in synchronization with other identical ePWM modules. 34.3.1 Overview of Multiple Modules Previously in this user's guide, all discussions have described the operation of a single module.
Application Examples www.ti.com Figure 34-52.
Application Examples www.ti.com 34.3.3 Controlling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck. A single ePWM module configured as a master can control two buck stages with the same PWM frequency. If independent frequency control is required for each buck converter, then one ePWM module must be allocated for each converter stage. Figure 34-53 shows four buck stages, each running at independent frequencies.
Application Examples www.ti.com Figure 34-54.
Application Examples www.ti.com Example 34-8. Configuration for Example in Figure 34-54 //===================================================================== // (Note: code for only 3 modules shown) // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 1200; // Period = 1201 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode EPwm1Regs.TBCTL.bit.
Application Examples www.ti.com 34.3.4 Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules remain locked. Figure 34-55 shows such a configuration; Figure 34-56 shows the waveforms generated by the configuration. Figure 34-55. Control of Four Buck Stages.
Application Examples www.ti.com Figure 34-56.
Application Examples www.ti.com Example 34-9. Code Snippet for Configuration in Figure 34-55 //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 600; // Period = 1200 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module EPwm1Regs.CMPCTL.
Application Examples www.ti.com 34.3.5 Controlling Multiple Half H-Bridge (HHB) Converters Topologies that require control of multiple switching elements can also be addressed with these same ePWM modules. It is possible to control a Half-H bridge stage with a single ePWM module. This control can be extended to multiple stages. Figure 34-57 shows control of two synchronized Half-H bridge stages where stage 2 can operate at integer multiple (N) frequencies of stage 1.
Application Examples www.ti.com Figure 34-58.
Application Examples www.ti.com Example 34-10. Code Snippet for Configuration in Figure 34-57 //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 600; // Period = 1200 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.
Application Examples www.ti.com Figure 34-59.
Application Examples www.ti.com Figure 34-60.
Application Examples www.ti.com 34.3.7 Practical Applications Using Phase Control Between PWM Modules So far, none of the examples have made use of the phase register (TBPHS). It has either been set to zero or its value has been a don't care. However, by programming appropriate values into TBPHS, multiple PWM modules can address another class of applications that rely on phase relationship between stages for correct operation.
Application Examples www.ti.com Figure 34-62 shows the associated timing waveforms for this configuration. Here, TBPRD = 600 for both master and slave. For the slave, TBPHS = 200 (200/600 × 360° = 120°). Whenever the master generates a SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCTR register so the slave time-base is always leading the master's time-base by 120°. Figure 34-62.
ePWM Registers www.ti.com 34.4 ePWM Registers Table 34-22 lists the complete ePWM module control and status register set grouped by submodule. Each register set is duplicated for each instance of the ePWM module. The base address for the control registers is FCF7 8C00h for ePWM1, FCF7 8D00h for ePWM2, FCF7 8E00h for ePWM3, FCF7 8F00h for ePWM4, FCF7 9000h for ePWM5, FCF7 9100h for ePWM6, and FCF7 9200h for ePWM7. Table 34-22.
ePWM Registers www.ti.com Table 34-22. ePWM Module Control and Status Register Set Grouped by Submodule (continued) Address Offset Name Description 6Ch DCFOFFSETCNT Digital Compare Filter Offset Counter Register Section 6Eh DCFWINDOW Digital Compare Filter Window Register Section 34.4.8.7 70h DCFWINDOWCNT Digital Compare Filter Window Counter Register Section 34.4.8.10 72h DCCAP Digital Compare Counter Capture Register Section 34.4.8.9 Section 34.4.8.8 34.4.
ePWM Registers www.ti.com 34.4.1.2 Time-Base Control Register (TBCTL) Figure 34-64. Time-Base Control Register (TBCTL) [offset = 00h] 15 14 13 FREE SOFT PHSDIR 12 CLKDIV HSPCLKDIV R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 HSPCLKDIV SWFSYNC R/W-1 R/W-0 4 10 9 8 3 2 1 0 SYNCOSEL PRDLD PHSEN CTRMODE R/W-0 R/W-0 R/W-0 R/W-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-24.
ePWM Registers www.ti.com Table 34-24. Time-Base Control Register (TBCTL) Field Descriptions (continued) Bit 6 Field Value SWFSYNC Description Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00. 5-4 3 SYNCOSEL Synchronization Output Select.
ePWM Registers www.ti.com 34.4.1.3 Time-Base Phase Register (TBPHS) Figure 34-65. Time-Base Phase Register (TBPHS) [offset = 06h] 15 0 TBPHS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-25. Time-Base Phase Register (TBPHS) Field Descriptions Bits Name Description 15-0 TBPHS These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal.
ePWM Registers www.ti.com 34.4.2 Counter-Compare Submodule Registers 34.4.2.1 Counter-Compare Control Register (CMPCTL) Figure 34-68. Counter-Compare Control Register (CMPCTL) [offset = 0Eh] 15 10 Reserved R-0 3 2 9 8 SHDWBFULL SHDWAFULL R-0 R-0 1 0 7 6 5 4 Reserved SHDWBMODE Reserved SHDWAMODE LOADBMODE LOADAMODE R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-28.
ePWM Registers www.ti.com 34.4.2.2 Counter-Compare A Register (CMPA) Figure 34-69. Counter-Compare A Register (CMPA) [offset = 12h] 15 0 CMPA R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-29. Counter-Compare A Register (CMPA) Field Descriptions Bits Name Description 15-0 CMPA The value in the active CMPA register is continuously compared to the time-base counter (TBCTR).
ePWM Registers www.ti.com 34.4.2.3 Counter-Compare B Register (CMPB) Figure 34-70. Counter-Compare B Register (CMPB) [offset = 14h] 15 0 CMPB R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-30. Counter-Compare B Register (CMPB) Field Descriptions Bits Name Description 15-0 CMPB The value in the active CMPB register is continuously compared to the time-base counter (TBCTR).
ePWM Registers www.ti.com 34.4.3 Action-Qualifier Submodule Registers 34.4.3.1 Action-Qualifier Output A Control Register (AQCTLA) Figure 34-71. Action-Qualifier Output A Control Register (AQCTLA) [offset = 16h] 15 12 7 11 10 9 8 Reserved CBD CBU R-0 R/W-0 R/W-0 6 5 4 3 2 1 0 CAD CAU PRD ZRO R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-31.
ePWM Registers www.ti.com 34.4.3.2 Action-Qualifier Software Force Register (AQSFRC) Figure 34-72. Action-Qualifier Software Force Register (AQSFRC) [offset = 1A] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 RLDCSF OTSFB ACTSFB OTSFA ACTSFA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-32.
ePWM Registers www.ti.com 34.4.3.3 Action-Qualifier Output B Control Register (AQCTLB) Figure 34-73. Action-Qualifier Output B Control Register (AQCTLB) [offset = 18h] 15 12 7 11 10 9 8 Reserved CBD CBU R-0 R/W-0 R/W-0 6 5 4 3 2 1 0 CAD CAU PRD ZRO R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-33.
ePWM Registers www.ti.com 34.4.3.4 Action-Qualifier Continuous Force Register (AQCSFRC) Figure 34-74. Action-Qualifier Continuous Software Force Register (AQCSFRC) [offset = 1Ch] 15 8 Reserved R-0 7 4 3 2 1 0 Reserved CSFB CSFA R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-34.
ePWM Registers www.ti.com 34.4.4 Dead-Band Submodule Registers 34.4.4.1 Dead-Band Generator Control Register (DBCTL) Figure 34-75. Dead-Band Generator Control Register (DBCTL) [offset = 1Eh] 15 14 8 HALFCYCLE Reserved R/W-0 R-0 7 6 5 4 3 2 1 0 Reserved IN_MODE POLSEL OUT_MODE R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-35.
ePWM Registers www.ti.com Table 34-35. Dead-Band Generator Control Register (DBCTL) Field Descriptions (continued) Bits Name 1-0 OUT_MODE Value Description Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 34-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0 Dead-band generation is bypassed for both output signals.
ePWM Registers www.ti.com 34.4.4.2 Dead-Band Generator Falling Edge Delay Register (DBFED) Figure 34-76. Dead-Band Generator Falling Edge Delay Register (DBFED) [offset = 22h] 15 10 9 8 Reserved DEL R-0 R/W-0 7 0 DEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-36. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions Bits 15-10 9-0 Name Description Reserved Reserved DEL Falling Edge Delay Count. 10-bit counter 34.4.4.
ePWM Registers www.ti.com 34.4.5 Trip-Zone Submodule Registers 34.4.5.1 Trip-Zone Digital Compare Event Select Register (TZDCSEL) Figure 34-78. Trip Zone Digital Compare Event Select Register (TZDCSEL) [offset = 26h] 15 12 11 9 8 6 5 3 2 0 Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-38.
ePWM Registers www.ti.com 34.4.5.2 Trip-Zone Select Register (TZSEL) Figure 34-79. Trip-Zone Select Register (TZSEL) [offset = 24h] 15 14 13 12 11 10 9 8 DCBEVT1 DCAEVT1 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 DCBEVT2 DCAEVT2 R-0 CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-39.
ePWM Registers www.ti.com Table 34-39.
ePWM Registers www.ti.com 34.4.5.3 Trip-Zone Enable Interrupt Register (TZEINT) Figure 34-80. Trip-Zone Enable Interrupt Register (TZEINT) [offset = 2Ah] 15 8 Reserved R -0 7 6 5 4 3 2 Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 1 0 OST CBC Reserved R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-40.
ePWM Registers www.ti.com 34.4.5.4 Trip-Zone Control Register (TZCTL) Figure 34-81. Trip-Zone Control Register (TZCTL) [offset = 28h] 15 12 7 11 10 Reserved DCBEVT2 R-0 R/W-0 6 5 4 3 9 8 DCBEVT1 R/W-0 2 1 0 DCAEVT2 DCAEVT1 TZB TZA R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-41.
ePWM Registers www.ti.com 34.4.5.5 Trip-Zone Clear Register (TZCLR) Figure 34-82. Trip-Zone Clear Register (TZCLR) [offset = 2Eh] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 OST CBC INT R-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; nC - write n to clear; R = Read only; -n = value after reset Table 34-42.
ePWM Registers www.ti.com 34.4.5.6 Trip-Zone Flag Register (TZFLG) Figure 34-83. Trip-Zone Flag Register (TZFLG) [offset = 2Ch] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 OST CBC INT R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-43.
ePWM Registers www.ti.com 34.4.5.7 Trip-Zone Force Register (TZFRC) Figure 34-84. Trip-Zone Force Register (TZFRC) [offset = 30h] 15 8 Reserved R-0 7 6 5 4 3 2 Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 1 0 OST CBC Reserved R/W-0 R/W-0 R- 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-44.
ePWM Registers www.ti.com 34.4.6 Event-Trigger Submodule Registers 34.4.6.1 Event-Trigger Selection Register (ETSEL) Figure 34-85. Event-Trigger Selection Register (ETSEL) [offset = 32h] 15 14 12 11 10 8 SOCBEN SOCBSEL SOCAEN SOCASEL R/W-0 R/W-0 R/W-0 R/W-0 7 4 3 2 0 Reserved INTEN INTSEL R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-45.
ePWM Registers www.ti.com Table 34-45. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued) Bits Name 2-0 INTSEL Value Description ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode.
ePWM Registers www.ti.com 34.4.6.3 Event-Trigger Prescale Register (ETPS) Figure 34-87. Event-Trigger Prescale Register (ETPS) [offset = 34h] 15 14 13 12 11 10 9 8 SOCBCNT SOCBPRD SOCACNT SOCAPRD R-0 R/W-0 R-0 R/W-0 7 4 3 2 1 0 Reserved INTCNT INTPRD R-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-47.
ePWM Registers www.ti.com Table 34-47. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued) Bits Name 3-2 INTCNT Value Description ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated.
ePWM Registers www.ti.com 34.4.6.4 Event-Trigger Force Register (ETFRC) Figure 34-88. Event-Trigger Force Register (ETFRC) [offset = 3Ah] 15 8 Reserved R-0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-48. Event-Trigger Force Register (ETFRC) Field Descriptions Bits Name 15-4 Reserved 3 2 0 SOCB Reserved 0 INT Description Reserved SOCB Force Bit.
ePWM Registers www.ti.com 34.4.6.5 Event-Trigger Clear Register (ETCLR) Figure 34-89. Event-Trigger Clear Register (ETCLR) [offset = 38h] 15 8 Reserved R-0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-49.
ePWM Registers www.ti.com 34.4.7 PWM-Chopper Submodule Register 34.4.7.1 PWM-Chopper Control Register (PCCTL) Figure 34-90. PWM-Chopper Control Register (PCCTL) [offset = 3Ch 15 11 7 10 8 Reserved CHPDUTY R-0 R/W-0 5 4 1 0 CHPFREQ OSHTWTH CHPEN R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-50.
ePWM Registers www.ti.com Table 34-50.
ePWM Registers www.ti.com 34.4.8 Digital Compare Submodule Registers 34.4.8.1 Digital Compare A Control Register (DCACTL) Figure 34-91. Digital Compare A Control Register (DCACTL) [offset = 62h] 15 9 8 Reserved 10 EVT2FRC SYNCSEL EVT2SRCSEL R-0 R/W-0 R/W-0 7 3 2 1 0 Reserved 4 EVT1SYNCE EVT1SOCE EVT1FRC SYNCSEL EVT1SRCSEL R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-51.
ePWM Registers www.ti.com 34.4.8.2 Digital Compare Trip Select (DCTRIPSEL) Figure 34-92. Digital Compare Trip Select (DCTRIPSEL) [offset = 60h] 15 12 11 8 DCBLCOMPSEL DCBHCOMPSEL R/W-0 R/W-0 7 4 3 0 DCALCOMPSEL DCAHCOMPSEL R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-52.
ePWM Registers www.ti.com 34.4.8.3 Digital Compare Filter Control Register (DCFCTL) Figure 34-93. Digital Compare Filter Control Register (DCFCTL) [offset = 66h] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 Reserved PULSESEL BLANKINV BLANKE SRCSEL R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-53.
ePWM Registers www.ti.com 34.4.8.4 Digital Compare B Control Register (DCBCTL) Figure 34-94. Digital Compare B Control Register (DCBCTL) [offset = 64h] 15 9 8 Reserved 10 EVT2FRC SYNCSEL EVT2SRCSEL R-0 R/W-0 R/W-0 7 3 2 1 0 Reserved 4 EVT1SYNCE EVT1SOCE EVT1FRC SYNCSEL EVT1SRCSEL R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-54.
ePWM Registers www.ti.com 34.4.8.5 Digital Compare Filter Offset Register (DCFOFFSET) Figure 34-95. Digital Compare Filter Offset Register (DCFOFFSET) [offset = 6Ah] 15 0 DCOFFSET R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-55.
ePWM Registers www.ti.com 34.4.8.7 Digital Compare Filter Window Register (DCFWINDOW) Figure 34-97. Digital Compare Filter Window Register (DCFWINDOW) [offset = 6Eh] 15 8 Reserved R-0 7 0 WINDOW R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-57. Digital Compare Filter Window Register (DCFWINDOW) Field Descriptions Bit Field 15-8 Reserved 7-0 WINDOW Value 0 Description Reserved Blanking Window Width 0 1h-FFh No blanking window is generated.
ePWM Registers www.ti.com 34.4.8.9 Digital Compare Counter Capture Register (DCCAP) Figure 34-99. Digital Compare Counter Capture Register (DCCAP) [offset = 72h] 15 0 DCCAP R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34-59. Digital Compare Counter Capture Register (DCCAP) Field Descriptions Bit 15-0 Field Description DCCAP Digital Compare Time-Base Counter Capture To enable time-base counter capture, set the DCCAPCLT[CAPE] bit to 1.
Chapter 35 SPNU562 – May 2014 Data Modification Module (DMM) This chapter describes the functionality of the Data Modification Module (DMM), which provides the capability to modify data in the entire 4 GB address space of the device from an external peripheral, with minimal interruption of the application. Topic 35.1 35.2 35.3 ........................................................................................................................... Page Overview.........................................
Overview www.ti.com 35.1 Overview 35.1.
Module Operation www.ti.com 35.2 Module Operation The DMM receives data over the DMM pins from external systems and writes the received data directly to the base address programmed in the module plus offset address given in the packet or into a buffer specified by start address and length. It leverages the protocol defined by the RAM Trace Port (RTP) module to have a common interface definition for external systems.
Module Operation www.ti.com The DEST bits (Table 35-1) will be used to determine which destination register applies to the transmitted data and the received address determines if the packet falls into a valid region of the destination area. If the address is valid, the base address, programmed in one of the destination registers (Section 35.3.12; Section 35.3.14) of this particular region will be applied to create the complete 32-bit address for the destination.
Module Operation www.ti.com The packet consists only of data bits and no header information. It can be 8-, 16- or 32-bit wide. A variable packet width is not supported because the DMM module will check the number of incoming bits (DMMCLK cycles) for error detection. The DMM will write the received data to the destination once the programmed number of bits has been received.
Module Operation www.ti.com 35.2.2.1 Signal Description DMMSYNC This signal has to be provided by external hardware. It signals the start of a new packet. It has to be active (high) for one full DMMCLK cycle, starting with the rising edge of DMMCLK. If the DMMSYNC pulse is longer than a single DMMCLK cycle and two falling edges of DMMCLK see a high pulse on DMMSYNC, the module will treat the second DMMSYNC pulse as the start of a packet and will flag a PACKET_ERR_INT (Section 35.3.5).
Module Operation www.ti.com 35.2.3.1 Overflow Error This error is signaled when the module has received new data before the previous data was written to the destination address. If the internal buffers are full, the DMMENA signal will go high. If the sending module does not evaluate the DMMENA signal and keeps on sending new frames, the data that was previously received might be overwritten, thus resulting in setting the BUFF_OVF flag (Section 35.3.5). 35.2.3.
Control Registers www.ti.com 35.3 Control Registers This section describes the DMM registers. The registers support 8, 16, and 32-bit writes. The offset is relative to the associated peripheral select. Table 35-6 provides a summary of the registers and their bits. The base address of the DMM module registers is FFFF F700h. Table 35-6. DMM Registers Offset Acronym Register Description 0 DMMGLBCTRL DMM Global Control Register Section 35.3.1 4h DMMINTSET DMM Interrupt Set Register Section 35.3.
Control Registers www.ti.com 35.3.1 DMM Global Control Register (DMMGLBCTRL) With this register the basic operation of the module is selected. Figure 35-7.
Control Registers www.ti.com Table 35-7. DMM Global Control Register (DMMGLBCTRL) Field Descriptions (continued) Bit 10-9 Field Value DDM_WIDTH Description Packet Width in direct data mode. User and privilege mode read and privilege mode write operation: Bit Encoding 8 Transfer Size 0 8 bit 1h 16 bit 2h 32 bit 3h Reserved TM_DMM Packet Format.
Control Registers www.ti.com 35.3.2 DMM Interrupt Set Register (DMMINTSET) This register contains the interrupt set bits for error interrupts and functional interrupts. Only the bits which are relevant for the particular mode (trace mode or direct data mode) will be taken into account for the interrupt generation. Figure 35-8.
Control Registers www.ti.com Table 35-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions (continued) Bit Field 14 DEST3REG1 Value Description Destination 3 Region 1 Interrupt Set. This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1. This bit is only relevant in Trace Mode.
Control Registers www.ti.com Table 35-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions (continued) Bit 9 Field Value DEST0REG2 Description Destination 0 Region 2 Interrupt Set. This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2. This bit is only relevant in Trace Mode.
Control Registers www.ti.com Table 35-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions (continued) Bit 4 Field Value DEST3_ERR Description Destination 3 Error. This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2. If both blocksizes are programmed to 0 or a reserved value, the interrupt will still be generated, the write to the internal RAM however will not take place.
Control Registers www.ti.com 35.3.3 DMM Interrupt Clear Register (DMMINTCLR) This register contains the interrupt clear bits for error interrupts and functional interrupts. Only the bits which are relevant for the particular mode (trace mode or direct data mode) will be taken into account for the interrupt generation Figure 35-9.
Control Registers www.ti.com Table 35-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions (continued) Bit Field 14 DEST3REG1 Value Description Destination 3 Region 1 Interrupt Set.This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1. This bit is only relevant in Trace Mode.
Control Registers www.ti.com Table 35-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions (continued) Bit 9 Field Value DEST0REG2 Description Destination 0 Region 2 Interrupt Set.This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2. This bit is only relevant in Trace Mode.
Control Registers www.ti.com Table 35-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions (continued) Bit 4 Field Value DEST3_ERR Description Destination 3 Error.This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2. If both blocksizes are programmed to 0 or a reserved value, the interrupt will still be generated, the write to the internal RAM however will not take place.
Control Registers www.ti.com Table 35-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions (continued) Bit 0 Field Value PACKET_ERR_INT Description Packet Error.This disables the interrupt generation in case of an error condition in the packet reception. Please refer to Section 35.2.3for the error conditions.
Control Registers www.ti.com 35.3.4 DMM Interrupt Level Register (DMMINTLVL) This register contains the interrupt level bits for error interrupts and normal interrupts. Figure 35-10.
Control Registers www.ti.com Table 35-10.
Control Registers www.ti.com 35.3.5 DMM Interrupt Flag Register (DMMINTFLG) This register contains the interrupt level bits for error interrupts and normal interrupts. Figure 35-11.
Control Registers www.ti.com Table 35-11.
Control Registers www.ti.com Table 35-11. DMM Interrupt Flag Register (DMMINTFLG) Field Descriptions (continued) Bit 7 Field Value BUSERROR Description BMM Bus Error Response.
Control Registers www.ti.com Table 35-11.
Control Registers www.ti.com 35.3.6 DMM Interrupt Offset 1 Register (DMMOFF1) This register holds the offset indicating which interrupt occurred on interrupt level 0. The CPU can read this register to determine the source of the interrupt without having to test individual interrupt flags. Figure 35-12. DMM Interrupt Offset 1 Register (DMMOFF1) [offset = 14h] 31 16 Reserved R-0 15 5 4 0 Reserved OFFSET R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 35-12.
Control Registers www.ti.com 35.3.7 DMM Interrupt Offset 2 Register (DMMOFF2) This register holds the offset indicating which interrupt occurred on interrupt level 1. The CPU can read this register to determine the source of the interrupt without having to test individual interrupt flags. Figure 35-13. DMM Interrupt Offset 2 Register (DMMOFF2) [offset = 18h] 31 16 Reserved R-0 15 5 4 0 Reserved OFFSET R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 35-13.
Control Registers www.ti.com 35.3.8 DMM Direct Data Mode Destination Register (DMMDDMDEST) This register defines the starting address of the buffer used to store the received data in Direct Data Mode. By writing to this register, the DMMDDMPT register (Section 35.3.10) will be set to 0x0000. Figure 35-14.
Control Registers www.ti.com 35.3.10 DMM Direct Data Mode Pointer Register (DMMDDMPT) This register shows the pointer into the buffer programmed by DMMDDMDEST (Section 35.3.8) and DMMDDMBL (Section 35.3.9). Figure 35-16. DMM Direct Data Mode Pointer Register (DMMDDMPT) [offset = 24h] 31 16 Reserved R-0 15 14 0 Rsvd POINTER R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 35-16.
Control Registers www.ti.com 35.3.12 DMM Destination x Region 1 (DMMDESTxREG1) This register defines the starting address of the buffer used to store the received data in Trace Mode. If the received data does not fall into the address range defined by DMMDESTxREG1 and DMMDESTxBL1, an interrupt (DESTx_ERR) can be generated. The description below is valid for following registers: DMMDEST0REG1, DMMDEST1REG1, DMMDEST2REG1, DMMDEST3REG1. Figure 35-18.
Control Registers www.ti.com 35.3.13 DMM Destination x Blocksize 1 (DMMDESTxBL1) This register defines the blocksize of the buffer used to store the received data in Trace Mode. If the received data does not fall into the address range defined by DMMDESTxREG1 and DMMDESTxBL1, an interrupt (DESTx_ERR) can be generated. The description below is valid for following registers: DMMDEST0BL1, DMMDEST1BL1, DMMDEST2BL1, DMMDEST3BL1. Figure 35-19.
Control Registers www.ti.com 35.3.14 DMM Destination x Region 2 (DMMDESTxREG2) This register defines the starting address of the buffer used to store the received data in Trace Mode. If the received data does not fall into the address range defined by DMMDESTxREG2 and DMMDESTxBL2, an interrupt (DESTx_ERR) can be generated. The description below is valid for following registers: DMMDEST0REG2, DMMDEST1REG2, DMMDEST2REG2, DMMDEST3REG2. Figure 35-20.
Control Registers www.ti.com 35.3.15 DMM Destination x Blocksize 2 (DMMDESTxBL2) This register defines the blocksize of the buffer used to store the received data in Trace Mode. If the received data does not fall into the address range defined by DMMDESTxREG2 and DMMDESTxBL2, an interrupt (DESTx_ERR) can be generated. The description below is valid for following registers: DMMDEST0BL2, DMMDEST1BL2, DMMDEST2BL2, DMMDEST3BL2. Figure 35-21.
Control Registers www.ti.com 35.3.16 DMM Pin Control 0 (DMMPC0) This register defines if the DMM pins are used in functional or GIO mode. It should only be written when ON/OFF = 0101 and the BUSY bit = 0 (Section 35.3.1). If pins other than the pins specified in Table 35-5 are configured, or DMMCLK and DMMSYNC are programmed as non-functional pins, no operation in trace mode or direct data mode is possible. Figure 35-22.
Control Registers www.ti.com Table 35-22. DMM Pin Control 0 (DMMPC0) Field Descriptions (continued) Bit Field 0 Value SYNCFUNC Description Functional mode of DMMSYNC pin. This bit defines whether the pin is used in functional mode or in GIO mode. User and privilege mode (read): 0 Pin is used in GIO mode 1 Pin is used in Functional mode User and privilege mode (write): 0 Pin is used in GIO mode 1 Pin is used in Functional mode 35.3.
Control Registers www.ti.com Table 35-23. DMM Pin Control 1 (DMMPC1) Field Descriptions (continued) Bit 1 Field Value CLKDIR Description Direction of DMMCLK pin. This bit defines whether the pin is used as input or output in GIO mode. User and privilege mode (read): 0 Pin is used as input 1 Pin is used as output User and privilege mode (write): 0 0 Pin is set to input 1 Pin is set to output SYNCDIR Direction of DMMSYNC pin.
Control Registers www.ti.com 35.3.18 DMM Pin Control 2 (DMMPC2) The bits in this register reflect the digital representation of the voltage level at the module pins. Even if a pin is configured to be an output pin, the level can be read back via this register. Figure 35-24.
Control Registers www.ti.com 35.3.19 DMM Pin Control 3 (DMMPC3) The bits in this register set the pin to logic low or high level if the pin is configured as output (Section 35.3.17). Figure 35-25.
Control Registers www.ti.com Table 35-25. DMM Pin Control 3 (DMMPC3) Field Descriptions (continued) Bit Field 0 Value SYNCOUT Description Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. User and privilege mode (read): 0 Logic low (output voltage is V OL or lower) 1 Logic high (output voltage is V OH or higher) User and privilege mode (write): 0 Logic low (output voltage is set to V OL or lower) 1 Logic high (output voltage is set to V OH or higher) 35.3.
Control Registers www.ti.com Table 35-26. DMM Pin Control 4 (DMMPC4) Field Descriptions (continued) Bit 1 Field Value CLKSET Description Sets output state of DMMCLK pin to logic high. Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit.
Control Registers www.ti.com 35.3.21 DMM Pin Control 5 (DMMPC5) This register allows to set individual pins to a logic low level without having to do a read-modify-write operation as would be the case with the DMMPC3 register (Section 35.3.19). Writing a one to a bit will change the output to a logic low level, writing a zero will not change the state of the pin. Figure 35-27.
Control Registers www.ti.com Table 35-27. DMM Pin Control 5 (DMMPC5) Field Descriptions (continued) Bit Field 0 Value Description SYNCCLR Sets output state of DMMSYNC pin to logic low. Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit.
Control Registers www.ti.com Table 35-28. DMM Pin Control 6 (DMMPC6) Field Descriptions (continued) Bit 17-2 Field Value DATAxPDR Description Open Drain enable. Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0[x]=0; DMMPC1[x]=1). If the pin is configured as functional pin (DMMPC0[x] = 1), the open drain functionality is disabled.
Control Registers www.ti.com 35.3.23 DMM Pin Control 7 (DMMPC7) The bits in register control the pullup/down functionality of a pin. The internal pullup/down can be enabled or disabled by this register. The reset configuration of these bits is device implementation dependent. Please consult the device datasheet this information. Figure 35-29.
Control Registers www.ti.com Table 35-29. DMM Pin Control 7 (DMMPC7) Field Descriptions (continued) Bit Field 0 Value SYNCPDIS Description Pull disable. Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1[0] = 0). User and privilege mode (read): 0 Pullup/pulldown functionality enabled 1 Pullup/pulldown functionality disabled User and privilege mode (write): 0 Enables pullup/pulldown functionality 1 Disables pullup/pulldown functionality 35.3.
Control Registers www.ti.com Table 35-30. DMM Pin Control 8 (DMMPC8) Field Descriptions (continued) Bit 1 Field Value CLKPSEL Description Pull select. Configures pullup or pulldown functionality if DMMPC7[1] = 0). User and privilege mode (read): 0 Pulldown functionality enabled 1 Pullup functionality enabled User and privilege mode (write): 0 0 Enables pulldown functionality 1 Enables pullup functionality SYNCPSEL Pull select. Configures pullup or pulldown functionality if DMMPC7[0] = 0).
Chapter 36 SPNU562 – May 2014 RAM Trace Port (RTP) This chapter describes the functionality of the RAM trace port (RTP) module. It allows the capability to perform data trace of a CPU or other master accesses to the internal RAM and peripherals. Topic 36.1 36.2 36.3 ........................................................................................................................... Page Overview.......................................................................................................
Overview www.ti.com 36.1 Overview This document describes the functionality of the RAM trace port (RTP) module, which provides the features to datalog the RAM contents of the devices or accesses to peripherals without program intrusion. It can trace all data write or read accesses to internal RAM. In addition, it provides the capability to directly transfer data to a FIFO to support a CPU-controlled transmission of the data. The trace data is transmitted over a dedicated external interface. 36.1.
Overview www.ti.com 36.1.2 Block Diagram Figure 36-1 is a block diagram of the RTP. Figure 36-1.
Module Operation www.ti.com 36.2 Module Operation The RTP module has two modes of operation: Trace Mode and Direct Data Mode. 36.2.1 Trace Mode This mode traces all write or read accesses of CPU and/or a different master to the internal RAMs and the peripheral bus, if the access falls into one of the programmed trace regions. The trace regions allow to restrict the amount of data which is traced. This is done by specifying the start address and the size of the region to be traced.
Module Operation www.ti.com Table 36-1. Encoding of RAM Bits in Trace Mode Packet Format RAM[1:0] RAM 0 Level 2 lower 256kB RAM 1h Level 2 upper 256kB RAM 2h Peripherals under PCR1 3h Peripherals under PCR3 Table 36-2.
Module Operation www.ti.com Example: For a 16-bit port and with data of 16-bit, the last transfer has to be padded with eight 0s. This effectively results in a transfer of 48 bits instead of 40. However the whole transfer is completed in 3 RTPCLK cycles. For a detailed description of the representation of the packet on the RTP port pins, refer to Section 36.2.5. 36.2.2 Direct Data Mode (DDM) In this mode, data is written directly by the CPU or other master to a dedicated capture register (RTPDDMW).
Module Operation www.ti.com 36.2.3.1 Inverse Trace Regions The RTP can be configured to trace accesses which fall into, or are made outside of the specified regions. This can be accomplished by the INV_RGN bit. If this bit is 0, all access which are made inside a region are traced. If the bit is 1, all accesses outside the region are traced. The INV_RGN bit affects all regions of the RTP, see the RTP global control register (RTPGLBCTRL).
Module Operation www.ti.com 36.2.3.3 Cortex-R5 Specifics Considerations/Restrictions • Reading and writing from/to Level 2 RAMs which is declared Cacheable can result in RAM traces that do not correspond to the software's original intent. • A store instruction to Non-cacheable, or write-through Normal memory might not result in an AXI transfer to the Level 2 RAMs or peripherals because of the merging of store in the internal buffers. 36.2.
Module Operation www.ti.com Figure 36-7 shows an example of multiple packet transmissions in Trace Mode with an interruption between packets because of RTPENA pulled high. Figure 36-7. RTP Packet Transfer with Sync Signal RTPENA RTPCLK RTPSYNC RTPDATA Packet1 Packet2 Packet4 Packet3 Packet1 Packet2 Figure 36-8 shows an example of a 4-bit data port with 8-bit write data (A5h) written into RAM1 (address 12345h) with no overflow in trace mode. Figure 36-8.
Module Operation www.ti.com 36.2.7 GIO Function Pins which are not used for RTP functionality can be used as normal GIO pins. If pins should be used in functional mode or GIO mode, they can be programmed in the RTP pin control 0 register (RTPPC0). The direction of the pins can be chosen in the RTP pin control 1 register (RTPPC1). Module pins can have either an internal pullup or active pulldown that makes it possible to leave the pins unconnected externally when configured as inputs.
RTP Control Registers www.ti.com 36.3.1 RTP Global Control Register (RTPGLBCTRL) The configuration of the module can be changed with this register. Figure 36-9 and Table 36-8 describe this register. Figure 36-9.
RTP Control Registers www.ti.com Table 36-8. RTP Global Control Register (RTPGLBCTRL) Field Descriptions (continued) Bit Field 11 DDM_RW Value Description Direct Data Mode Read: 0 Read tracing in Direct Data Mode is enabled. 1 Write tracing in Direct Data Mode to DDMW register is enabled. Write in Privilege: 10 0 Enable read tracing in Direct Data Mode. The RW bits in the RTPRAMxREGy registers to be ignored. 1 Write tracing in Direct Data Mode to DDMW register is enabled.
RTP Control Registers www.ti.com Table 36-8. RTP Global Control Register (RTPGLBCTRL) Field Descriptions (continued) Bit 4 Field Value Description INV_RGN Trace inside or outside of defined trace regions. Read: 0 Accesses inside the trace regions are traced. 1 Accesses outside the trace regions are traced. Write in Privilege: 3-0 0 Allow tracing of accesses inside the regions set in RTPRAMxREGy. 1 Allow tracing of accesses outside the regions set in RTPRAMxREGy. ON/OFF ON/Off switch.
RTP Control Registers www.ti.com 36.3.2 RTP Trace Enable Register (RTPTRENA) This register enables/disables tracing of the different RAM blocks or the peripherals individually. Figure 36-10 and Table 36-11 describe this register. Figure 36-10.
RTP Control Registers www.ti.com Table 36-11. RTP Trace Enable Register (RTPTRENA) Field Descriptions (continued) Bit Field 0 ENA1 Value Description Enable tracing for RAM block 1. This bit enables tracing into FIFO1 in Trace Mode (read/write) or Direct Data Mode (read) operations. In Direct Data Mode write operations, this bit will be ignored and tracing into FIFO1 will be disabled. Read: 0 Tracing is disabled. 1 Tracing is enabled. Write in Privilege: 0 Disable tracing. If RTPGLBCTRL.
RTP Control Registers www.ti.com 36.3.3 RTP Global Status Register (RTPGSR) This register provides status information of the module. Figure 36-11 and Table 36-12 describe this register. Figure 36-11.
RTP Control Registers www.ti.com Table 36-12. RTP Global Status Register (RTPGSR) Field Descriptions (continued) Bit Field 1 OVF2 Value Description Overflow RAM block 2 FIFO. This flag indicates that FIFO2 had all locations full and another attempt to write data to it occurred. The bit will not be cleared automatically if the FIFO is emptied again. The bit will stay set until the CPU clears it. Read: 0 No overflow occurred. 1 An overflow occurred. Write in Privilege: 0 0 No effect.
RTP Control Registers www.ti.com 36.3.4 RTP RAM 1 Trace Region Registers (RTPRAM1REG[1:2]) Figure 36-12 and Table 36-13 illustrate these registers. Figure 36-12. RTP RAM 1 Trace Region Registers (RTPRAM1REGn) (offset = 0Ch and 10h) 31 29 28 27 24 23 18 17 16 CPU_DMA RW BLOCKSIZE Reserved STARTADDR R/WP-0 R/WP-0 R/WP-0 R-0 R/WP-0 15 0 STARTADDR R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 36-13.
RTP Control Registers www.ti.com 36.3.5 RTP RAM 2 Trace Region Registers (RTPRAM2REG[1:2]) Figure 36-13 and Table 36-14 illustrate these registers. Figure 36-13. RTP RAM 2 Trace Region Registers (RTPRAM2REGn) (offset = 14h and 18h) 31 29 28 27 24 23 18 17 16 CPU_DMA RW BLOCKSIZE Reserved STARTADDR R/WP-0 R/WP-0 R/WP-0 R-0 R/WP-0 15 0 STARTADDR R/WP-0 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 36-14.
RTP Control Registers www.ti.com 36.3.6 RTP RAM 3 Trace Region Registers (RTPRAM3REG[1:2]) FIFO3 was originally designed to support RAM trace limiting to a maximum trace range of 256kB. In this device, FIFO3 is dedicated for tracing the PCR1 peripheral accesses. Peripherals in PCR1 occupy a total address range of 512kB of space. Therefore, it is not possible to trace the entire range of 512kB since there are only 18 bits of address being traced out in the packet.
RTP Control Registers www.ti.com Table 36-15. RTP RAM 3 Trace Region Registers (RTPRAM3REGn) Field Descriptions (continued) Bit 27-24 Field Value BLOCKSIZE Description These bits define the length of the trace region. Depending on the setting of INV_RGN (RTPGLBCTRL), accesses inside or outside the region defined by the start address and blocksize will be traced. If all bits of BLOCKSIZE are 0, the region is disabled and no data will be captured.
RTP Control Registers www.ti.com 36.3.7 RTP Peripheral Trace Region Registers (RTPPERREG[1:2]) FIFO4 is dedicated for tracing the PCR3 peripheral accesses. Since the peripheral frame is 16 Mbytes, the start address has to be defined as a 24-bit value. However, only bits 16 to 0 will be transmitted in the protocol. Bit REG (Section 36.2.1.1) in the protocol will be 0 if there was an access to the range defined by RTPPERREG1. REG will be 1 if the access was into the range defined by RTPPERREG2.
RTP Control Registers www.ti.com 36.3.8 RTP Direct Data Mode Write Register (RTPDDMW) The CPU has to write data to this register if the module is used in Direct Data Mode write configuration. Figure 36-16 and Table 36-17 describe this register. Figure 36-16. RTP Direct Data Mode Write Register (RTPDDMW) (offset = 2Ch) 31 0 DATA R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 36-17.
RTP Control Registers www.ti.com 36.3.9 RTP Pin Control 0 Register (RTPPC0) This register configures the RTP pins as functional or GIO pins. Once the pin is configured in functional mode, it overrides the settings in the RTPPC1 register. Writing to the RTPPC3, RTPPC4, and RTPPC5 registers will have no effect for pins configured as functional pins. Figure 36-17 and Table 36-18 describe this register. Figure 36-17.
RTP Control Registers www.ti.com 36.3.10 RTP Pin Control 1 Register (RTPPC1) Once the pin is configured in functional mode (using RTPPC0 register), configuring the corresponding bit in RTPPC1 to 0 will not disable the output driver. Figure 36-18 and Table 36-19 describe this register. Figure 36-18.
RTP Control Registers www.ti.com 36.3.11 RTP Pin Control 2 Register (RTPPC2) This register represents the input value of the pins when in GIO or functional mode. Figure 36-19 and Table 36-20 describe this register. Figure 36-19. RTP Pin Control 2 Register (RTPPC2) (offset = 3Ch) 31 18 17 16 Reserved 19 ENAIN CLKIN SYNCIN R-0 R-x R-x R-x 15 0 DATAIN[15:0] R-x LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 36-20.
RTP Control Registers www.ti.com 36.3.12 RTP Pin Control 3 Register (RTPPC3) This register defines the state of the pins when configured in GIO mode as output pins. Once a pin is configured in functional mode (using RTPPC0 register), changing the state of the corresponding bit in RTPPC3 will not affect the pin's state. Figure 36-20 and Table 36-21 describe this register. Figure 36-20.
RTP Control Registers www.ti.com 36.3.13 RTP Pin Control 4 Register (RTPPC4) This register provides the option to set pins to a logic 1 level without influencing the state of other pins. It eliminates the read-modify-write operation necessary with the RTPPC3 register. Once the pin is configured in functional mode (using RTPPC0 register), setting the corresponding bit to one in RTPPC4 will not affect the pin's state. Figure 36-21 and Table 36-22 describe this register. Figure 36-21.
RTP Control Registers www.ti.com 36.3.14 RTP Pin Control 5 Register (RTPPC5) This register provides the option to set pins to a logic 0 level without influencing the state of other pins. It eliminates the read-modify-write operation necessary with the RTPPC3 register. Once the pin is configured in functional mode (using RTPPC0 register), setting the corresponding bit to one in RTPPC5 will not affect the pin state. Figure 36-22 and Table 36-23 describe this register. Figure 36-22.
RTP Control Registers www.ti.com 36.3.15 RTP Pin Control 6 Register (RTPPC6) This register configures the pins in push-pull or open-drain functionality. If configured to be open-drain, the module only drives a logic low level on the pin. An external pull-up resistor needs to be connected to the pin to pull it high when the pin is in high-impedance mode. Figure 36-23 and Table 36-24 describe this register. Figure 36-23.
RTP Control Registers www.ti.com Table 36-24. RTP Pin Control 6 Register (RTPPC6) Field Descriptions (continued) Bit 15-0 Field Value DATAPDR[n] Description RTPDATA[15:0] Open drain enable. These bits enable open drain functionality on the pins if they are configured as a GIO output (RTPPC0[15:0] = 0; RTPPC1[15:0] = 1). If the pins are configured as a functional pins (RTPPC0[15:0] = 1), the open drain functionality is disabled. Each bit [n] represents a single pin.
RTP Control Registers www.ti.com 36.3.16 RTP Pin Control 7 Register (RTPPC7) This register controls the pullup/down functionality of a pin. The internal pullup/down can be enabled or disabled by this register. The reset configuration of these bits is device dependent, consult the device datasheet for this information. Figure 36-24 and Table 36-25 describe this register. Figure 36-24.
RTP Control Registers www.ti.com 36.3.17 RTP Pin Control 8 Register (RTPPC8) This register configures the internal pullup or pulldown on the input pin. A secondary function exists when the pull configuration is disabled and a pulldown is selected. This will disable the input buffer. Figure 36-25 and Table 36-26 describe this register. NOTE: If the pullup/down is disabled in the RTPPC7 register and configured as pulldown in RTPPC8, then the input buffer is disabled. Figure 36-25.
Chapter 37 SPNU562 – May 2014 eFuse Controller This chapter describes the eFuse controller. Topic 37.1 37.2 37.3 37.4 1904 ........................................................................................................................... Overview........................................................................................................ Introduction ................................................................................................... eFuse Controller Testing ..........
Overview www.ti.com 37.1 Overview Electrically programmable fuses (eFuses) are used to configure the device after deassertion of PORRST. The eFuse values are read and loaded into internal registers as part of the power-on-reset sequence. The eFuse values are protected with single bit error correction, double bit error detection (SECDED) codes. These fuses are programmed during the initial factory test of the device.
eFuse Controller Testing www.ti.com 37.3.2.3 Class 3 Error A class 3 error indicates that there was a single bit failure reading the eFuses that was corrected by ECC bits. Proper operation is still likely, but the system is now at a higher risk for a future non-correctable error. When a correctable error occurs, ESM group 1, channel 40 will be set.
eFuse Controller Testing www.ti.com Figure 37-1.
eFuse Controller Registers www.ti.com 37.4 eFuse Controller Registers All registers in the eFuse Controller module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are allowed. Table 37-2 provides a quick reference to each of these registers. Specific bit descriptions are discussed in the following subsections. The base address for the control registers is FFF8 C000h. Table 37-2.
eFuse Controller Registers www.ti.com Table 37-3. EFC Boundary Register (EFCBOUND) Field Descriptions (continued) Bit Field 19 EFC Instruction Error 18 17 16 15 14 13 Value This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. This signal is used to denote an error occurred during e-fuse programming. This signal is not attached to the ESM.
eFuse Controller Registers www.ti.com 37.4.2 EFC Pins Register (EFCPINS) Figure 37-3 and Figure 37-3 describe the EFCPINS register. Figure 37-3.
eFuse Controller Registers www.ti.com 37.4.3 EFC Error Status Register (EFCERRSTAT) Figure 37-4 and Table 37-5 describe the EFCERRSTAT register. Figure 37-4. EFC Error Status Register (EFCERRSTAT) [offset = 3Ch] 31 8 Reserved R-0 7 6 5 4 0 Reserved Instruc Done Error Code R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after power-on reset (nPORRST) Table 37-5.
eFuse Controller Registers www.ti.com 37.4.5 EFC Self Test Signature Register (EFCSTSIG) Figure 37-6 and Table 37-7 describe the EFCSTSIG register. Figure 37-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch] 31 16 Signature R/W-0 15 0 Signature R/W-0 LEGEND: R/W = Read/Write; -n = value after power-on reset (nPORRST) Table 37-7.
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