Datasheet
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 4.1 PGE QFP Package Pinout (144-Pin)
- 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
- 4.3 Terminal Functions
- 4.3.1 PGE Package
- 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.1.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.1.3 Enhanced Capture Modules (eCAP)
- 4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.1.6 General-Purpose Input / Output (GPIO)
- 4.3.1.7 Controller Area Network Controllers (DCAN)
- 4.3.1.8 Local Interconnect Network Interface Module (LIN)
- 4.3.1.9 Standard Serial Communication Interface (SCI)
- 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.1.11 Standard Serial Peripheral Interface (SPI)
- 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.1.13 Ethernet Controller
- 4.3.1.14 USB Host and Device Port Controller Interface
- 4.3.1.15 System Module Interface
- 4.3.1.16 Clock Inputs and Outputs
- 4.3.1.17 Test and Debug Modules Interface
- 4.3.1.18 Flash Supply and Test Pads
- 4.3.1.19 Supply for Core Logic: 1.2V nominal
- 4.3.1.20 Supply for I/O Cells: 3.3V nominal
- 4.3.1.21 Ground Reference for All Supplies Except VCCAD
- 4.3.2 ZWT Package
- 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.2.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.2.3 Enhanced Capture Modules (eCAP)
- 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.2.6 General-Purpose Input / Output (GPIO)
- 4.3.2.7 Controller Area Network Controllers (DCAN)
- 4.3.2.8 Local Interconnect Network Interface Module (LIN)
- 4.3.2.9 Standard Serial Communication Interface (SCI)
- 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.2.11 Standard Serial Peripheral Interface (SPI)
- 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.2.13 Ethernet Controller
- 4.3.2.14 USB Host and Device Port Controller Interface
- 4.3.2.15 External Memory Interface (EMIF)
- 4.3.2.16 System Module Interface
- 4.3.2.17 Clock Inputs and Outputs
- 4.3.2.18 Test and Debug Modules Interface
- 4.3.2.19 Flash Supply and Test Pads
- 4.3.2.20 Reserved
- 4.3.2.21 No Connects
- 4.3.2.22 Supply for Core Logic: 1.2V nominal
- 4.3.2.23 Supply for I/O Cells: 3.3V nominal
- 4.3.2.24 Ground Reference for All Supplies Except VCCAD
- 4.3.1 PGE Package
- 5 Specifications
- 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Device Recommended Operating Conditions
- 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
- 5.6 Wait States Required
- 5.7 Power Consumption Over Recommended Operating Conditions
- 5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions
- 5.9 Thermal Resistance Characteristics
- 5.10 Output Buffer Drive Strengths
- 5.11 Input Timings
- 5.12 Output Timings
- 5.13 Low-EMI Output Buffers
- 6 System Information and Electrical Specifications
- 6.1 Device Power Domains
- 6.2 Voltage Monitor Characteristics
- 6.3 Power Sequencing and Power On Reset
- 6.4 Warm Reset (nRST)
- 6.5 ARM Cortex-R4F CPU Information
- 6.6 Clocks
- 6.7 Clock Monitoring
- 6.8 Glitch Filters
- 6.9 Device Memory Map
- 6.10 Flash Memory
- 6.11 Tightly Coupled RAM Interface Module
- 6.12 Parity Protection for Accesses to Peripheral RAMs
- 6.13 On-Chip SRAM Initialization and Testing
- 6.14 External Memory Interface (EMIF)
- 6.15 Vectored Interrupt Manager
- 6.16 DMA Controller
- 6.17 Real Time Interrupt Module
- 6.18 Error Signaling Module
- 6.19 Reset / Abort / Error Sources
- 6.20 Digital Windowed Watchdog
- 6.21 Debug Subsystem
- 7 Peripheral Information and Electrical Specifications
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 7.1.1 ePWM Clocking and Reset
- 7.1.2 Synchronization of ePWMx Time Base Counters
- 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
- 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
- 7.1.5 ePWM Synchronization with External Devices
- 7.1.6 ePWM Trip Zones
- 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
- 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
- 7.2 Enhanced Capture Modules (eCAP)
- 7.3 Enhanced Quadrature Encoder (eQEP)
- 7.4 Multibuffered 12bit Analog-to-Digital Converter
- 7.5 General-Purpose Input/Output
- 7.6 Enhanced High-End Timer (N2HET)
- 7.7 Controller Area Network (DCAN)
- 7.8 Local Interconnect Network Interface (LIN)
- 7.9 Serial Communication Interface (SCI)
- 7.10 Inter-Integrated Circuit (I2C)
- 7.11 Multibuffered / Standard Serial Peripheral Interface
- 7.12 Ethernet Media Access Controller
- 7.13 Universal Serial Bus (USB) Host and Device Controllers
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
- 1518515_DS2.pdf
A
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C
D
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F
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19
VSS
VSS
TMS
N2HET1
[10]
MIBSPI5
NCS[0]
MIBSPI1
SIMO
MIBSPI1
NENA
MIBSPI5
CLK
MIBSPI5
SIMO[0]
N2HET1
[28]
NC
CAN3RX
AD1EVT
AD1IN[15]
/
AD2IN[15]
AD1IN[22]
/
AD2IN[6]
AD1IN
[6]
AD1IN[11]
/
AD2IN[11]
VSSAD
VSSAD
19
18
VSS
TCK
TDO
nTRST
N2HET1
[8]
MIBSPI1
CLK
MIBSPI1
SOMI
MIBSPI5
NENA
MIBSPI5
SOMI[0]
N2HET1
[0]
NC
CAN3TX
NC
AD1IN[8]
/
AD2IN[8]
AD1IN[14]
/
AD2IN[14]
AD1IN[13]
/
AD2IN[13]
AD1IN
[4]
AD1IN
[2]
VSSAD
18
17
TDI
nRST
NC
EMIF_
nWE
MIBSPI5
SOMI[1]
NC
MIBSPI5
SIMO[3]
MIBSPI5
SIMO[2]
N2HET1
[31]
EMIF_
nCS[3]
EMIF_
nCS[2]
EMIF_
nCS[4]
EMIF_
nCS[0]
NC
AD1IN
[5]
AD1IN
[3]
AD1IN[10]
/
AD2IN[10]
AD1IN
[1]
AD1IN[9]
/
AD2IN[9]
17
16
RTCK
NC
NC
EMIF_
BA[1]
MIBSPI5
SIMO[1]
NC
MIBSPI5
SOMI[3]
MIBSPI5
SOMI[2]
NC
NC
NC
NC
NC
NC
AD1IN[23]
/
AD2IN[7]
AD1IN[12]
/
AD2IN[12]
AD1IN[19]
/
AD2IN[3]
ADREFLO
VSSAD
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
EMIF_
DATA[0]
EMIF_
DATA[1]
EMIF_
DATA[2]
EMIF_
DATA[3]
NC
NC
AD1IN[21]
/
AD2IN[5]
AD1IN[20]
/
AD2IN[4]
ADREFHI
VCCAD
15
14
N2HET1
[26]
nERROR
NC
NC
NC
VCCIO
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
VCCIO
NC
NC
AD1IN[18]
/
AD2IN[2]
AD1IN
[7]
AD1IN
[0]
14
13
N2HET1
[17]
N2HET1
[19]
NC
NC
EMIF_BA[0]
VCCIO
VCCIO
NC
NC
AD1IN[17]
/
AD2IN[1]
AD1IN[16]
/
AD2IN[0]
NC
13
12
ECLK
N2HET1
[4]
NC
NC
EMIF_nOE
VCCIO
VSS
VSS
VCC
VSS
VSS
VCCIO
NC
MIBSPI5
NCS[3]
NC
NC
NC
12
11
N2HET1
[14]
N2HET1
[30]
NC
NC
EMIF_
nDQM[1]
VCCIO
VSS
VSS
VSS
VSS
VSS
VCCPLL
NC
NC
NC
NC
NC
11
10
CAN1TX
CAN1RX
EMIF_
ADDR[12]
NC
EMIF_
nDQM[0]
VCC
VCC
VSS
VSS
VSS
VCC
VCC
NC
NC
NC
MIBSPI3
NCS[0]
GIOB[3]
10
9
N2HET1
[27]
NC
EMIF_
ADDR[11]
NC
EMIF_
ADDR[5]
VCC
VSS
VSS
VSS
VSS
VSS
VCCIO
EXTCLKI
N2
NC
NC
MIBSPI3
CLK
MIBSPI3
NENA
9
8
NC
NC
EMIF_
ADDR[10]
NC
EMIF_
ADDR[4]
VCCP
VSS
VSS
VCC
VSS
VSS
VCCIO
EMIF_
DATA[15]
NC
NC
MIBSPI3
SOMI
MIBSPI3
SIMO
8
7
LINRX
LINTX
EMIF_
ADDR[9]
NC
EMIF_
ADDR[3]
VCCIO
VCCIO
EMIF_
DATA[14]
NC
NC
N2HET1
[9]
nPORRST
7
6
GIOA[4]
MIBSPI5
NCS[1]
EMIF_
ADDR[8]
NC
EMIF_
ADDR[2]
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
EMIF_
DATA[13]
NC
NC
N2HET1
[5]
MIBSPI5
NCS[2]
6
5
GIOA[0]
GIOA[5]
EMIF_
ADDR[7]
EMIF_
ADDR[1]
EMIF_
DATA[4]
EMIF_
DATA[5]
EMIF_
DATA[6]
FLTP2
FLTP1
EMIF_
DATA[7]
EMIF_
DATA[8]
EMIF_
DATA[9]
EMIF_
DATA[10]
EMIF_
DATA[11]
EMIF_
DATA[12]
NC
NC
MIBSPI3
NCS[1]
N2HET1
[2]
5
4
N2HET1
[16]
N2HET1
[12]
EMIF_
ADDR[6]
EMIF_
ADDR[0]
NC
NC
NC
N2HET1
[21]
N2HET1
[23]
NC
NC
NC
NC
NC
EMIF_
nCAS
NC
NC
NC
NC
4
3
N2HET1
[29]
N2HET1
[22]
MIBSPI3
NCS[3]
SPI2
NENA
N2HET1
[11]
MIBSPI1
NCS[1]
MIBSPI1
NCS[2]
GIOA[6]
MIBSPI1
NCS[3]
EMIF_
CLK
EMIF_
CKE
N2HET1
[25]
SPI2
NCS[0]
EMIF_
nWAIT
EMIF_
nRAS
NC
NC
NC
N2HET1
[6]
3
2
VSS
MIBSPI3
NCS[2]
GIOA[1]
SPI2
SOMI
SPI2 CLK
GIOB[2]
GIOB[5]
CAN2TX
GIOB[6]
GIOB[1]
KELVIN_
GND
GIOB[0]
N2HET1
[13]
N2HET1
[20]
MIBSPI1
NCS[0]
NC
TEST
N2HET1
[1]
VSS
2
1
VSS
VSS
GIOA[2]
SPI2
SIMO
GIOA[3]
GIOB[7]
GIOB[4]
CAN2RX
N2HET1
[18]
OSCIN
OSCOUT
GIOA[7]
N2HET1
[15]
N2HET1
[24]
NC
N2HET1
[7]
N2HET1
[3]
VSS
VSS
1
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RM46L852
www.ti.com
SPNS185C –SEPTEMBER 2012–REVISED JUNE 2015
4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
Figure 4-2. ZWT Package Pinout. Top View
Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram.
Copyright © 2012–2015, Texas Instruments Incorporated Terminal Configuration and Functions 9
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