Datasheet
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 4.1 PGE QFP Package Pinout (144-Pin)
- 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
- 4.3 Terminal Functions
- 4.3.1 PGE Package
- 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.1.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.1.3 Enhanced Capture Modules (eCAP)
- 4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.1.6 General-Purpose Input / Output (GPIO)
- 4.3.1.7 Controller Area Network Controllers (DCAN)
- 4.3.1.8 Local Interconnect Network Interface Module (LIN)
- 4.3.1.9 Standard Serial Communication Interface (SCI)
- 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.1.11 Standard Serial Peripheral Interface (SPI)
- 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.1.13 Ethernet Controller
- 4.3.1.14 USB Host and Device Port Controller Interface
- 4.3.1.15 System Module Interface
- 4.3.1.16 Clock Inputs and Outputs
- 4.3.1.17 Test and Debug Modules Interface
- 4.3.1.18 Flash Supply and Test Pads
- 4.3.1.19 Supply for Core Logic: 1.2V nominal
- 4.3.1.20 Supply for I/O Cells: 3.3V nominal
- 4.3.1.21 Ground Reference for All Supplies Except VCCAD
- 4.3.2 ZWT Package
- 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.2.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.2.3 Enhanced Capture Modules (eCAP)
- 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.2.6 General-Purpose Input / Output (GPIO)
- 4.3.2.7 Controller Area Network Controllers (DCAN)
- 4.3.2.8 Local Interconnect Network Interface Module (LIN)
- 4.3.2.9 Standard Serial Communication Interface (SCI)
- 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.2.11 Standard Serial Peripheral Interface (SPI)
- 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.2.13 Ethernet Controller
- 4.3.2.14 USB Host and Device Port Controller Interface
- 4.3.2.15 External Memory Interface (EMIF)
- 4.3.2.16 System Module Interface
- 4.3.2.17 Clock Inputs and Outputs
- 4.3.2.18 Test and Debug Modules Interface
- 4.3.2.19 Flash Supply and Test Pads
- 4.3.2.20 Reserved
- 4.3.2.21 No Connects
- 4.3.2.22 Supply for Core Logic: 1.2V nominal
- 4.3.2.23 Supply for I/O Cells: 3.3V nominal
- 4.3.2.24 Ground Reference for All Supplies Except VCCAD
- 4.3.1 PGE Package
- 5 Specifications
- 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Device Recommended Operating Conditions
- 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
- 5.6 Wait States Required
- 5.7 Power Consumption Over Recommended Operating Conditions
- 5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions
- 5.9 Thermal Resistance Characteristics
- 5.10 Output Buffer Drive Strengths
- 5.11 Input Timings
- 5.12 Output Timings
- 5.13 Low-EMI Output Buffers
- 6 System Information and Electrical Specifications
- 6.1 Device Power Domains
- 6.2 Voltage Monitor Characteristics
- 6.3 Power Sequencing and Power On Reset
- 6.4 Warm Reset (nRST)
- 6.5 ARM Cortex-R4F CPU Information
- 6.6 Clocks
- 6.7 Clock Monitoring
- 6.8 Glitch Filters
- 6.9 Device Memory Map
- 6.10 Flash Memory
- 6.11 Tightly Coupled RAM Interface Module
- 6.12 Parity Protection for Accesses to Peripheral RAMs
- 6.13 On-Chip SRAM Initialization and Testing
- 6.14 External Memory Interface (EMIF)
- 6.15 Vectored Interrupt Manager
- 6.16 DMA Controller
- 6.17 Real Time Interrupt Module
- 6.18 Error Signaling Module
- 6.19 Reset / Abort / Error Sources
- 6.20 Digital Windowed Watchdog
- 6.21 Debug Subsystem
- 7 Peripheral Information and Electrical Specifications
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 7.1.1 ePWM Clocking and Reset
- 7.1.2 Synchronization of ePWMx Time Base Counters
- 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
- 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
- 7.1.5 ePWM Synchronization with External Devices
- 7.1.6 ePWM Trip Zones
- 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
- 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
- 7.2 Enhanced Capture Modules (eCAP)
- 7.3 Enhanced Quadrature Encoder (eQEP)
- 7.4 Multibuffered 12bit Analog-to-Digital Converter
- 7.5 General-Purpose Input/Output
- 7.6 Enhanced High-End Timer (N2HET)
- 7.7 Controller Area Network (DCAN)
- 7.8 Local Interconnect Network Interface (LIN)
- 7.9 Serial Communication Interface (SCI)
- 7.10 Inter-Integrated Circuit (I2C)
- 7.11 Multibuffered / Standard Serial Peripheral Interface
- 7.12 Ethernet Media Access Controller
- 7.13 Universal Serial Bus (USB) Host and Device Controllers
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
- 1518515_DS2.pdf

RM46L852
www.ti.com
SPNS185C –SEPTEMBER 2012–REVISED JUNE 2015
Table 6-21. Device Memory Map (continued)
FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE SIZE
START END
FRAME
Reads return zeros, writes have no
SPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B
effect
Reads return zeros, writes have no
MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B
effect
Reads return zeros, writes have no
SPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B
effect
Reads return zeros, writes have no
MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B
effect
System Modules Control Registers and Memories
DMA RAM PPCS0 0xFFF8_0000 0xFFF8_0FFF 4KB 4KB Abort
Wrap around for accesses to
VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB unimplemented address offsets
between 1KB and 4KB.
Flash Module PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort
eFuse Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort
Power
Management PPSE0 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort
Module (PMM)
Reads return zeros, writes have no
PCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B
effect
System Module -
Reads return zeros, writes have no
Frame 2 (see PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B
effect
SPNU514)
Reads return zeros, writes have no
PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B
effect
Generates address error interrupt, if
STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B
enabled
IOMM
Reads return zeros, writes have no
Multiplexing PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B
effect
Control Module
Reads return zeros, writes have no
DCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B
effect
Reads return zeros, writes have no
DMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1KB 1KB
effect
Reads return zeros, writes have no
DCC2 PPS5 0xFFFF_F400 0xFFFF_F4FF 256B 256B
effect
Reads return zeros, writes have no
ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B
effect
Reads return zeros, writes have no
CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B
effect
Reads return zeros, writes have no
RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B
effect
Reads return zeros, writes have no
RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B
effect
Reads return zeros, writes have no
RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B
effect
Reads return zeros, writes have no
VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B
effect
Reads return zeros, writes have no
VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B
effect
System Module -
Reads return zeros, writes have no
Frame 1 (see PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B
effect
SPNU514)
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