Datasheet
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 4.1 PGE QFP Package Pinout (144-Pin)
- 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
- 4.3 Terminal Functions
- 4.3.1 PGE Package
- 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.1.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.1.3 Enhanced Capture Modules (eCAP)
- 4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.1.6 General-Purpose Input / Output (GPIO)
- 4.3.1.7 Controller Area Network Controllers (DCAN)
- 4.3.1.8 Local Interconnect Network Interface Module (LIN)
- 4.3.1.9 Standard Serial Communication Interface (SCI)
- 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.1.11 Standard Serial Peripheral Interface (SPI)
- 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.1.13 Ethernet Controller
- 4.3.1.14 USB Host and Device Port Controller Interface
- 4.3.1.15 System Module Interface
- 4.3.1.16 Clock Inputs and Outputs
- 4.3.1.17 Test and Debug Modules Interface
- 4.3.1.18 Flash Supply and Test Pads
- 4.3.1.19 Supply for Core Logic: 1.2V nominal
- 4.3.1.20 Supply for I/O Cells: 3.3V nominal
- 4.3.1.21 Ground Reference for All Supplies Except VCCAD
- 4.3.2 ZWT Package
- 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.2.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.2.3 Enhanced Capture Modules (eCAP)
- 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.2.6 General-Purpose Input / Output (GPIO)
- 4.3.2.7 Controller Area Network Controllers (DCAN)
- 4.3.2.8 Local Interconnect Network Interface Module (LIN)
- 4.3.2.9 Standard Serial Communication Interface (SCI)
- 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.2.11 Standard Serial Peripheral Interface (SPI)
- 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.2.13 Ethernet Controller
- 4.3.2.14 USB Host and Device Port Controller Interface
- 4.3.2.15 External Memory Interface (EMIF)
- 4.3.2.16 System Module Interface
- 4.3.2.17 Clock Inputs and Outputs
- 4.3.2.18 Test and Debug Modules Interface
- 4.3.2.19 Flash Supply and Test Pads
- 4.3.2.20 Reserved
- 4.3.2.21 No Connects
- 4.3.2.22 Supply for Core Logic: 1.2V nominal
- 4.3.2.23 Supply for I/O Cells: 3.3V nominal
- 4.3.2.24 Ground Reference for All Supplies Except VCCAD
- 4.3.1 PGE Package
- 5 Specifications
- 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Device Recommended Operating Conditions
- 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
- 5.6 Wait States Required
- 5.7 Power Consumption Over Recommended Operating Conditions
- 5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions
- 5.9 Thermal Resistance Characteristics
- 5.10 Output Buffer Drive Strengths
- 5.11 Input Timings
- 5.12 Output Timings
- 5.13 Low-EMI Output Buffers
- 6 System Information and Electrical Specifications
- 6.1 Device Power Domains
- 6.2 Voltage Monitor Characteristics
- 6.3 Power Sequencing and Power On Reset
- 6.4 Warm Reset (nRST)
- 6.5 ARM Cortex-R4F CPU Information
- 6.6 Clocks
- 6.7 Clock Monitoring
- 6.8 Glitch Filters
- 6.9 Device Memory Map
- 6.10 Flash Memory
- 6.11 Tightly Coupled RAM Interface Module
- 6.12 Parity Protection for Accesses to Peripheral RAMs
- 6.13 On-Chip SRAM Initialization and Testing
- 6.14 External Memory Interface (EMIF)
- 6.15 Vectored Interrupt Manager
- 6.16 DMA Controller
- 6.17 Real Time Interrupt Module
- 6.18 Error Signaling Module
- 6.19 Reset / Abort / Error Sources
- 6.20 Digital Windowed Watchdog
- 6.21 Debug Subsystem
- 7 Peripheral Information and Electrical Specifications
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 7.1.1 ePWM Clocking and Reset
- 7.1.2 Synchronization of ePWMx Time Base Counters
- 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
- 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
- 7.1.5 ePWM Synchronization with External Devices
- 7.1.6 ePWM Trip Zones
- 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
- 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
- 7.2 Enhanced Capture Modules (eCAP)
- 7.3 Enhanced Quadrature Encoder (eQEP)
- 7.4 Multibuffered 12bit Analog-to-Digital Converter
- 7.5 General-Purpose Input/Output
- 7.6 Enhanced High-End Timer (N2HET)
- 7.7 Controller Area Network (DCAN)
- 7.8 Local Interconnect Network Interface (LIN)
- 7.9 Serial Communication Interface (SCI)
- 7.10 Inter-Integrated Circuit (I2C)
- 7.11 Multibuffered / Standard Serial Peripheral Interface
- 7.12 Ethernet Media Access Controller
- 7.13 Universal Serial Bus (USB) Host and Device Controllers
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
- 1518515_DS2.pdf

RM46L852
SPNS185C –SEPTEMBER 2012 –REVISED JUNE 2015
www.ti.com
Table 6-21. Device Memory Map (continued)
FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE SIZE
START END
FRAME
Wrap around for accesses to
unimplemented address offsets lower
MIBADC1 RAM 8KB
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
Look-Up Table for ADC1 wrapper.
PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB
Starts at address offset 0x2000 and
MibADC1 Look- ends at address offset 0x217F. Wrap
384B
Up Table around for accesses between offsets
0x0180 and 0x3FFF. Abort generated
for accesses beyond offset 0x4000.
Wrap around for accesses to
unimplemented address offsets lower
N2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128KB 16KB
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
Wrap around for accesses to
unimplemented address offsets lower
N2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
HTU2 RAM PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB Abort
HTU1 RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort
Debug Components
CoreSight Debug Reads return zeros, writes have no
CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB
ROM effect
Cortex-R4F Reads return zeros, writes have no
CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB
Debug effect
POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4KB 4KB Abort
Peripheral Control Registers
Reads return zeros, writes have no
HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B
effect
Reads return zeros, writes have no
HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B
effect
Reads return zeros, writes have no
N2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B
effect
Reads return zeros, writes have no
N2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B
effect
Reads return zeros, writes have no
GIO PS[16] 0xFFF7_BC00 0xFFF7_BDFF 512B 256B
effect
Reads return zeros, writes have no
MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B
effect
Reads return zeros, writes have no
MIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B
effect
Reads return zeros, writes have no
I2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B
effect
Reads return zeros, writes have no
DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B
effect
Reads return zeros, writes have no
DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B
effect
Reads return zeros, writes have no
DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B
effect
Reads return zeros, writes have no
LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B
effect
Reads return zeros, writes have no
SCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B
effect
Reads return zeros, writes have no
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B
effect
84 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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