Datasheet

RM46L852
www.ti.com SPNS185C –SEPTEMBER 2012–REVISED JUNE 2015
6.3 Power Sequencing and Power On Reset
6.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-
up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for
more details), core voltage rising above the minimum core supply threshold and the release of power-on
reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 6-3. Power-Up Phases
Oscillator start-up and validity check 1032 oscillator cycles
eFuse autoload 1160 oscillator cycles
Flash pump power-up 688 oscillator cycles
Flash bank power-up 617 oscillator cycles
Total 3497 oscillator cycles
The CPU reset is released at the end of the above sequence and fetches the first instruction from address
0x00000000.
6.3.2 Power-Down Sequence
The different supplies to the device can be powered down in any order.
6.3.3 Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
6.3.3.1 nPORRST Electrical and Timing Requirements
Table 6-4. Electrical Requirements for nPORRST
NO Parameter MIN MAX Unit
V
CCPORL
V
CC
low supply level when nPORRST must be active during power- 0.5 V
up
V
CCPORH
V
CC
high supply level when nPORRST must remain active during 1.14 V
power-up and become active during power down
V
CCIOPORL
V
CCIO
/ V
CCP
low supply level when nPORRST must be active during 1.1 V
power-up
V
CCIOPORH
V
CCIO
/ V
CCP
high supply level when nPORRST must remain active 3.0 V
during power-up and become active during power down
V
IL(PORRST)
Low-level input voltage of nPORRST V
CCIO
> 2.5V 0.2 * V
CCIO
V
Low-level input voltage of nPORRST V
CCIO
< 2.5V 0.5 V
3 t
su(PORRST)
Setup time, nPORRST active before V
CCIO
and V
CCP
> V
CCIOPORL
0 ms
during power-up
6 t
h(PORRST)
Hold time, nPORRST active after V
CC
> V
CCPORH
1 ms
7 t
su(PORRST)
Setup time, nPORRST active before V
CC
< V
CCPORH
during power 2 µs
down
8 t
h(PORRST)
Hold time, nPORRST active after V
CCIO
and V
CCP
> V
CCIOPORH
1 ms
9 t
h(PORRST)
Hold time, nPORRST active after V
CC
< V
CCPORL
0 ms
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