Datasheet

V
CCIO
V
IH
V
IH
V
IL
0
Input
t
pw
V
IL
RM46L852
SPNS185C –SEPTEMBER 2012 –REVISED JUNE 2015 www.ti.com
Table 5-5. Selectable 8 mA/2 mA Control
Signal Control Bit Address 8 mA 2 mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9] 0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10] 0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11]
(1)
0xFFF7 F668 0 1
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits
differ, SPI2PC9[11] determines the drive strength.
5.11 Input Timings
Figure 5-2. TTL-Level Inputs
Table 5-6. Timing Requirements for Inputs
(1)
Parameter MIN MAX Unit
t
pw
Input minimum pulse width t
c(VCLK)
+ 10
(2)
ns
t
in_slew
Time for input signal to go from V
IL
to V
IH
or from V
IH
to V
IL
1 ns
(1) t
c(VCLK)
= peripheral VBUS clock cycle time = 1 / f
(VCLK)
(2) The timing shown above is only valid for pin used in general-purpose input mode.
5.12 Output Timings
Table 5-7. Switching Characteristics for Output Timings versus Load Capacitance ©
L
)
Parameter MIN MAX Unit
Rise time, t
r
8 mA low EMI pins CL = 15 pF 2.5 ns
(see Table 5-4)
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, t
f
CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, t
r
4 mA low EMI pins CL = 15 pF 5.6 ns
(see Table 5-4)
CL = 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Fall time, t
f
CL = 15 pF 5.6 ns
CL= 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
58 Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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