Datasheet
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 4.1 PGE QFP Package Pinout (144-Pin)
- 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
- 4.3 Terminal Functions
- 4.3.1 PGE Package
- 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.1.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.1.3 Enhanced Capture Modules (eCAP)
- 4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.1.6 General-Purpose Input / Output (GPIO)
- 4.3.1.7 Controller Area Network Controllers (DCAN)
- 4.3.1.8 Local Interconnect Network Interface Module (LIN)
- 4.3.1.9 Standard Serial Communication Interface (SCI)
- 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.1.11 Standard Serial Peripheral Interface (SPI)
- 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.1.13 Ethernet Controller
- 4.3.1.14 USB Host and Device Port Controller Interface
- 4.3.1.15 System Module Interface
- 4.3.1.16 Clock Inputs and Outputs
- 4.3.1.17 Test and Debug Modules Interface
- 4.3.1.18 Flash Supply and Test Pads
- 4.3.1.19 Supply for Core Logic: 1.2V nominal
- 4.3.1.20 Supply for I/O Cells: 3.3V nominal
- 4.3.1.21 Ground Reference for All Supplies Except VCCAD
- 4.3.2 ZWT Package
- 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.2.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.2.3 Enhanced Capture Modules (eCAP)
- 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.2.6 General-Purpose Input / Output (GPIO)
- 4.3.2.7 Controller Area Network Controllers (DCAN)
- 4.3.2.8 Local Interconnect Network Interface Module (LIN)
- 4.3.2.9 Standard Serial Communication Interface (SCI)
- 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.2.11 Standard Serial Peripheral Interface (SPI)
- 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.2.13 Ethernet Controller
- 4.3.2.14 USB Host and Device Port Controller Interface
- 4.3.2.15 External Memory Interface (EMIF)
- 4.3.2.16 System Module Interface
- 4.3.2.17 Clock Inputs and Outputs
- 4.3.2.18 Test and Debug Modules Interface
- 4.3.2.19 Flash Supply and Test Pads
- 4.3.2.20 Reserved
- 4.3.2.21 No Connects
- 4.3.2.22 Supply for Core Logic: 1.2V nominal
- 4.3.2.23 Supply for I/O Cells: 3.3V nominal
- 4.3.2.24 Ground Reference for All Supplies Except VCCAD
- 4.3.1 PGE Package
- 5 Specifications
- 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Device Recommended Operating Conditions
- 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
- 5.6 Wait States Required
- 5.7 Power Consumption Over Recommended Operating Conditions
- 5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions
- 5.9 Thermal Resistance Characteristics
- 5.10 Output Buffer Drive Strengths
- 5.11 Input Timings
- 5.12 Output Timings
- 5.13 Low-EMI Output Buffers
- 6 System Information and Electrical Specifications
- 6.1 Device Power Domains
- 6.2 Voltage Monitor Characteristics
- 6.3 Power Sequencing and Power On Reset
- 6.4 Warm Reset (nRST)
- 6.5 ARM Cortex-R4F CPU Information
- 6.6 Clocks
- 6.7 Clock Monitoring
- 6.8 Glitch Filters
- 6.9 Device Memory Map
- 6.10 Flash Memory
- 6.11 Tightly Coupled RAM Interface Module
- 6.12 Parity Protection for Accesses to Peripheral RAMs
- 6.13 On-Chip SRAM Initialization and Testing
- 6.14 External Memory Interface (EMIF)
- 6.15 Vectored Interrupt Manager
- 6.16 DMA Controller
- 6.17 Real Time Interrupt Module
- 6.18 Error Signaling Module
- 6.19 Reset / Abort / Error Sources
- 6.20 Digital Windowed Watchdog
- 6.21 Debug Subsystem
- 7 Peripheral Information and Electrical Specifications
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 7.1.1 ePWM Clocking and Reset
- 7.1.2 Synchronization of ePWMx Time Base Counters
- 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
- 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
- 7.1.5 ePWM Synchronization with External Devices
- 7.1.6 ePWM Trip Zones
- 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
- 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
- 7.2 Enhanced Capture Modules (eCAP)
- 7.3 Enhanced Quadrature Encoder (eQEP)
- 7.4 Multibuffered 12bit Analog-to-Digital Converter
- 7.5 General-Purpose Input/Output
- 7.6 Enhanced High-End Timer (N2HET)
- 7.7 Controller Area Network (DCAN)
- 7.8 Local Interconnect Network Interface (LIN)
- 7.9 Serial Communication Interface (SCI)
- 7.10 Inter-Integrated Circuit (I2C)
- 7.11 Multibuffered / Standard Serial Peripheral Interface
- 7.12 Ethernet Media Access Controller
- 7.13 Universal Serial Bus (USB) Host and Device Controllers
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
- 1518515_DS2.pdf
Main Cross Bar: Arbitration and Prioritization Control
CRC
Peripheral Central Resource Bridge
Dual Cortex-R4F
CPUs in Lockstep
DCAN1
DCAN2
DCAN3
LIN
SCI
SPI4
64KB Flash
for EEPROM
Emulation
with ECC
MibSPI1
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MibSPI3
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MibSPI5
LIN_RX
LIN_TX
SCI_RX
SCI_TX
PMM
RTI
DCC1
DCC2
32K
32K
32K
192KB RAM
with ECC
IOMM
VIM
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
MibADC1 MibADC2
I2C
N2HET1
GIO
I2C_SCL
I2C_SDA
GIOB[7:0]
GIOA[7:0]
AD1EVT
AD1IN[7:0]
AD2EVT
# 2
# 3
# 5
# 1
# 2
# 1
always on
Core/RAM
RAM
Core
Color Legend for
Power Domains
SYS
nPORRST
nRST
ECLK
ESM
nERROR
1.25MB
Flash
with
ECC
32K
32K
32K
Switched
Central Resource
Switched Central Resource
N2HET2[18,16]
N2HET2[15:0]
N2HET1[31:0]
N2HET1_PIN_nDIS
N2HET2_PIN_nDIS
VSSAD
VCCAD
ADREFHI
ADREFLO
N2HET2
AD1IN[15:8] \
AD2IN[15:8]
AD1IN[23:16] \
AD2IN[7:0]
EMAC Slaves
MDIO
MII
MDCLK
MDIO
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
MII_CRS
MII_RXDV
MII_COL
EMIF
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[12:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nWAIT
eQEP
1,2
eQEPxA
eQEPxB
eQEPxS
eQEPxI
eCAP
1..6
eCAP[6:1]
ePWM
1..7
nTZ[3:1]
SYNCO
SYNCI
ePWMxA
ePWMxB
Device
Host
USB1.OVERCURRENT
USB1.RCV
USB1.VM
USB1.VP
USB1.PORTPOWER
USB1.SPEED
USB1.SUSPEND
USB1.TXDAT
USB1.TXEN
USB1.TXSE0
USB2.
USB2.RCV
USB2.VM
USB2.VP
USB2.
USB2.SPEED
USB2.SUSPEND
USB2.TXDAT
USB2.TXEN
USB2.TXSE0
OVERCURRENT
PORTPOWER
USB_FUNC.GZO
USB_FUNC.PUENO
USB_FUNC.PUENON
USB_FUNC.RXDI
USB_FUNC.RXDMI
USB_FUNC.RXDPI
USB_FUNC.SE0O
USB_FUNC.SUSPENDO
USB_FUNC.TXDO
USB_FUNC.VBUSI
USB Slaves
HTU1 HTU2
Switched
Central Resource
DMA POM
Switched
Central Resource
Switched
Central Resource
EMAC OHCI
MIBSPI5_CLK
RM46L852
SPNS185C –SEPTEMBER 2012–REVISED JUNE 2015
www.ti.com
1.4 Functional Block Diagram
NOTE
The block diagram reflects the 337BGA package. Some pins are multiplexed or not available
in the 144QFP. For details, see the respective terminal functions tables in Section 4.3.
Figure 1-1. Functional Block Diagram
4 Device Overview Copyright © 2012–2015, Texas Instruments Incorporated
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