Datasheet
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 4.1 PGE QFP Package Pinout (144-Pin)
- 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
- 4.3 Terminal Functions
- 4.3.1 PGE Package
- 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.1.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.1.3 Enhanced Capture Modules (eCAP)
- 4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.1.6 General-Purpose Input / Output (GPIO)
- 4.3.1.7 Controller Area Network Controllers (DCAN)
- 4.3.1.8 Local Interconnect Network Interface Module (LIN)
- 4.3.1.9 Standard Serial Communication Interface (SCI)
- 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.1.11 Standard Serial Peripheral Interface (SPI)
- 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.1.13 Ethernet Controller
- 4.3.1.14 USB Host and Device Port Controller Interface
- 4.3.1.15 System Module Interface
- 4.3.1.16 Clock Inputs and Outputs
- 4.3.1.17 Test and Debug Modules Interface
- 4.3.1.18 Flash Supply and Test Pads
- 4.3.1.19 Supply for Core Logic: 1.2V nominal
- 4.3.1.20 Supply for I/O Cells: 3.3V nominal
- 4.3.1.21 Ground Reference for All Supplies Except VCCAD
- 4.3.2 ZWT Package
- 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.2.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.2.3 Enhanced Capture Modules (eCAP)
- 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.2.6 General-Purpose Input / Output (GPIO)
- 4.3.2.7 Controller Area Network Controllers (DCAN)
- 4.3.2.8 Local Interconnect Network Interface Module (LIN)
- 4.3.2.9 Standard Serial Communication Interface (SCI)
- 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.2.11 Standard Serial Peripheral Interface (SPI)
- 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.2.13 Ethernet Controller
- 4.3.2.14 USB Host and Device Port Controller Interface
- 4.3.2.15 External Memory Interface (EMIF)
- 4.3.2.16 System Module Interface
- 4.3.2.17 Clock Inputs and Outputs
- 4.3.2.18 Test and Debug Modules Interface
- 4.3.2.19 Flash Supply and Test Pads
- 4.3.2.20 Reserved
- 4.3.2.21 No Connects
- 4.3.2.22 Supply for Core Logic: 1.2V nominal
- 4.3.2.23 Supply for I/O Cells: 3.3V nominal
- 4.3.2.24 Ground Reference for All Supplies Except VCCAD
- 4.3.1 PGE Package
- 5 Specifications
- 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Device Recommended Operating Conditions
- 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
- 5.6 Wait States Required
- 5.7 Power Consumption Over Recommended Operating Conditions
- 5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions
- 5.9 Thermal Resistance Characteristics
- 5.10 Output Buffer Drive Strengths
- 5.11 Input Timings
- 5.12 Output Timings
- 5.13 Low-EMI Output Buffers
- 6 System Information and Electrical Specifications
- 6.1 Device Power Domains
- 6.2 Voltage Monitor Characteristics
- 6.3 Power Sequencing and Power On Reset
- 6.4 Warm Reset (nRST)
- 6.5 ARM Cortex-R4F CPU Information
- 6.6 Clocks
- 6.7 Clock Monitoring
- 6.8 Glitch Filters
- 6.9 Device Memory Map
- 6.10 Flash Memory
- 6.11 Tightly Coupled RAM Interface Module
- 6.12 Parity Protection for Accesses to Peripheral RAMs
- 6.13 On-Chip SRAM Initialization and Testing
- 6.14 External Memory Interface (EMIF)
- 6.15 Vectored Interrupt Manager
- 6.16 DMA Controller
- 6.17 Real Time Interrupt Module
- 6.18 Error Signaling Module
- 6.19 Reset / Abort / Error Sources
- 6.20 Digital Windowed Watchdog
- 6.21 Debug Subsystem
- 7 Peripheral Information and Electrical Specifications
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 7.1.1 ePWM Clocking and Reset
- 7.1.2 Synchronization of ePWMx Time Base Counters
- 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
- 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
- 7.1.5 ePWM Synchronization with External Devices
- 7.1.6 ePWM Trip Zones
- 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
- 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
- 7.2 Enhanced Capture Modules (eCAP)
- 7.3 Enhanced Quadrature Encoder (eQEP)
- 7.4 Multibuffered 12bit Analog-to-Digital Converter
- 7.5 General-Purpose Input/Output
- 7.6 Enhanced High-End Timer (N2HET)
- 7.7 Controller Area Network (DCAN)
- 7.8 Local Interconnect Network Interface (LIN)
- 7.9 Serial Communication Interface (SCI)
- 7.10 Inter-Integrated Circuit (I2C)
- 7.11 Multibuffered / Standard Serial Peripheral Interface
- 7.12 Ethernet Media Access Controller
- 7.13 Universal Serial Bus (USB) Host and Device Controllers
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
- 1518515_DS2.pdf
RM46L852
www.ti.com
SPNS185C –SEPTEMBER 2012–REVISED JUNE 2015
The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer
RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. Each MibADC
supports three separate groupings of channels. Each group can be converted once when triggered or
configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility
with older devices or faster conversion time is desired. MibADC1 also supports the use of external analog
multiplexers.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three
DCANs, one I
2
C, one Ethernet, and one USB module. The SPI provides a convenient method of serial
high-speed communications between similar shift-register type devices. The LIN supports the Local
Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-
Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a
serial, multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh
environments (for example, automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The Ethernet module supports MII, RMII, and MDIO interfaces.
The USB module includes a 2-port USB host controller that is revision 2.0-compatible, based on the OHCI
specification for USB, release 1.0. The USB module also includes a USB device controller compatible with
the USB specification revision 2.0 and USB specification revision 1.1.
The I2C module is a multimaster communication module providing an interface between the
microcontroller and an I
2
C-compatible device through the I
2
C serial bus. The I
2
C supports speeds of 100
and 400 Kbps.
A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the
mapping between the available clock sources and the device clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of
the device operating frequency.
The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests, and parity
protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or
external error pin (ball) is triggered when a fault is detected. The nERROR terminal can be monitored
externally as an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous
memories or other slave devices.
A Parameter Overlay Module (POM) enhances the calibration capabilities of application code. The POM
can reroute flash accesses to internal memory or to the EMIF, thus avoiding the reprogramming steps
necessary for parameter updates in flash.
With integrated safety features and a wide choice of communication and control peripherals, the
RM46L852 device is an ideal solution for high-performance real-time control applications with safety-
critical requirements.
Table 1-1. Device Information
(1)
PART NUMBER PACKAGE BODY SIZE
RM46L852ZWT NFBGA (337) 16.0 mm × 16.0 mm
RM46L852PGE LQFP (144) 20.0 mm × 20.0 mm
(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.
Copyright © 2012–2015, Texas Instruments Incorporated Device Overview 3
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