Datasheet
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 4.1 PGE QFP Package Pinout (144-Pin)
- 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
- 4.3 Terminal Functions
- 4.3.1 PGE Package
- 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.1.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.1.3 Enhanced Capture Modules (eCAP)
- 4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.1.6 General-Purpose Input / Output (GPIO)
- 4.3.1.7 Controller Area Network Controllers (DCAN)
- 4.3.1.8 Local Interconnect Network Interface Module (LIN)
- 4.3.1.9 Standard Serial Communication Interface (SCI)
- 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.1.11 Standard Serial Peripheral Interface (SPI)
- 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.1.13 Ethernet Controller
- 4.3.1.14 USB Host and Device Port Controller Interface
- 4.3.1.15 System Module Interface
- 4.3.1.16 Clock Inputs and Outputs
- 4.3.1.17 Test and Debug Modules Interface
- 4.3.1.18 Flash Supply and Test Pads
- 4.3.1.19 Supply for Core Logic: 1.2V nominal
- 4.3.1.20 Supply for I/O Cells: 3.3V nominal
- 4.3.1.21 Ground Reference for All Supplies Except VCCAD
- 4.3.2 ZWT Package
- 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.2.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.2.3 Enhanced Capture Modules (eCAP)
- 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.2.6 General-Purpose Input / Output (GPIO)
- 4.3.2.7 Controller Area Network Controllers (DCAN)
- 4.3.2.8 Local Interconnect Network Interface Module (LIN)
- 4.3.2.9 Standard Serial Communication Interface (SCI)
- 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.2.11 Standard Serial Peripheral Interface (SPI)
- 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.2.13 Ethernet Controller
- 4.3.2.14 USB Host and Device Port Controller Interface
- 4.3.2.15 External Memory Interface (EMIF)
- 4.3.2.16 System Module Interface
- 4.3.2.17 Clock Inputs and Outputs
- 4.3.2.18 Test and Debug Modules Interface
- 4.3.2.19 Flash Supply and Test Pads
- 4.3.2.20 Reserved
- 4.3.2.21 No Connects
- 4.3.2.22 Supply for Core Logic: 1.2V nominal
- 4.3.2.23 Supply for I/O Cells: 3.3V nominal
- 4.3.2.24 Ground Reference for All Supplies Except VCCAD
- 4.3.1 PGE Package
- 5 Specifications
- 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Device Recommended Operating Conditions
- 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
- 5.6 Wait States Required
- 5.7 Power Consumption Over Recommended Operating Conditions
- 5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions
- 5.9 Thermal Resistance Characteristics
- 5.10 Output Buffer Drive Strengths
- 5.11 Input Timings
- 5.12 Output Timings
- 5.13 Low-EMI Output Buffers
- 6 System Information and Electrical Specifications
- 6.1 Device Power Domains
- 6.2 Voltage Monitor Characteristics
- 6.3 Power Sequencing and Power On Reset
- 6.4 Warm Reset (nRST)
- 6.5 ARM Cortex-R4F CPU Information
- 6.6 Clocks
- 6.7 Clock Monitoring
- 6.8 Glitch Filters
- 6.9 Device Memory Map
- 6.10 Flash Memory
- 6.11 Tightly Coupled RAM Interface Module
- 6.12 Parity Protection for Accesses to Peripheral RAMs
- 6.13 On-Chip SRAM Initialization and Testing
- 6.14 External Memory Interface (EMIF)
- 6.15 Vectored Interrupt Manager
- 6.16 DMA Controller
- 6.17 Real Time Interrupt Module
- 6.18 Error Signaling Module
- 6.19 Reset / Abort / Error Sources
- 6.20 Digital Windowed Watchdog
- 6.21 Debug Subsystem
- 7 Peripheral Information and Electrical Specifications
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 7.1.1 ePWM Clocking and Reset
- 7.1.2 Synchronization of ePWMx Time Base Counters
- 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
- 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
- 7.1.5 ePWM Synchronization with External Devices
- 7.1.6 ePWM Trip Zones
- 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
- 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
- 7.2 Enhanced Capture Modules (eCAP)
- 7.3 Enhanced Quadrature Encoder (eQEP)
- 7.4 Multibuffered 12bit Analog-to-Digital Converter
- 7.5 General-Purpose Input/Output
- 7.6 Enhanced High-End Timer (N2HET)
- 7.7 Controller Area Network (DCAN)
- 7.8 Local Interconnect Network Interface (LIN)
- 7.9 Serial Communication Interface (SCI)
- 7.10 Inter-Integrated Circuit (I2C)
- 7.11 Multibuffered / Standard Serial Peripheral Interface
- 7.12 Ethernet Media Access Controller
- 7.13 Universal Serial Bus (USB) Host and Device Controllers
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
- 1518515_DS2.pdf
Meet the
Hercules RM46x
LaunchPad
Development Kit
Part Number: LAUNCHXL2-RM46
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DRV8301 Motor Driver
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SPI CS
SPI CS
SPI CS
GND
GPIO
(!)
GPIO
(!)
GPIO**
RST
SPI
MOSI
MISO
GPIO
(!)
GPIO
(!)
GPIO
(!)
PWM
+3.3V
Analog In
UART
RX ( MCU)
TX ( MCU)
GPIO
(!)
Analog In
SPI CLK
GPIO
(!)
I2C
SCL
SDA
+5V
Analog In
Analog In
Analog In
Analog In
Analog In
Analog In
GND
Reserved
Reserved
Timer
Timer
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PWM
PWM
PWM
PWM
(!)
(!)
(!)
(!)
(!)
(!)
(!)
(!)
(!)
(!)
SPI CS
SPI CS
SPI CS
GND
GPIO
(!)
GPIO
(!)
GPIO**
RST
SPI
MOSI
MISO
GPIO
(!)
GPIO
(!)
GPIO
(!)
PWM
+3.3V
Analog In
UART
RX ( MCU)
TX ( MCU)
GPIO
(!)
Analog In
SPI CLK
GPIO
(!)
I2C
SCL
SDA
+5V
Analog In
Analog In
Analog In
Analog In
Analog In
Analog In
GND
Reserved
Reserved
Timer
Timer
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PWM
PWM
PWM
PWM
(!)
(!)
(!)
(!)
(!)
(!)
(!)
(!)
(!)
(!)
BoosterPack standard
LAUNCHXL2-RM46 Pin map
LAUNCHXL2-RM46 Pin map
Resources
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{
Code examples
Open Source Design Files
Documentation
Example projects
Videos
Tutorials
Other TI products
Below are the pins exposed @ the 2x BoosterPack connector sites.
Mapping to the booster pack standard is shown. In some cases a function can be either a GIO or another function,
and may be listed twice (color coded as both GIO and again as the function). Additional functions beyond the
booster pack standard may be available. For details consult the launchpad schematic.
(!) Denotes I/O pins that are interrupt-capable.
BoosterPack standard
LAUNCHXL2-RM46 Pin map
LAUNCHXL2-RM46 Pin map
LAUNCHXL2-RM46
+3.3V
AD1[16]/AD2[0]
SCITX
SCIRX
MIBSPI3CLK
N2HET1[4]
N2HET1[9]
GIOA[7]
(!)
AD1[17]/AD2[1]
GIOA[6]
(!)
GND
AD1[0]
AD1[7]
AD1[18]/AD2[2]
AD1[19]/AD2[3]
AD1[20]/AD2[4]
AD1[21]/AD2[5]
+3.3V
AD1[9]/AD2[9]
LIN1TX
LIN1RX
MIBSPI1CLK
N2HET1[24]
N2HET1[26]
GIOB[2]
(!)
AD1[1]
N2HET1[31]
(!)
+5V
GND
AD1[3]
AD1[2]
AD1[10]/AD2[10]
AD1[11]/AD2[11]
AD1[12]/AD2[12]
AD1[4]
P50
P51
GND
nRESET
MIBSPI1SIMO
MIBSPI1SOMI
N2HET2[8]
N2HET1[1]
(!)
MIBSPI1NCS[0]
MIBSPI1SOMI[1]
MIBSPI5SIMO[0]
MIBSPI5SOMI[0]
MIBSPI1NCS[1]
N2HET1[17]
(!)
MIBSPI1NCS[2]
N2HET1[19]
(!)
N2HET1[10]
(!)
N2HET1[10]
GIOB[0]
AD1EVT
MIBSPI5CLK
MIBSPI5NENA
ECAP5
N2HET1[28]
N2HET1[28]
(!)
N2HET1[8]
N2HET1[8]
(!)
N2HET1[23]
N2HET1[23]
(!)
N2HET1[11]
N2HET2[18]
(!)
GIOB[1]
(!)
(!)
N2HET1[20]
(!)
EPWM6B
EPWM6A
N2HET1[18]
(!)
N2HET1[30]
N2HET1[30]
(!)
N2HET1[12]
N2HET1[12]
(!)
GIOA[5]
(!)
GIOA[2]
(!)
GIOA[0]
(!)
GIOA[1]
(!)
N2HET1[14]
(!)
N2HET1[14]
N2HET1[16]
N2HET1[16]
(!)
GND
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI3NCS[2]
N2HET1[27]
(!)
MIBSPI3NCS[3]
N2HET1[29]
(!)
N2HET1[22]
N2HET1[22]
(!)
MIBSPI3NCS[1]
N2HET1[25]
(!)
GIOB[3]
(!)
nRESET
GIOB[2]
(!)
+5V
JP2 JP3
JP4 JP5
J2,J3
J4,J5
J6,J7
J8,J9
When using some BoosterPacks, JP2,3,4, or 5 may need to be removed. For example, using this LaunchPad with BoosterPack BOOSTXL-DRV8301 that includes a
3.3V regulator. To avoid conflict between the LaunchPad's 3.3V regulator and the regulator on the BoosterPack, JP2 (or JP4) should be removed.