Datasheet

1
2
3
RMII_REFCLK
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RX_ER
6
7
11
9
8
5
4
10
5
RM46L852
SPNS185C –SEPTEMBER 2012 –REVISED JUNE 2015 www.ti.com
7.12.2 Ethernet RMII Electrical and Timing Specifications
Figure 7-24. RMII Timing Diagram
Table 7-39. Timing Requirements for EMAC RMII Receive and RMII_REFCLK
NO. MIN NOM MAX UNIT
1 t
c(REFCLK)
Cycle time, RMII_REFCLK 20 ns
2 t
w(REFCLKH)
Pulse width, RMII_REFCLK high 7 13 ns
3 t
w(REFCLKL)
Pulse width, RMII_REFCLK low 7 13 ns
6 t
su(RXD-REFCLK)
Input setup time, RMII_RXD[1:0] valid before RMII_REFCLK high 4 ns
7 t
h(REFCLK-RXD)
Input hold time, RMII_RXD[1:0] valid after RMII_REFCLK high 2 ns
8 t
su(CRSDV-REFCLK)
Input setup time, RMII_CRS_DV valid before RMII_REFCLK high 4 ns
9 t
h(REFCLK-CRSDV)
Input hold time, RMII_CRS_DV valid after RMII_REFCLK high 2 ns
10 t
su(RXER-REFCLK)
Input setup time, RMII_RX_ER valid before RMII_REFCLK high 4 ns
11 t
h(REFCLK-RXER)
Input hold time, RMII_RX_ER valid after RMII_REFCLK high 2 ns
Table 7-40. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit
NO. PARAMETER MIN MAX UNIT
4 t
d(REFCLK-TXD)
Output delay time, RMII_REFCLK high to RMII_TXD[1:0] valid 2 ns
5 t
d(REFCLK-TXEN)
Output delay time, RMII_REFCLK high to RMII_TXEN valid 2 ns
170 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated
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