Datasheet

ID Decode Addr Decode

MasterID Address/Control

MasterID Protection Register N

Peripheral Select N

PCRx

TMS570LC4357

SPNS195C –FEBRUARY 2014–REVISED JUNE 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TMS570LC4357

6.9.5 MasterID to PCRx

The MasterID associated with each master port on the Peripheral Interconnect Subsystem contains a 4-bit

value. The MasterID is passed along with the address and control signals to three PCR modules. PCR

decodes the address and control signals to select the peripheral. In addition, it decodes this 4-bit MasterID

value to perform memory protection. With 4-bit of MasterID, it allows the PCR to distinguish among 16

different masters to allow or disallow access to a given peripheral. Associated with each peripheral a 16-

bit MasterID access protection register is defined. Each bit grants or denies the permission of the

corresponding binary coded decimal MasterID. For example, if bit 5 of the access permission register is

set, it grants MasterID 5 to access the peripheral. If bit 7 is clear, it denies MasterID 7 to access the

peripheral. Figure 6-10 shows the MasterID filtering scheme. Table 6-27 lists the MasterID of each master,

which can access the PCRx.

Figure 6-10. PCR MasterID Filtering

6.9.6 CPU Interconnect Subsystem SDC MMR Port

The CPU Interconnect Subsystem SDC MMR Port is a special slave to the Peripheral Interconnect

Subsystem. It is memory mapped at starting address of 0xFA00_0000. Various status registers pertaining

to the diagnostics of the CPU Interconnect Subsystem can be access through this slave port. The CPU

Interconnect Subsystem contains built-in hardware diagnostic checkers which will constantly watch

transactions flowing through the interconnect. There is a checker for each master and slave attached to

the CPU Interconnect Subsystem. The checker checks the expected behavior against the generated

behavior by the interconnect. For example, if the CPU issues a burst read request to the flash, the

checker will ensure that the expected behavior is indeed a burst read request to the proper slave module.

If the interconnects generates a transaction which is not a read, or not a burst or not to the flash as the

destination, then the checker will flag it one of the registers. The detected error will also be signaled to the

ESM module. Refer to the Interconnect chapter of the TRM SPNU563 for details on the registers.