Datasheet

96
TMS570LC4357
SPNS195C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 6-25. Module Registers / Memories Memory Map (continued)
TARGET NAME
MEMORY
SELECT
ADDRESS RANGE
FRAME
SIZE
ACTUAL
SIZE
RESPONSE FOR
ACCESS TO
UNIMPLEMENTED
LOCATIONS IN
FRAME
START END
VIM
PPS[7] 0xFFFF_FD00 0xFFFF_FEFF 512B 512B
Reads return zeros,
writes have no effect
System Module - Frame 1 (see
the TRM SPNU563)
PPS[7] 0xFFFF_FF00 0xFFFF_FFFF 256B 256B
Reads return zeros,
writes have no effect
6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an
imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to
handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program
status register (CPSR).