Datasheet

TMS570LC4357

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SPNS195C –FEBRUARY 2014–REVISED JUNE 2016

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2 Revision History

This data manual revision history highlights the technical changes made to the SPNS195B device-specific

data manual to make it an SPNS195C revision. These devices are now in the Production Data (PD) stage

of development.

Changes from January 31, 2016 to June 25, 2016 (from B Revision (January 2016) to C Revision) Page

• Global: Updated/Changed the product status from Product Preview to Production Data................................... 1

• Table 6-13 (LPO Specifications): Updated/Changed LPO - HF oscillator, Untrimmed frequency TYP value from

"9.6" to "9" MHz ..................................................................................................................... 78

• Section 6.9.3 (Special Consideration for CPU Access Errors Resulting in Imprecise Aborts): Add missing

subsection............................................................................................................................ 96

• Section 6.14.1 (External Memory Interface (EMIF), Features): Updated/Changed the EMIF asynchronous

memory maximum addressable size from "32KB" to "16MB" each......................................................... 109

• Section 6.14 (External Memory Interface (EMIF)): Added 32-bit access note using a 16-bit EMIF interface. ........ 109

• Added "Commonly caused by ..." statement for clarification................................................................. 131

• Table 6-56 (ETMTRACECLK Timing): Restructured timing table formatting to standards............................... 149

• Table 7-7, (eCAPx Clock Enable Control): Updated/Changed "ePWM" to "eCAP" in the MODULE INSTANCE

column............................................................................................................................... 162

• Table 7-11, (eQEPx Clock Enable Control): Updated/Changed "ePWM" to "eQEP" in the MODULE INSTANCE

column............................................................................................................................... 164

• Table 7-16 (MibADC1 Event Trigger Selection): Added lead-in paragraph referencing the able ....................... 166

• (MibADC1 Event Trigger Hookup): NOTE: Added new paragraph ......................................................... 168

• Table 7-17 (MibADC2 Event Trigger Selection): Added lead-in paragraph referencing the able ....................... 168

• Section 7.4.2.3 (Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules):

Updated/Changed the names of the four ePWM signals that event trigger the ADC .................................... 170

• Table 7-22 (MibADC Operating Characteristics Over 3.0 V to 3.6 V Operating Conditions): Updated/Changed

the 10- and 12-bit mode formulas to be superscript power of 2 values .................................................... 175

• Table 7-23 (MibADC Operating Characteristics Over 3.6 V to 5.25 V Operating Conditions): Updated/Changed

the 10- and 12-bit mode formulas to be superscript power of 2 values .................................................... 175