Datasheet

PCR
ROM
Interface
ESM
ROM
Clock Controller
FSM
and
Sequence
Controller
COMP
BLK2
COMP
BLK1
nHET_Reset
misr_out
Global Clock
Controller
STC
STC REG
BLOCK
STC_BYPASS/
ATE Interface
VBUSP
Inteface
Test
Controller
DBIST
CNTRL2
DBIST
CNTRL1
nHET1
nHET2
misr_out
www.ti.com General Description
Figure 10-3. STC2 - Segment 0 Redundant Architecture (Parallel Mode)
425
SPNU563–May 2014 Self-Test Controller (STC) Module
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